From nobody Sat Feb 7 04:40:38 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B409F221277 for ; Fri, 16 Jan 2026 12:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768568286; cv=pass; b=sFkFxhYFGtOh8xiJPp1Bazv5tVL3hKHYQDMUy8ykYafQjVarDLoYivVu3I0iXCrygLM0YSFlvh15HyO34KyKqArSfn7x00g/VEdUYKRIdLTxpIl0OHmJUiGeQ0t6DMEmRmbsX1kZpLoRyRxIkfgYQyD+bc5UPWFGvHGTpWc67Dg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768568286; c=relaxed/simple; bh=NU3WMZrBWfT7gMgh/ChFpiRuUuIc/JYVhuCrMD+wSSc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EnnrIca2KoWjl1mU8WhCapA4ghpeGt5Iyz7bucAOgNHdgFO7FnucD3Loxg6tpLJDCFPAiGS9MXLlxcGRezVuQxjuNvgmxZ8el2LOt/WCDQH01lsShPA/PdytWAEhnC6K2YBYqn0fCL9u4f4Qa4eAupPC0+eduGbyScD2AWaY53Q= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=f+gC34Au; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="f+gC34Au" ARC-Seal: i=1; a=rsa-sha256; t=1768568270; cv=none; d=zohomail.com; s=zohoarc; b=WSJP/yiH7VxKbkhjiiIh1pQCXWeVuS2LnIZNFL5IBH9C84NJyok5N3Z9EH9tISKhbY1CAOcSFPrcaAm8QdN86lIF5aXc8JxdWAppR9PF1xtuaZDrX+LhF/gDjGOiCSeZyojqJI1r/1E4w9Ys6sPJlyZ2M5+eSAfHrGZtxvmApLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1768568270; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=7Vs6Hx5M5iOCZHlPNzxvtAfQld9Y5HN4gfBASmzYMnk=; b=SEb9lC+yzEShEJoVVHNKx43Rt3NRtdPv+0eIAdomoN0K+eRnvxbV9+O0eJ4rIBI9KPft1tzi113EZPlPX2rBcgscyiyGbLHkuNJ0Z1l1UdWmGymn4Xu07ACGARkMml6ahzaP2x54wQK5Z3nqirmwMvZnXsRBFOcpXQ+9K1pjzMM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768568270; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=7Vs6Hx5M5iOCZHlPNzxvtAfQld9Y5HN4gfBASmzYMnk=; b=f+gC34AuvCeGoZ/o1xqrTOP+x5gH3NaKyVolXbYc6XqY28XV6wRJQptkGfnjgluZ 12GcOG3UZLtYU6q5y1iuCuo463qyiFu5rutmpSi3KPnQeZwI4CVRmHJ9avt+gN4yJvF 8TpcRI1Zq2NrVT5v2DQu9ablNC8eg4HawKiOhWFk= Received: by mx.zohomail.com with SMTPS id 1768568269688536.57292235551; Fri, 16 Jan 2026 04:57:49 -0800 (PST) From: Nicolas Frattaroli Date: Fri, 16 Jan 2026 13:57:30 +0100 Subject: [PATCH v10 1/4] drm/panthor: Rework panthor_irq::suspended into panthor_irq::state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260116-panthor-tracepoints-v10-1-d925986e3d1b@collabora.com> References: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> In-Reply-To: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chia-I Wu , Karunika Choo Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 To deal with the threaded interrupt handler and a suspend action overlapping, the boolean panthor_irq::suspended is not sufficient. Rework it into taking several different values depending on the current state, and check it and set it within the IRQ helper functions. Co-developed-by: Boris Brezillon Signed-off-by: Boris Brezillon Signed-off-by: Nicolas Frattaroli Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panthor/panthor_device.h | 35 +++++++++++++++++++++++++---= ---- 1 file changed, 28 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index f35e52b9546a..8597b388cc40 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -61,6 +61,17 @@ enum panthor_device_pm_state { PANTHOR_DEVICE_PM_STATE_SUSPENDING, }; =20 +enum panthor_irq_state { + /** @PANTHOR_IRQ_STATE_ACTIVE: IRQ is active and ready to process events.= */ + PANTHOR_IRQ_STATE_ACTIVE =3D 0, + /** @PANTHOR_IRQ_STATE_PROCESSING: IRQ is currently processing events. */ + PANTHOR_IRQ_STATE_PROCESSING, + /** @PANTHOR_IRQ_STATE_SUSPENDED: IRQ is suspended. */ + PANTHOR_IRQ_STATE_SUSPENDED, + /** @PANTHOR_IRQ_STATE_SUSPENDING: IRQ is being suspended. */ + PANTHOR_IRQ_STATE_SUSPENDING, +}; + /** * struct panthor_irq - IRQ data * @@ -76,8 +87,8 @@ struct panthor_irq { /** @mask: Current mask being applied to xxx_INT_MASK. */ u32 mask; =20 - /** @suspended: Set to true when the IRQ is suspended. */ - atomic_t suspended; + /** @state: one of &enum panthor_irq_state reflecting the current state. = */ + atomic_t state; }; =20 /** @@ -409,12 +420,17 @@ static irqreturn_t panthor_ ## __name ## _irq_raw_han= dler(int irq, void *data) { \ struct panthor_irq *pirq =3D data; \ struct panthor_device *ptdev =3D pirq->ptdev; \ + enum panthor_irq_state old_state; \ \ - if (atomic_read(&pirq->suspended)) \ - return IRQ_NONE; \ if (!gpu_read(ptdev, __reg_prefix ## _INT_STAT)) \ return IRQ_NONE; \ \ + old_state =3D atomic_cmpxchg(&pirq->state, \ + PANTHOR_IRQ_STATE_ACTIVE, \ + PANTHOR_IRQ_STATE_PROCESSING); \ + if (old_state !=3D PANTHOR_IRQ_STATE_ACTIVE) \ + return IRQ_NONE; \ + \ gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \ return IRQ_WAKE_THREAD; \ } \ @@ -423,6 +439,7 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded_= handler(int irq, void *da { \ struct panthor_irq *pirq =3D data; \ struct panthor_device *ptdev =3D pirq->ptdev; \ + enum panthor_irq_state old_state; \ irqreturn_t ret =3D IRQ_NONE; \ \ while (true) { \ @@ -435,7 +452,10 @@ static irqreturn_t panthor_ ## __name ## _irq_threaded= _handler(int irq, void *da ret =3D IRQ_HANDLED; \ } \ \ - if (!atomic_read(&pirq->suspended)) \ + old_state =3D atomic_cmpxchg(&pirq->state, \ + PANTHOR_IRQ_STATE_PROCESSING, \ + PANTHOR_IRQ_STATE_ACTIVE); \ + if (old_state =3D=3D PANTHOR_IRQ_STATE_PROCESSING) \ gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \ \ return ret; \ @@ -445,14 +465,15 @@ static inline void panthor_ ## __name ## _irq_suspend= (struct panthor_irq *pirq) { \ pirq->mask =3D 0; \ gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \ + atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDING); \ synchronize_irq(pirq->irq); \ - atomic_set(&pirq->suspended, true); \ + atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDED); \ } \ \ static inline void panthor_ ## __name ## _irq_resume(struct panthor_irq *p= irq, u32 mask) \ { \ - atomic_set(&pirq->suspended, false); \ pirq->mask =3D mask; \ + atomic_set(&pirq->state, PANTHOR_IRQ_STATE_ACTIVE); \ gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, mask); \ gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, mask); \ } \ --=20 2.52.0 From nobody Sat Feb 7 04:40:38 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8FE621ABC9 for ; Fri, 16 Jan 2026 12:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768568295; cv=pass; b=APwx1+p9q1u4i3lhzHtSZqG4a4pmAqSBU7vmvKLaONYT5uKeylrFxvUZa/4Jrqrv0vUjbsHxAaxo6AB5BAF7ZV6RC1tS7/9rNppjiyBYIU86nCF4hsfygAeNMoLcII1g5EEojSNKjouXE3zaSkkIjAuTX3pkWzgH7vMxz5Y8PyM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768568295; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=lF286FRMXFvQsxuQs94ivqkIwPtQ7dRPUcQzy1QhnY8=; b=ehv28S3be7i3nu5YEchqhd+K9W83jF83gW7alKHnXtsrfHo0wyLEzz4JkvuOdFk8 nZEDY4uxW/ihp7RBw6DixXdNCl38cHTM555PAV0t9WyHZHGFaOxDMfz1fQstHoz4Y6G gkI9arivy1hq9u94aWi94+68oeUXqB4X9plg/RKM= Received: by mx.zohomail.com with SMTPS id 1768568273708418.44415252090823; Fri, 16 Jan 2026 04:57:53 -0800 (PST) From: Nicolas Frattaroli Date: Fri, 16 Jan 2026 13:57:31 +0100 Subject: [PATCH v10 2/4] drm/panthor: Extend IRQ helpers for mask modification/restoration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260116-panthor-tracepoints-v10-2-d925986e3d1b@collabora.com> References: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> In-Reply-To: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chia-I Wu , Karunika Choo Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 The current IRQ helpers do not guarantee mutual exclusion that covers the entire transaction from accessing the mask member and modifying the mask register. This makes it hard, if not impossible, to implement mask modification helpers that may change one of these outside the normal suspend/resume/isr code paths. Add a spinlock to struct panthor_irq that protects both the mask member and register. Acquire it in all code paths that access these, but drop it before processing the threaded handler function. Then, add the aforementioned new helpers: enable_events, and disable_events. They work by ORing and NANDing the mask bits. resume is changed to no longer have a mask passed, as pirq->mask is supposed to be the user-requested mask now, rather than a mirror of the INT_MASK register contents. Users of the resume helper are adjusted accordingly, including a rather painful refactor in panthor_mmu.c. In panthor_mmu.c, the bespoke mask modification is excised, and replaced with enable_events/disable_events in as_enable/as_disable. Co-developed-by: Boris Brezillon Signed-off-by: Boris Brezillon Signed-off-by: Nicolas Frattaroli Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panthor/panthor_device.h | 86 ++++++++++++++++++++++++++--= ---- drivers/gpu/drm/panthor/panthor_fw.c | 3 +- drivers/gpu/drm/panthor/panthor_gpu.c | 2 +- drivers/gpu/drm/panthor/panthor_mmu.c | 47 ++++++++--------- drivers/gpu/drm/panthor/panthor_pwr.c | 2 +- 5 files changed, 98 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index 8597b388cc40..8664adb1febf 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -84,9 +84,19 @@ struct panthor_irq { /** @irq: IRQ number. */ int irq; =20 - /** @mask: Current mask being applied to xxx_INT_MASK. */ + /** @mask: Values to write to xxx_INT_MASK if active. */ u32 mask; =20 + /** + * @mask_lock: protects modifications to _INT_MASK and @mask. + * + * In paths where _INT_MASK is updated based on a state + * transition/check, it's crucial for the state update/check to be + * inside the locked section, otherwise it introduces a race window + * leading to potential _INT_MASK inconsistencies. + */ + spinlock_t mask_lock; + /** @state: one of &enum panthor_irq_state reflecting the current state. = */ atomic_t state; }; @@ -425,13 +435,14 @@ static irqreturn_t panthor_ ## __name ## _irq_raw_han= dler(int irq, void *data) if (!gpu_read(ptdev, __reg_prefix ## _INT_STAT)) \ return IRQ_NONE; \ \ + guard(spinlock_irqsave)(&pirq->mask_lock); \ + gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \ old_state =3D atomic_cmpxchg(&pirq->state, \ PANTHOR_IRQ_STATE_ACTIVE, \ PANTHOR_IRQ_STATE_PROCESSING); \ if (old_state !=3D PANTHOR_IRQ_STATE_ACTIVE) \ return IRQ_NONE; \ \ - gpu_write(ptdev, __reg_prefix ## _INT_MASK, 0); \ return IRQ_WAKE_THREAD; \ } \ \ @@ -439,10 +450,17 @@ static irqreturn_t panthor_ ## __name ## _irq_threade= d_handler(int irq, void *da { \ struct panthor_irq *pirq =3D data; \ struct panthor_device *ptdev =3D pirq->ptdev; \ - enum panthor_irq_state old_state; \ irqreturn_t ret =3D IRQ_NONE; \ \ while (true) { \ + /* It's safe to access pirq->mask without the lock held here. If a new \ + * event gets added to the mask and the corresponding IRQ is pending, \ + * we'll process it right away instead of adding an extra raw -> threade= d \ + * round trip. If an event is removed and the status bit is set, it will= \ + * be ignored, just like it would have been if the mask had been adjuste= d \ + * right before the HW event kicks in. TLDR; it's all expected races we'= re \ + * covered for. \ + */ \ u32 status =3D gpu_read(ptdev, __reg_prefix ## _INT_RAWSTAT) & pirq->mas= k; \ \ if (!status) \ @@ -452,30 +470,36 @@ static irqreturn_t panthor_ ## __name ## _irq_threade= d_handler(int irq, void *da ret =3D IRQ_HANDLED; \ } \ \ - old_state =3D atomic_cmpxchg(&pirq->state, \ - PANTHOR_IRQ_STATE_PROCESSING, \ - PANTHOR_IRQ_STATE_ACTIVE); \ - if (old_state =3D=3D PANTHOR_IRQ_STATE_PROCESSING) \ - gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \ + scoped_guard(spinlock_irqsave, &pirq->mask_lock) { \ + enum panthor_irq_state old_state; \ + \ + old_state =3D atomic_cmpxchg(&pirq->state, \ + PANTHOR_IRQ_STATE_PROCESSING, \ + PANTHOR_IRQ_STATE_ACTIVE); \ + if (old_state =3D=3D PANTHOR_IRQ_STATE_PROCESSING) \ + gpu_write(ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \ + } \ \ return ret; \ } \ \ static inline void panthor_ ## __name ## _irq_suspend(struct panthor_irq *= pirq) \ { \ - pirq->mask =3D 0; \ - gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \ - atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDING); \ + scoped_guard(spinlock_irqsave, &pirq->mask_lock) { \ + atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDING); \ + gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, 0); \ + } \ synchronize_irq(pirq->irq); \ atomic_set(&pirq->state, PANTHOR_IRQ_STATE_SUSPENDED); \ } \ \ -static inline void panthor_ ## __name ## _irq_resume(struct panthor_irq *p= irq, u32 mask) \ +static inline void panthor_ ## __name ## _irq_resume(struct panthor_irq *p= irq) \ { \ - pirq->mask =3D mask; \ + guard(spinlock_irqsave)(&pirq->mask_lock); \ + \ atomic_set(&pirq->state, PANTHOR_IRQ_STATE_ACTIVE); \ - gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, mask); \ - gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, mask); \ + gpu_write(pirq->ptdev, __reg_prefix ## _INT_CLEAR, pirq->mask); \ + gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \ } \ \ static int panthor_request_ ## __name ## _irq(struct panthor_device *ptdev= , \ @@ -484,13 +508,43 @@ static int panthor_request_ ## __name ## _irq(struct = panthor_device *ptdev, \ { \ pirq->ptdev =3D ptdev; \ pirq->irq =3D irq; \ - panthor_ ## __name ## _irq_resume(pirq, mask); \ + pirq->mask =3D mask; \ + spin_lock_init(&pirq->mask_lock); \ + panthor_ ## __name ## _irq_resume(pirq); \ \ return devm_request_threaded_irq(ptdev->base.dev, irq, \ panthor_ ## __name ## _irq_raw_handler, \ panthor_ ## __name ## _irq_threaded_handler, \ IRQF_SHARED, KBUILD_MODNAME "-" # __name, \ pirq); \ +} \ + \ +static inline void panthor_ ## __name ## _irq_enable_events(struct panthor= _irq *pirq, u32 mask) \ +{ \ + guard(spinlock_irqsave)(&pirq->mask_lock); \ + pirq->mask |=3D mask; \ + \ + /* The only situation where we need to write the new mask is if the IRQ i= s active. \ + * If it's being processed, the mask will be restored for us in _irq_thre= aded_handler() \ + * on the PROCESSING -> ACTIVE transition. \ + * If the IRQ is suspended/suspending, the mask is restored at resume tim= e. \ + */ \ + if (atomic_read(&pirq->state) =3D=3D PANTHOR_IRQ_STATE_ACTIVE) \ + gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \ +} \ + \ +static inline void panthor_ ## __name ## _irq_disable_events(struct pantho= r_irq *pirq, u32 mask)\ +{ \ + guard(spinlock_irqsave)(&pirq->mask_lock); \ + pirq->mask &=3D ~mask; \ + \ + /* The only situation where we need to write the new mask is if the IRQ i= s active. \ + * If it's being processed, the mask will be restored for us in _irq_thre= aded_handler() \ + * on the PROCESSING -> ACTIVE transition. \ + * If the IRQ is suspended/suspending, the mask is restored at resume tim= e. \ + */ \ + if (atomic_read(&pirq->state) =3D=3D PANTHOR_IRQ_STATE_ACTIVE) \ + gpu_write(pirq->ptdev, __reg_prefix ## _INT_MASK, pirq->mask); \ } =20 extern struct workqueue_struct *panthor_cleanup_wq; diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index a64ec8756bed..0e46625f7621 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -1080,7 +1080,8 @@ static int panthor_fw_start(struct panthor_device *pt= dev) bool timedout =3D false; =20 ptdev->fw->booted =3D false; - panthor_job_irq_resume(&ptdev->fw->irq, ~0); + panthor_job_irq_enable_events(&ptdev->fw->irq, ~0); + panthor_job_irq_resume(&ptdev->fw->irq); gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_AUTO); =20 if (!wait_event_timeout(ptdev->fw->req_waitqueue, diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index 057e167468d0..9304469a711a 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -395,7 +395,7 @@ void panthor_gpu_suspend(struct panthor_device *ptdev) */ void panthor_gpu_resume(struct panthor_device *ptdev) { - panthor_gpu_irq_resume(&ptdev->gpu->irq, GPU_INTERRUPTS_MASK); + panthor_gpu_irq_resume(&ptdev->gpu->irq); panthor_hw_l2_power_on(ptdev); } =20 diff --git a/drivers/gpu/drm/panthor/panthor_mmu.c b/drivers/gpu/drm/pantho= r/panthor_mmu.c index 198d59f42578..a1b7917a31b1 100644 --- a/drivers/gpu/drm/panthor/panthor_mmu.c +++ b/drivers/gpu/drm/panthor/panthor_mmu.c @@ -562,9 +562,21 @@ static u64 pack_region_range(struct panthor_device *pt= dev, u64 *region_start, u6 return region_width | *region_start; } =20 +static u32 panthor_mmu_as_fault_mask(struct panthor_device *ptdev, u32 as) +{ + return BIT(as); +} + +/* Forward declaration to call helpers within as_enable/disable */ +static void panthor_mmu_irq_handler(struct panthor_device *ptdev, u32 stat= us); +PANTHOR_IRQ_HANDLER(mmu, MMU, panthor_mmu_irq_handler); + static int panthor_mmu_as_enable(struct panthor_device *ptdev, u32 as_nr, u64 transtab, u64 transcfg, u64 memattr) { + panthor_mmu_irq_enable_events(&ptdev->mmu->irq, + panthor_mmu_as_fault_mask(ptdev, as_nr)); + gpu_write64(ptdev, AS_TRANSTAB(as_nr), transtab); gpu_write64(ptdev, AS_MEMATTR(as_nr), memattr); gpu_write64(ptdev, AS_TRANSCFG(as_nr), transcfg); @@ -580,6 +592,9 @@ static int panthor_mmu_as_disable(struct panthor_device= *ptdev, u32 as_nr, =20 lockdep_assert_held(&ptdev->mmu->as.slots_lock); =20 + panthor_mmu_irq_disable_events(&ptdev->mmu->irq, + panthor_mmu_as_fault_mask(ptdev, as_nr)); + /* Flush+invalidate RW caches, invalidate RO ones. */ ret =3D panthor_gpu_flush_caches(ptdev, CACHE_CLEAN | CACHE_INV, CACHE_CLEAN | CACHE_INV, CACHE_INV); @@ -612,11 +627,6 @@ static u32 panthor_mmu_fault_mask(struct panthor_devic= e *ptdev, u32 value) return value & GENMASK(15, 0); } =20 -static u32 panthor_mmu_as_fault_mask(struct panthor_device *ptdev, u32 as) -{ - return BIT(as); -} - /** * panthor_vm_has_unhandled_faults() - Check if a VM has unhandled faults * @vm: VM to check. @@ -670,6 +680,7 @@ int panthor_vm_active(struct panthor_vm *vm) struct io_pgtable_cfg *cfg =3D &io_pgtable_ops_to_pgtable(vm->pgtbl_ops)-= >cfg; int ret =3D 0, as, cookie; u64 transtab, transcfg; + u32 fault_mask; =20 if (!drm_dev_enter(&ptdev->base, &cookie)) return -ENODEV; @@ -743,14 +754,13 @@ int panthor_vm_active(struct panthor_vm *vm) /* If the VM is re-activated, we clear the fault. */ vm->unhandled_fault =3D false; =20 - /* Unhandled pagefault on this AS, clear the fault and re-enable interrup= ts - * before enabling the AS. + /* Unhandled pagefault on this AS, clear the fault and enable the AS, + * which re-enables interrupts. */ - if (ptdev->mmu->as.faulty_mask & panthor_mmu_as_fault_mask(ptdev, as)) { - gpu_write(ptdev, MMU_INT_CLEAR, panthor_mmu_as_fault_mask(ptdev, as)); - ptdev->mmu->as.faulty_mask &=3D ~panthor_mmu_as_fault_mask(ptdev, as); - ptdev->mmu->irq.mask |=3D panthor_mmu_as_fault_mask(ptdev, as); - gpu_write(ptdev, MMU_INT_MASK, ~ptdev->mmu->as.faulty_mask); + fault_mask =3D panthor_mmu_as_fault_mask(ptdev, as); + if (ptdev->mmu->as.faulty_mask & fault_mask) { + gpu_write(ptdev, MMU_INT_CLEAR, fault_mask); + ptdev->mmu->as.faulty_mask &=3D ~fault_mask; } =20 /* The VM update is guarded by ::op_lock, which we take at the beginning @@ -1698,7 +1708,6 @@ static void panthor_mmu_irq_handler(struct panthor_de= vice *ptdev, u32 status) while (status) { u32 as =3D ffs(status | (status >> 16)) - 1; u32 mask =3D panthor_mmu_as_fault_mask(ptdev, as); - u32 new_int_mask; u64 addr; u32 fault_status; u32 exception_type; @@ -1716,8 +1725,6 @@ static void panthor_mmu_irq_handler(struct panthor_de= vice *ptdev, u32 status) mutex_lock(&ptdev->mmu->as.slots_lock); =20 ptdev->mmu->as.faulty_mask |=3D mask; - new_int_mask =3D - panthor_mmu_fault_mask(ptdev, ~ptdev->mmu->as.faulty_mask); =20 /* terminal fault, print info about the fault */ drm_err(&ptdev->base, @@ -1741,11 +1748,6 @@ static void panthor_mmu_irq_handler(struct panthor_d= evice *ptdev, u32 status) */ gpu_write(ptdev, MMU_INT_CLEAR, mask); =20 - /* Ignore MMU interrupts on this AS until it's been - * re-enabled. - */ - ptdev->mmu->irq.mask =3D new_int_mask; - if (ptdev->mmu->as.slots[as].vm) ptdev->mmu->as.slots[as].vm->unhandled_fault =3D true; =20 @@ -1760,7 +1762,6 @@ static void panthor_mmu_irq_handler(struct panthor_de= vice *ptdev, u32 status) if (has_unhandled_faults) panthor_sched_report_mmu_fault(ptdev); } -PANTHOR_IRQ_HANDLER(mmu, MMU, panthor_mmu_irq_handler); =20 /** * panthor_mmu_suspend() - Suspend the MMU logic @@ -1805,7 +1806,7 @@ void panthor_mmu_resume(struct panthor_device *ptdev) ptdev->mmu->as.faulty_mask =3D 0; mutex_unlock(&ptdev->mmu->as.slots_lock); =20 - panthor_mmu_irq_resume(&ptdev->mmu->irq, panthor_mmu_fault_mask(ptdev, ~0= )); + panthor_mmu_irq_resume(&ptdev->mmu->irq); } =20 /** @@ -1859,7 +1860,7 @@ void panthor_mmu_post_reset(struct panthor_device *pt= dev) =20 mutex_unlock(&ptdev->mmu->as.slots_lock); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260116-panthor-tracepoints-v10-3-d925986e3d1b@collabora.com> References: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> In-Reply-To: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chia-I Wu , Karunika Choo Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Mali GPUs have three registers that indicate which parts of the hardware are powered at any moment. These take the form of bitmaps. In the case of SHADER_READY for example, a high bit indicates that the shader core corresponding to that bit index is powered on. These bitmaps aren't solely contiguous bits, as it's common to have holes in the sequence of shader core indices, and the actual set of which cores are present is defined by the "shader present" register. When the GPU finishes a power state transition, it fires a GPU_IRQ_POWER_CHANGED_ALL interrupt. After such an interrupt is received, the _READY registers will contain new interesting data. During power transitions, the GPU_IRQ_POWER_CHANGED interrupt will fire, and the registers will likewise contain potentially changed data. This is not to be confused with the PWR_IRQ_POWER_CHANGED_ALL interrupt, which is something related to Mali v14+'s power control logic. The _READY registers and corresponding interrupts are already available in v9 and onwards. Expose the data as a tracepoint to userspace. This allows users to debug various scenarios and gather interesting information, such as: knowing how much hardware is lit up at any given time, correlating graphics corruption with a specific powered shader core, measuring when hardware is allowed to go to a powered off state again, and so on. The registration/unregistration functions for the tracepoint go through a wrapper in panthor_hw.c, so that v14+ can implement the same tracepoint by adding its hardware specific IRQ on/off callbacks to the panthor_hw.ops member. Signed-off-by: Nicolas Frattaroli Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panthor/panthor_gpu.c | 28 +++++++++++++++ drivers/gpu/drm/panthor/panthor_gpu.h | 2 ++ drivers/gpu/drm/panthor/panthor_hw.c | 62 +++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/panthor/panthor_hw.h | 8 +++++ drivers/gpu/drm/panthor/panthor_trace.h | 58 ++++++++++++++++++++++++++++++ 5 files changed, 158 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/pantho= r/panthor_gpu.c index 9304469a711a..2ab444ee8c71 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.c +++ b/drivers/gpu/drm/panthor/panthor_gpu.c @@ -22,6 +22,9 @@ #include "panthor_hw.h" #include "panthor_regs.h" =20 +#define CREATE_TRACE_POINTS +#include "panthor_trace.h" + /** * struct panthor_gpu - GPU block management data. */ @@ -48,6 +51,9 @@ struct panthor_gpu { GPU_IRQ_RESET_COMPLETED | \ GPU_IRQ_CLEAN_CACHES_COMPLETED) =20 +#define GPU_POWER_INTERRUPTS_MASK \ + (GPU_IRQ_POWER_CHANGED | GPU_IRQ_POWER_CHANGED_ALL) + static void panthor_gpu_coherency_set(struct panthor_device *ptdev) { gpu_write(ptdev, GPU_COHERENCY_PROTOCOL, @@ -80,6 +86,12 @@ static void panthor_gpu_irq_handler(struct panthor_devic= e *ptdev, u32 status) { gpu_write(ptdev, GPU_INT_CLEAR, status); =20 + if (tracepoint_enabled(gpu_power_status) && (status & GPU_POWER_INTERRUPT= S_MASK)) + trace_gpu_power_status(ptdev->base.dev, + gpu_read64(ptdev, SHADER_READY), + gpu_read64(ptdev, TILER_READY), + gpu_read64(ptdev, L2_READY)); + if (status & GPU_IRQ_FAULT) { u32 fault_status =3D gpu_read(ptdev, GPU_FAULT_STATUS); u64 address =3D gpu_read64(ptdev, GPU_FAULT_ADDR); @@ -157,6 +169,22 @@ int panthor_gpu_init(struct panthor_device *ptdev) return 0; } =20 +int panthor_gpu_power_changed_on(struct panthor_device *ptdev) +{ + guard(pm_runtime_active)(ptdev->base.dev); + + panthor_gpu_irq_enable_events(&ptdev->gpu->irq, GPU_POWER_INTERRUPTS_MASK= ); + + return 0; +} + +void panthor_gpu_power_changed_off(struct panthor_device *ptdev) +{ + guard(pm_runtime_active)(ptdev->base.dev); + + panthor_gpu_irq_disable_events(&ptdev->gpu->irq, GPU_POWER_INTERRUPTS_MAS= K); +} + /** * panthor_gpu_block_power_off() - Power-off a specific block of the GPU * @ptdev: Device. diff --git a/drivers/gpu/drm/panthor/panthor_gpu.h b/drivers/gpu/drm/pantho= r/panthor_gpu.h index 12e66f48ced1..12c263a39928 100644 --- a/drivers/gpu/drm/panthor/panthor_gpu.h +++ b/drivers/gpu/drm/panthor/panthor_gpu.h @@ -51,5 +51,7 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev); int panthor_gpu_flush_caches(struct panthor_device *ptdev, u32 l2, u32 lsc, u32 other); int panthor_gpu_soft_reset(struct panthor_device *ptdev); +void panthor_gpu_power_changed_off(struct panthor_device *ptdev); +int panthor_gpu_power_changed_on(struct panthor_device *ptdev); =20 #endif diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor= /panthor_hw.c index 80c521784cd3..d135aa6724fa 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.c +++ b/drivers/gpu/drm/panthor/panthor_hw.c @@ -2,6 +2,8 @@ /* Copyright 2025 ARM Limited. All rights reserved. */ =20 #include +#include + #include =20 #include "panthor_device.h" @@ -30,6 +32,8 @@ static struct panthor_hw panthor_hw_arch_v10 =3D { .soft_reset =3D panthor_gpu_soft_reset, .l2_power_off =3D panthor_gpu_l2_power_off, .l2_power_on =3D panthor_gpu_l2_power_on, + .power_changed_off =3D panthor_gpu_power_changed_off, + .power_changed_on =3D panthor_gpu_power_changed_on, }, }; =20 @@ -54,6 +58,64 @@ static struct panthor_hw_entry panthor_hw_match[] =3D { }, }; =20 +static int panthor_hw_set_power_tracing(struct device *dev, void *data) +{ + struct panthor_device *ptdev =3D dev_get_drvdata(dev); + + if (!ptdev) + return -ENODEV; + + if (!ptdev->hw) + return 0; + + if (data) { + if (ptdev->hw->ops.power_changed_on) + return ptdev->hw->ops.power_changed_on(ptdev); + } else { + if (ptdev->hw->ops.power_changed_off) + ptdev->hw->ops.power_changed_off(ptdev); + } + + return 0; +} + +int panthor_hw_power_status_register(void) +{ + struct device_driver *drv; + int ret; + + drv =3D driver_find("panthor", &platform_bus_type); + if (!drv) + return -ENODEV; + + ret =3D driver_for_each_device(drv, NULL, (void *)true, + panthor_hw_set_power_tracing); + + return ret; +} + +void panthor_hw_power_status_unregister(void) +{ + struct device_driver *drv; + int ret; + + drv =3D driver_find("panthor", &platform_bus_type); + if (!drv) + return; + + ret =3D driver_for_each_device(drv, NULL, NULL, panthor_hw_set_power_trac= ing); + + /* + * Ideally, it'd be possible to ask driver_for_each_device to hand us + * another "start" to keep going after the failing device, but it + * doesn't do that. Minor inconvenience in what is probably a bad day + * on the computer already though. + */ + if (ret) + pr_warn("Couldn't mask power IRQ for at least one device: %pe\n", + ERR_PTR(ret)); +} + static char *get_gpu_model_name(struct panthor_device *ptdev) { const u32 gpu_id =3D ptdev->gpu_info.gpu_id; diff --git a/drivers/gpu/drm/panthor/panthor_hw.h b/drivers/gpu/drm/panthor= /panthor_hw.h index 56c68c1e9c26..2c28aea82841 100644 --- a/drivers/gpu/drm/panthor/panthor_hw.h +++ b/drivers/gpu/drm/panthor/panthor_hw.h @@ -19,6 +19,12 @@ struct panthor_hw_ops { =20 /** @l2_power_on: L2 power on function pointer */ int (*l2_power_on)(struct panthor_device *ptdev); + + /** @power_changed_on: Start listening to power change IRQs */ + int (*power_changed_on)(struct panthor_device *ptdev); + + /** @power_changed_off: Stop listening to power change IRQs */ + void (*power_changed_off)(struct panthor_device *ptdev); }; =20 /** @@ -32,6 +38,8 @@ struct panthor_hw { }; =20 int panthor_hw_init(struct panthor_device *ptdev); +int panthor_hw_power_status_register(void); +void panthor_hw_power_status_unregister(void); =20 static inline int panthor_hw_soft_reset(struct panthor_device *ptdev) { diff --git a/drivers/gpu/drm/panthor/panthor_trace.h b/drivers/gpu/drm/pant= hor/panthor_trace.h new file mode 100644 index 000000000000..5bd420894745 --- /dev/null +++ b/drivers/gpu/drm/panthor/panthor_trace.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 or MIT */ +/* Copyright 2025 Collabora ltd. */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM panthor + +#if !defined(__PANTHOR_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) +#define __PANTHOR_TRACE_H__ + +#include +#include + +#include "panthor_hw.h" + +/** + * gpu_power_status - called whenever parts of GPU hardware are turned on = or off + * @dev: pointer to the &struct device, for printing the device name + * @shader_bitmap: bitmap where a high bit indicates the shader core at a = given + * bit index is on, and a low bit indicates a shader core = is + * either powered off or absent + * @tiler_bitmap: bitmap where a high bit indicates the tiler unit at a gi= ven + * bit index is on, and a low bit indicates a tiler unit is + * either powered off or absent + * @l2_bitmap: bitmap where a high bit indicates the L2 cache at a given b= it + * index is on, and a low bit indicates the L2 cache is either + * powered off or absent + */ +TRACE_EVENT_FN(gpu_power_status, + TP_PROTO(const struct device *dev, u64 shader_bitmap, u64 tiler_bitmap, + u64 l2_bitmap), + TP_ARGS(dev, shader_bitmap, tiler_bitmap, l2_bitmap), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u64, shader_bitmap) + __field(u64, tiler_bitmap) + __field(u64, l2_bitmap) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->shader_bitmap =3D shader_bitmap; + __entry->tiler_bitmap =3D tiler_bitmap; + __entry->l2_bitmap =3D l2_bitmap; + ), + TP_printk("%s: shader_bitmap=3D0x%llx tiler_bitmap=3D0x%llx l2_bitmap=3D0= x%llx", + __get_str(dev_name), __entry->shader_bitmap, __entry->tiler_bitmap, + __entry->l2_bitmap + ), + panthor_hw_power_status_register, panthor_hw_power_status_unregister +); + +#endif /* __PANTHOR_TRACE_H__ */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE panthor_trace + +#include --=20 2.52.0 From nobody Sat Feb 7 04:40:38 2026 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66EAD2253FC for ; Fri, 16 Jan 2026 12:58:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1768568284; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=19nv2PZgHaBu1531IdjRSZZ3SQBGh0yLoB263HOVEbI=; b=dSToYjIdd0cYX31FkJqy5gm9U9NZZpXT9GzXXO4+M2l0inQVT9dpr2np9SSV0I7S HJpiFbhm/wVj4SUL6NbUeCGoCQHPRxk5k2Ytd/xaPLnpaoDaZu7T3GZP7CXzsxOB84C NeWKOthz8/EH+Ues7H85spPfyra2l4ZVmGY/XxU4= Received: by mx.zohomail.com with SMTPS id 1768568283857153.72395643692175; Fri, 16 Jan 2026 04:58:03 -0800 (PST) From: Nicolas Frattaroli Date: Fri, 16 Jan 2026 13:57:33 +0100 Subject: [PATCH v10 4/4] drm/panthor: Add gpu_job_irq tracepoint Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260116-panthor-tracepoints-v10-4-d925986e3d1b@collabora.com> References: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> In-Reply-To: <20260116-panthor-tracepoints-v10-0-d925986e3d1b@collabora.com> To: Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chia-I Wu , Karunika Choo Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nicolas Frattaroli X-Mailer: b4 0.14.3 Mali's CSF firmware triggers the job IRQ whenever there's new firmware events for processing. While this can be a global event (BIT(31) of the status register), it's usually an event relating to a command stream group (the other bit indices). Panthor throws these events onto a workqueue for processing outside the IRQ handler. It's therefore useful to have an instrumented tracepoint that goes beyond the generic IRQ tracepoint for this specific case, as it can be augmented with additional data, namely the events bit mask. This can then be used to debug problems relating to GPU jobs events not being processed quickly enough. The duration_ns field can be used to work backwards from when the tracepoint fires (at the end of the IRQ handler) to figure out when the interrupt itself landed, providing not just information on how long the work queueing took, but also when the actual interrupt itself arrived. With this information in hand, the IRQ handler itself being slow can be excluded as a possible source of problems, and attention can be directed to the workqueue processing instead. Signed-off-by: Nicolas Frattaroli Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panthor/panthor_fw.c | 13 +++++++++++++ drivers/gpu/drm/panthor/panthor_trace.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_fw.c b/drivers/gpu/drm/panthor= /panthor_fw.c index 0e46625f7621..5a904ca64525 100644 --- a/drivers/gpu/drm/panthor/panthor_fw.c +++ b/drivers/gpu/drm/panthor/panthor_fw.c @@ -26,6 +26,7 @@ #include "panthor_mmu.h" #include "panthor_regs.h" #include "panthor_sched.h" +#include "panthor_trace.h" =20 #define CSF_FW_NAME "mali_csffw.bin" =20 @@ -1060,6 +1061,12 @@ static void panthor_fw_init_global_iface(struct pant= hor_device *ptdev) =20 static void panthor_job_irq_handler(struct panthor_device *ptdev, u32 stat= us) { + u32 duration; + u64 start =3D 0; + + if (tracepoint_enabled(gpu_job_irq)) + start =3D ktime_get_ns(); + gpu_write(ptdev, JOB_INT_CLEAR, status); =20 if (!ptdev->fw->booted && (status & JOB_INT_GLOBAL_IF)) @@ -1072,6 +1079,12 @@ static void panthor_job_irq_handler(struct panthor_d= evice *ptdev, u32 status) return; =20 panthor_sched_report_fw_events(ptdev, status); + + if (tracepoint_enabled(gpu_job_irq) && start) { + if (check_sub_overflow(ktime_get_ns(), start, &duration)) + duration =3D U32_MAX; + trace_gpu_job_irq(ptdev->base.dev, status, duration); + } } PANTHOR_IRQ_HANDLER(job, JOB, panthor_job_irq_handler); =20 diff --git a/drivers/gpu/drm/panthor/panthor_trace.h b/drivers/gpu/drm/pant= hor/panthor_trace.h index 5bd420894745..6ffeb4fe6599 100644 --- a/drivers/gpu/drm/panthor/panthor_trace.h +++ b/drivers/gpu/drm/panthor/panthor_trace.h @@ -48,6 +48,34 @@ TRACE_EVENT_FN(gpu_power_status, panthor_hw_power_status_register, panthor_hw_power_status_unregister ); =20 +/** + * gpu_job_irq - called after a job interrupt from firmware completes + * @dev: pointer to the &struct device, for printing the device name + * @events: bitmask of BIT(CSG id) | BIT(31) for a global event + * @duration_ns: Nanoseconds between job IRQ handler entry and exit + * + * The panthor_job_irq_handler() function instrumented by this tracepoint = exits + * once it has queued the firmware interrupts for processing, not when the + * firmware interrupts are fully processed. This tracepoint allows for deb= ugging + * issues with delays in the workqueue's processing of events. + */ +TRACE_EVENT(gpu_job_irq, + TP_PROTO(const struct device *dev, u32 events, u32 duration_ns), + TP_ARGS(dev, events, duration_ns), + TP_STRUCT__entry( + __string(dev_name, dev_name(dev)) + __field(u32, events) + __field(u32, duration_ns) + ), + TP_fast_assign( + __assign_str(dev_name); + __entry->events =3D events; + __entry->duration_ns =3D duration_ns; + ), + TP_printk("%s: events=3D0x%x duration_ns=3D%d", __get_str(dev_name), + __entry->events, __entry->duration_ns) +); + #endif /* __PANTHOR_TRACE_H__ */ =20 #undef TRACE_INCLUDE_PATH --=20 2.52.0