From nobody Tue Feb 10 10:03:26 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9995F3933E8 for ; Fri, 16 Jan 2026 14:50:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768575055; cv=none; b=QqHKSF0xRDYVfTy0zxJefPbP1WGW5otw/KGrqKYxBMGjBFr8CvpQSWv1gLxzPhgDiMhwIaZMuATvlefZneNw06cgkffDexhJZURQqO7ZLHGmc7Zcjbh7FnR+ialxhbKu1T8lsY/1UHDMK61Fd3PqzSTvnF+92Tgsw/REF/vZjP4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768575055; c=relaxed/simple; bh=gjhNyyiXPMwDxet4wKDSHV0d9wDjmHjHxnL5eNbp+F4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=M+6s+p1lOOgD9MVZ+vPANugQqkueMaygHGV/cgXwMnhJcHfKTNBJrwpslT1G+Va5FzGeC0HH56SHEE26FietgmItjXNDOlauyghvaVCW5QPjha4LMH29tQHxHQBZRbPRGyWksCQ2jusce6DNalfrsq4Vz4e5guJsaTaPd9V11LA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=M/KRtbmx; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="M/KRtbmx" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-64b7318f1b0so3323846a12.2 for ; Fri, 16 Jan 2026 06:50:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1768575052; x=1769179852; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=mjx8cp8u1zTtz+8HPO5dBG1VmcVVPk4nfrHWtFsxXSs=; b=M/KRtbmxY3K3nTUwFVbNEsKQliOss69ZFDb7zTwda8rwFtHsq1s0XjqPu9tS602ski W36mjZLIA6U7YXlYRSB4ijpJykNVPOZ8Bq1acWrkwV/wzrC4low5lnlA/45me8Edfgom ISXeNBoTYnwiH9Na9IioySD4Qn9L19wd6xG048k2Sw0xOOcko+ZTzg3FOrx8LQVON6ZY M41HfsU/UbXCs1XdL5HHGbY4BXGhcWk+udSxsSOPT73E4MsItanaxnffuhYGyFs5zU4W 1KTF2qdMUqOG69HV7aez5ql4o06yFEuAWcicusIskDPstQ6ZoZu4H8UunbZ8iRv44kbF KBIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768575052; x=1769179852; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=mjx8cp8u1zTtz+8HPO5dBG1VmcVVPk4nfrHWtFsxXSs=; b=j35qlRq60wyPDwkF+AUlD451h1X55205Vux5uUlIfkBdt9UHxYZniZ2vfX1njetKXH YNcobMUyr9wBVDhRvI7QorvUB+i9xTVP+B8MQv8C7emImvwdV8KHQ6DU+eCvDQVy893l S4RdYeFRWHnBgBfNnLCfcbs9R4Cl+QzpkcixXWdRp/8pw+T2+/y3f/J5e/G+NzmcdwgO Z4v/Kg5LKV7ONSACe2Uh7MagiJe/vFzbr0NiLVdr4RheOj7pqb61LFQRQxfzx/hmFStw z4k8z2IajZWxGMmiidDIG9D/rWj4UD+wAdLEjxHpqdMW6vXI9NyHxarnk+jTM9nH3RQF 55tA== X-Forwarded-Encrypted: i=1; AJvYcCW8qg6EUYd1j45ehZAy5KYcQvTFJzdwEQoJvW8MKMse1dNGJW5/DTtEsP9ykQGzd7FoNNr4t6Z4qcJh68Y=@vger.kernel.org X-Gm-Message-State: AOJu0YyUyp5sOoqumejGKg/LI92ufkM0XLlUCN6ClRDbWQe9iuJIhrlB 3zuHj/2BQIzpalaCLBKX1V4BOcNkFx1P5Ds2I9EH/dPJTg7tcl4WY+eM49rgIQlFvEg= X-Gm-Gg: AY/fxX6KCbyzVfDw2n+8nEzGgjkIWo7S5sKWFQB9t5tofw9AR4HVLxNQZAu2omIW4gh cxTIz2WlrLNWgaPx0xBb/m3wIezpBTz4v/UztDS9bmSntiw2/KYj3QYof7fKERqHrqOhIqB2Zbh zKpldRBYSbqTn1mICSYonZ04S/Trx3NmYvWstMtCD7GdLwRZYa54Lt+hEMlEPqy52akJq4hrqaQ JRQSqbj3mq/r1BPh9PNhXnHCaD4ii6a4yxm3g9yUE0SAF7hlB3yjmc0gm1Cw0CyetnGVGxz7BpU gwqlakQNf08rsa9wqynsPukr4l7NiLj8g6KKhkhPXHsQP/BZ/Ost6LKq44vB0AhJeZzKSDwj3WK kHAppbwuCrct1Vz7skWZe2+SpY4NEE7X1ugLHaaBjJGb5wosIPlQmM/YQ4x1rOAJ+zfD5OHvPKA JEe1QBjJ/zEeJUJlwmOCgwxxFwG8Hr8ts9C1DEnM3VM514wjjcJjC28r2cjPKLwS7Z X-Received: by 2002:a05:6402:1ece:b0:649:2347:e15f with SMTP id 4fb4d7f45d1cf-654bb61af82mr2022241a12.31.1768575052026; Fri, 16 Jan 2026 06:50:52 -0800 (PST) Received: from [172.16.240.99] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65452cdab55sm2699427a12.10.2026.01.16.06.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jan 2026 06:50:51 -0800 (PST) From: Luca Weiss Date: Fri, 16 Jan 2026 15:50:48 +0100 Subject: [PATCH 2/5] arm64: dts: qcom: milos: Split up uart11 pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260116-milos-fp6-bt-wifi-v1-2-27b4fbb77e9c@fairphone.com> References: <20260116-milos-fp6-bt-wifi-v1-0-27b4fbb77e9c@fairphone.com> In-Reply-To: <20260116-milos-fp6-bt-wifi-v1-0-27b4fbb77e9c@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768575048; l=1821; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=gjhNyyiXPMwDxet4wKDSHV0d9wDjmHjHxnL5eNbp+F4=; b=9aCWGUk70yj5LCtl1yQkbB+PuccQDjLr6m/nWRrB15aM5nCuUYvR/4W9Y8+MxDkkNrS7kb8u2 C+9KiWmMFacBR25AAZ//iePt3boxN4/eIxF6O2AZgcmfclRZmZWZ7i9 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= In order to set the pinctrl for the individual CTS, RTS, TX and RX pins, split up the pinctrl configuration into 4 nodes so that boards can set some properties separately. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 0f69deabb60c..024e1c9992fe 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -915,7 +915,7 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, interconnect-names =3D "qup-core", "qup-config"; =20 - pinctrl-0 =3D <&qup_uart11_default>, <&qup_uart11_cts_rts>; + pinctrl-0 =3D <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, = <&qup_uart11_rx>; pinctrl-names =3D "default"; =20 status =3D "disabled"; @@ -1835,20 +1835,24 @@ qup_uart5_default: qup-uart5-default-state { bias-disable; }; =20 - qup_uart11_default: qup-uart11-default-state { - /* TX, RX */ - pins =3D "gpio50", "gpio51"; + qup_uart11_cts: qup-uart11-cts-state { + pins =3D "gpio48"; function =3D "qup1_se4"; - drive-strength =3D <2>; - bias-pull-up; }; =20 - qup_uart11_cts_rts: qup-uart11-cts-rts-state { - /* CTS, RTS */ - pins =3D "gpio48", "gpio49"; + qup_uart11_rts: qup-uart11-rts-state { + pins =3D "gpio49"; + function =3D "qup1_se4"; + }; + + qup_uart11_tx: qup-uart11-tx-state { + pins =3D "gpio50"; + function =3D "qup1_se4"; + }; + + qup_uart11_rx: qup-uart11-rx-state { + pins =3D "gpio51"; function =3D "qup1_se4"; - drive-strength =3D <2>; - bias-pull-down; }; =20 sdc2_default: sdc2-default-state { --=20 2.52.0