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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-654534c8b7fsm2495528a12.27.2026.01.16.05.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jan 2026 05:39:02 -0800 (PST) From: Luca Weiss Date: Fri, 16 Jan 2026 14:38:57 +0100 Subject: [PATCH 3/4] arm64: dts: qcom: milos: Add CCI busses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260116-milos-cci-v1-3-28e01128da9c@fairphone.com> References: <20260116-milos-cci-v1-0-28e01128da9c@fairphone.com> In-Reply-To: <20260116-milos-cci-v1-0-28e01128da9c@fairphone.com> To: Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , Robert Foss , Andi Shyti , Bjorn Andersson , Konrad Dybcio Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768570739; l=5415; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=Yfgai6qrSyDXbvMaMx6loOe5siBb8JOHwHrZfKdrvlc=; b=PlG90T1HaQ7oCDdUV+49GaybYGmN222ZTMKkMQRFhBG4axvFxsoJObUUAP15jmqi71hrFT7pm 9LMqbh4vENpC4Nq7lCPXr7+2pxqeSL/RPs40ONy738CjJqVYPTohv+m X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the nodes and the pinctrl for the CCI I2C busses on the Milos SoC. Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 194 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 194 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 58b4c2966df1..c8771beffa9b 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1652,6 +1652,72 @@ videocc: clock-controller@aaf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac15000 { + compatible =3D "qcom,milos-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac15000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_CAMSS_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "soc_ahb", + "cpas_ahb", + "cci"; + pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; + pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac16000 { + compatible =3D "qcom,milos-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac16000 0x0 0x1000>; + interrupts =3D ; + power-domains =3D <&camcc CAM_CC_CAMSS_TOP_GDSC>; + clocks =3D <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "soc_ahb", + "cpas_ahb", + "cci"; + pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; + pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camcc: clock-controller@adb0000 { compatible =3D "qcom,milos-camcc"; reg =3D <0x0 0x0adb0000 0x0 0x40000>; @@ -1791,6 +1857,134 @@ tlmm: pinctrl@f100000 { =20 wakeup-parent =3D <&pdc>; =20 + cci0_0_default: cci0-0-default-state { + sda-pins { + pins =3D "gpio88"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio89"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_0_sleep: cci0-0-sleep-state { + sda-pins { + pins =3D "gpio88"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio89"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_1_default: cci0-1-default-state { + sda-pins { + pins =3D "gpio90"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio91"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_1_sleep: cci0-1-sleep-state { + sda-pins { + pins =3D "gpio90"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio91"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_0_default: cci1-0-default-state { + sda-pins { + pins =3D "gpio92"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio93"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_0_sleep: cci1-0-sleep-state { + sda-pins { + pins =3D "gpio92"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio93"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_1_default: cci1-1-default-state { + sda-pins { + pins =3D "gpio94"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio95"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_1_sleep: cci1-1-sleep-state { + sda-pins { + pins =3D "gpio94"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio95"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + qup_i2c1_data_clk: qup-i2c1-data-clk-state { /* SDA, SCL */ pins =3D "gpio4", "gpio5"; --=20 2.52.0