From nobody Wed Feb 11 05:25:43 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012063.outbound.protection.outlook.com [40.107.209.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F16FA329C54; Thu, 15 Jan 2026 21:27:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.209.63 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768512484; cv=fail; b=dVYcWd23Yz9oodJAUv21AflBNKkwJSYG6MM4r2IEREF6g7MeEaVuNsFgs8KqsEZ4X2PFxQHUKuxsDOkVLSyfGgHWTaPU/k0pjn0+/snrseBFG5aPi3iuSdsbX+wBTL/jC9rzzD2id8v/07BkPTiMuV4Iqo1qLysK4DrmIxxo+/c= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768512484; c=relaxed/simple; bh=cpirfd74wB8kzsIIQfiihWwsOKxfRYunKbeteX1jMLc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BpVTLRFUPN+XRwiguQsvuAwq1tD4ypctsep8dPHJnltCFRC+nQzklLpaoF4t3CLDOSyjfWo2zTI1B5J0CjyQBWqPAKP0+e8FypodMxyyUYIATCcu0aFHhZtUluQ8JGkxT/lL4n5E3Hlr3wKwyS+nDAV8Itwcpxp8IcTFrLHmF0k= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=drQevAXU; arc=fail smtp.client-ip=40.107.209.63 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="drQevAXU" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=H7LLXHAKrmx9u4ZshuyH1TpqNgcCkgh0jCm7nqyh+AXcEgqGNYLIpvNk3QS7HLaTc5QFdAkzeQlzeImIzFT0HOHSccyxTDfGRqHnyr9GcfRytRyOprwtnOm12ULEiEEnQfwoA4XGtyqjneIs/zOKDjmyOnmZhTzDemijuLgZhlaD1At/cQ5b+zy4p4VTOHk4J3X9LuObyKwjwbAASQ7Wrp/wm0xefTUjZxQMrOHISYnmoXx4cidCAqDgAOxwwc0+lcQWHokC8iu+c0Vq/fB7AYb1lV7yo0yTMMtaQT4JG1pdh8jmbuB6CdtlEIJ7Uge0lrZ0QlAPaM8LwzNicmUeQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=omCWvaQX8ZeZk7rbKBC9PLasJ7qUI+RMo19RMO7u1oQ=; b=G3yh9Cbg63OZZFC1T69giCeaUmbxMiEkIdhi66aiFNEuAHhxmOaqRMROLXkuFEbltTbj8JReQ4/204w7h8FZqBlwzLdN1drtBq1mI80XZkDQ6jD49u+lxUik3yv/z5wCVn/2nLU4tT9QHdKYYARgvNcs0vYfglcsYOD29OaljUGI1TXoaotjNe7Y1yion1Tpaa/yv5EtmJVoGptJ/FdnFAxmZe7oxD83Iw8Rt/Ad0kDvOe8TSdK9pBxbm5Lc6XnU/HsTbabcC8VVDyvk0qZMm9EX5X8c+Yg8FplC5IZLF+LXbT8filhV0v4frwBIKzmyxwRzwquYCRcvNw4IWu+l7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=omCWvaQX8ZeZk7rbKBC9PLasJ7qUI+RMo19RMO7u1oQ=; b=drQevAXUCWRxzT2L/A1Ivra+YKAouKsYtlSLKNmdak/gh0phRQZTulisRE9ZVm9JA0++fEETXNTQCqRUk2qOHzuFj9XLnPZCJQrs2K6UMwNtTR/Mt+JLMJKJz/NEAyAesdMk75RZMx0iVsHLwkUYQuYGpshn0/yarXmSKMHrxtaEvkjB7m6zk+77zCocTBRORqpOfov68tpGIdpK5co1OIrn0FM4WRSoRkZ5jAM8EsX45+HyS1ATNtMu9xvWnx/AvRmgPW+l28BAWI8MLXXowLDg6yjbTDJndbMFRxmU2YECBErgtkxqgXiwu4XSbmbdfJAorMCxXNLN/dDDGwTtNQ== Received: from BN0PR02CA0019.namprd02.prod.outlook.com (2603:10b6:408:e4::24) by DS5PPF78FC67EBA.namprd12.prod.outlook.com (2603:10b6:f:fc00::655) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.5; Thu, 15 Jan 2026 21:27:44 +0000 Received: from BN1PEPF00005FFC.namprd05.prod.outlook.com (2603:10b6:408:e4:cafe::6) by BN0PR02CA0019.outlook.office365.com (2603:10b6:408:e4::24) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9520.6 via Frontend Transport; Thu, 15 Jan 2026 21:27:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BN1PEPF00005FFC.mail.protection.outlook.com (10.167.243.228) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.4 via Frontend Transport; Thu, 15 Jan 2026 21:27:44 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 15 Jan 2026 13:27:23 -0800 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Thu, 15 Jan 2026 13:27:23 -0800 Received: from inno-vm-xubuntu (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Thu, 15 Jan 2026 13:27:17 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Zhi Wang Subject: [PATCH v9 2/5] rust: io: factor common I/O helpers into Io trait Date: Thu, 15 Jan 2026 23:26:46 +0200 Message-ID: <20260115212657.399231-3-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260115212657.399231-1-zhiw@nvidia.com> References: <20260115212657.399231-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00005FFC:EE_|DS5PPF78FC67EBA:EE_ X-MS-Office365-Filtering-Correlation-Id: 34185d71-5664-4c37-21b8-08de547cebf5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/YPjFk6csHmhtcNoCuFIMWB58AW3QtZOGV3qESnwUiLMPmog4o5TL1ZInkDO?= =?us-ascii?Q?cJT6nJ8I6RbCCCEXC7Qf2R72feopeIW+UL6IRJcPKGE+nXgasaxT0zs5+ZeY?= =?us-ascii?Q?DY6vOMgrBFesUWTqINgpyiSBIGAR3PPLbq0xbkhPR7+mH78wam6zPsCtIqVu?= =?us-ascii?Q?NTEMXLgbkIYiVI9FXe/11x+fxedLNf0jHvwf7GA+TcT2pNiMYfl8zAQpZsKR?= =?us-ascii?Q?bn2HCbIDtFOjoYSJwzy3NhdF7NKztg1vE6XSwrzWPpk/GRzMvE6EnEv2iQkt?= =?us-ascii?Q?yiRB1RU/Y6jQr2fR3fnXCFsBqiByHksYTImV8uAoq0O/TI7A0JXgfUVHhn1x?= =?us-ascii?Q?U3dN5CG9c+rmmaWdSPxVYAcYAcvdpvlkfYHvETXcLzwVzZNe87sv1RjeL5T3?= =?us-ascii?Q?yPZLqkGL+nMgcH/DRPobXhMv3HlHvEDF1tqgZIuYfgsXjsh36g8TRgwkjr8q?= =?us-ascii?Q?Hc+BmO+4vzlOhpsTZCBu5fYP3fDQIeHjgRl4ayZwz/2fGMWQqF/ioYwBFRhR?= =?us-ascii?Q?cW2a+F/zoLq+zQzW0i97J6yClgQwtY07H5lKUGHk8BsKV2rSfPHSACS99EZf?= =?us-ascii?Q?HXyIclakvKrt7nVrQ+D9LKx61APEGihVM1WZpJdbFEizztSKzFe4fzymanhY?= =?us-ascii?Q?k1Y/KNRxzxolgWcvk65nXFaQhX3Yaw7DIsPAmdkcPUt0ECp30fiJZ0BxY98j?= =?us-ascii?Q?NA/8KkCrcUtzFrSDGY9s3Mnlat7Bhg+aZnCeXtLayyK0E6xhw1vpg6s36nla?= =?us-ascii?Q?CKnShuSqpyhfD6OKXL5QCfXprzoeeEUgZbe3wrGy+LKruJVEKLI7Bh4VfzEw?= =?us-ascii?Q?o9ACk2F/CWSJ0026x/PQw/RX5hSEzXm08w2oaFiuYZ83RMPOuOYbKYU0yCtK?= =?us-ascii?Q?VklUdDjgYsfIcHQIClO2vuHIVIGQVX2W3Y9pSeFLaLHnJBZyoebCJ0UoHifm?= =?us-ascii?Q?ohpPkR6VnquB4HBwfQ9f0WXIwetX+5sYeHBmbEzmv3x/1+RsP1MkcaTsUtMT?= =?us-ascii?Q?WxvNDREwjXukJYce2+0TPoY/EKmGDz29BsfRY0ShiM4SDN+OrBmwibWWr4H6?= =?us-ascii?Q?OiY19rBYlvDokdhPPJpUPjDxW6pb7qysN100gg747uI0UShz5Wl3eCUl4oyI?= =?us-ascii?Q?cR409jrLLqlUyxl9u/0xTrTH6gMV/PZBMW8NFAidA3t9sFMZfmNAfhdwoV3v?= =?us-ascii?Q?8ZL9XbboGUHwNI7jEvhjw4/LloNQZjVlNCZcq8OfdiE428HSg11BdFPqdmpo?= =?us-ascii?Q?w4a6pb6OlqH+MrJG9AaPIlGvUTgOVX8cUhbE2Gnfob1uArlSYV2ryAE4WNg0?= =?us-ascii?Q?i2EbSqBELe87O7dGfYlXkdNDxLRvWF5WlGE/BeykYE7q7wILa36JQssZKHin?= =?us-ascii?Q?K8CSN14XFIHFMx/NSbWLdfL8UYR91QN8OXjwiv7xWQbw7HbopISUKJ7vQ6ZE?= =?us-ascii?Q?O+HAFEU+TNno2vDrnrI1vdYT2eRIOacFnlyAbPc6imCM9kz0grjdyhgh7grF?= =?us-ascii?Q?RNdp+XxHsv66B82A0I4NpnY7ajYrnuFvr15XUlocK+X2pARrXeMI6a4a8ise?= =?us-ascii?Q?ocYGNBhjEVeTlxLDfdyKw5s2HL1jEZ1od8Mr0v88tcWeQ6LSMwkC7TU1y96/?= =?us-ascii?Q?pohc5/B6U6P9EkSdo/2vVr/seBV1GEDJIc8iLMxNU+n2lW6p1woYxOV4b29O?= =?us-ascii?Q?aYrZqg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2026 21:27:44.2815 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34185d71-5664-4c37-21b8-08de547cebf5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00005FFC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS5PPF78FC67EBA Content-Type: text/plain; charset="utf-8" The previous Io type combined both the generic I/O access helpers and MMIO implementation details in a single struct. To establish a cleaner layering between the I/O interface and its concrete backends, paving the way for supporting additional I/O mechanisms in the future, Io need to be factored. Factor the common helpers into new {Io, Io64} traits, and move the MMIO-specific logic into a dedicated Mmio type implementing that trait. Rename the IoRaw to MmioRaw and update the bus MMIO implementations to use MmioRaw. No functional change intended. Cc: Alexandre Courbot Cc: Alice Ryhl Cc: Bjorn Helgaas Cc: Danilo Krummrich Cc: John Hubbard Signed-off-by: Zhi Wang --- drivers/gpu/drm/tyr/regs.rs | 1 + drivers/gpu/nova-core/gsp/sequencer.rs | 5 +- drivers/gpu/nova-core/regs/macros.rs | 90 +++++--- drivers/gpu/nova-core/vbios.rs | 1 + rust/kernel/devres.rs | 14 +- rust/kernel/io.rs | 291 +++++++++++++++++++------ rust/kernel/io/mem.rs | 16 +- rust/kernel/io/poll.rs | 16 +- rust/kernel/pci/io.rs | 12 +- samples/rust/rust_driver_pci.rs | 2 + 10 files changed, 317 insertions(+), 131 deletions(-) diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs index f46933aaa221..9f89bc73a775 100644 --- a/drivers/gpu/drm/tyr/regs.rs +++ b/drivers/gpu/drm/tyr/regs.rs @@ -11,6 +11,7 @@ use kernel::device::Bound; use kernel::device::Device; use kernel::devres::Devres; +use kernel::io::IoKnownSize; use kernel::prelude::*; =20 use crate::driver::IoMem; diff --git a/drivers/gpu/nova-core/gsp/sequencer.rs b/drivers/gpu/nova-core= /gsp/sequencer.rs index 2d0369c49092..862cf7f27143 100644 --- a/drivers/gpu/nova-core/gsp/sequencer.rs +++ b/drivers/gpu/nova-core/gsp/sequencer.rs @@ -12,7 +12,10 @@ =20 use kernel::{ device, - io::poll::read_poll_timeout, + io::{ + poll::read_poll_timeout, + Io, // + }, prelude::*, time::{ delay::fsleep, diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/r= egs/macros.rs index fd1a815fa57d..6c7d164937a0 100644 --- a/drivers/gpu/nova-core/regs/macros.rs +++ b/drivers/gpu/nova-core/regs/macros.rs @@ -369,16 +369,18 @@ impl $name { =20 /// Read the register from its address in `io`. #[inline(always)] - pub(crate) fn read(io: &T) -> Self where - T: ::core::ops::Deref>, + pub(crate) fn read(io: &T) -> Self where + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, { Self(io.read32($offset)) } =20 /// Write the value contained in `self` to the register addres= s in `io`. #[inline(always)] - pub(crate) fn write(self, io: &T) where - T: ::core::ops::Deref>, + pub(crate) fn write(self, io: &T) where + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, { io.write32(self.0, $offset) } @@ -386,11 +388,12 @@ pub(crate) fn write(self, io: &= T) where /// Read the register from its address in `io` and run `f` on = its value to obtain a new /// value to write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io)); @@ -408,12 +411,13 @@ impl $name { /// Read the register from `io`, using the base address provid= ed by `base` and adding /// the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -428,13 +432,14 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, { const OFFSET: usize =3D $name::OFFSET; @@ -449,12 +454,13 @@ pub(crate) fn write( /// the register's offset to it, then run `f` on its value to = obtain a new value to /// write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, base: &B, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -474,11 +480,12 @@ impl $name { =20 /// Read the array register at index `idx` from its address in= `io`. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, { build_assert!(idx < Self::SIZE); =20 @@ -490,12 +497,13 @@ pub(crate) fn read( =20 /// Write the value contained in `self` to the array register = with index `idx` in `io`. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, { build_assert!(idx < Self::SIZE); =20 @@ -507,12 +515,13 @@ pub(crate) fn write( /// Read the array register at index `idx` in `io` and run `f`= on its value to obtain a /// new value to write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, F: ::core::ops::FnOnce(Self) -> Self, { let reg =3D f(Self::read(io, idx)); @@ -524,11 +533,12 @@ pub(crate) fn update( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, { if idx < Self::SIZE { Ok(Self::read(io, idx)) @@ -542,12 +552,13 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, { if idx < Self::SIZE { Ok(self.write(io, idx)) @@ -562,12 +573,13 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_update( + pub(crate) fn try_update( io: &T, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, F: ::core::ops::FnOnce(Self) -> Self, { if idx < Self::SIZE { @@ -593,13 +605,14 @@ impl $name { /// Read the array register at index `idx` from `io`, using th= e base address provided /// by `base` and adding the register's offset to it. #[inline(always)] - pub(crate) fn read( + pub(crate) fn read( io: &T, #[allow(unused_variables)] base: &B, idx: usize, ) -> Self where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -614,14 +627,15 @@ pub(crate) fn read( /// Write the value contained in `self` to `io`, using the bas= e address provided by /// `base` and adding the offset of array register `idx` to it. #[inline(always)] - pub(crate) fn write( + pub(crate) fn write( self, io: &T, #[allow(unused_variables)] base: &B, idx: usize ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, { build_assert!(idx < Self::SIZE); @@ -636,13 +650,14 @@ pub(crate) fn write( /// by `base` and adding the register's offset to it, then run= `f` on its value to /// obtain a new value to write back. #[inline(always)] - pub(crate) fn update( + pub(crate) fn update( io: &T, base: &B, idx: usize, f: F, ) where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { @@ -656,12 +671,13 @@ pub(crate) fn update( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_read( + pub(crate) fn try_read( io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -677,13 +693,14 @@ pub(crate) fn try_read( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_write( + pub(crate) fn try_write( self, io: &T, base: &B, idx: usize, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, { if idx < Self::SIZE { @@ -700,13 +717,14 @@ pub(crate) fn try_write( /// The validity of `idx` is checked at run-time, and `EINVAL`= is returned is the /// access was out-of-bounds. #[inline(always)] - pub(crate) fn try_update( + pub(crate) fn try_update( io: &T, base: &B, idx: usize, f: F, ) -> ::kernel::error::Result where - T: ::core::ops::Deref>, + T: ::core::ops::Deref, + I: ::kernel::io::IoKnownSize, B: crate::regs::macros::RegisterBase<$base>, F: ::core::ops::FnOnce(Self) -> Self, { diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs index abf423560ff4..fe33b519e4d8 100644 --- a/drivers/gpu/nova-core/vbios.rs +++ b/drivers/gpu/nova-core/vbios.rs @@ -6,6 +6,7 @@ =20 use kernel::{ device, + io::Io, prelude::*, ptr::{ Alignable, diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs index 43089511bf76..dfaddac2af59 100644 --- a/rust/kernel/devres.rs +++ b/rust/kernel/devres.rs @@ -73,15 +73,16 @@ struct Inner { /// }, /// devres::Devres, /// io::{ -/// Io, -/// IoRaw, +/// IoKnownSize, +/// Mmio, +/// MmioRaw, /// PhysAddr, /// }, /// }; /// use core::ops::Deref; /// /// // See also [`pci::Bar`] for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -96,7 +97,7 @@ struct Inner { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -108,11 +109,11 @@ struct Inner { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// # fn no_run(dev: &Device) -> Result<(), Error> { @@ -258,6 +259,7 @@ pub fn device(&self) -> &Device { /// use kernel::{ /// device::Core, /// devres::Devres, + /// io::IoKnownSize, /// pci, // /// }; /// diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs index a97eb44a9a87..89d94e4fb1e3 100644 --- a/rust/kernel/io.rs +++ b/rust/kernel/io.rs @@ -32,16 +32,16 @@ /// By itself, the existence of an instance of this structure does not pro= vide any guarantees that /// the represented MMIO region does exist or is properly mapped. /// -/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an `Io` -/// instance providing the actual memory accessors. Only by the conversion= into an `Io` structure -/// any guarantees are given. -pub struct IoRaw { +/// Instead, the bus specific MMIO implementation must convert this raw re= presentation into an +/// `Mmio` instance providing the actual memory accessors. Only by the con= version into an `Mmio` +/// structure any guarantees are given. +pub struct MmioRaw { addr: usize, maxsize: usize, } =20 -impl IoRaw { - /// Returns a new `IoRaw` instance on success, an error otherwise. +impl MmioRaw { + /// Returns a new `MmioRaw` instance on success, an error otherwise. pub fn new(addr: usize, maxsize: usize) -> Result { if maxsize < SIZE { return Err(EINVAL); @@ -81,14 +81,16 @@ pub fn maxsize(&self) -> usize { /// ffi::c_void, /// io::{ /// Io, -/// IoRaw, +/// IoKnownSize, +/// Mmio, +/// MmioRaw, /// PhysAddr, /// }, /// }; /// use core::ops::Deref; /// /// // See also `pci::Bar` for a real example. -/// struct IoMem(IoRaw); +/// struct IoMem(MmioRaw); /// /// impl IoMem { /// /// # Safety @@ -103,7 +105,7 @@ pub fn maxsize(&self) -> usize { /// return Err(ENOMEM); /// } /// -/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?)) +/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?)) /// } /// } /// @@ -115,11 +117,11 @@ pub fn maxsize(&self) -> usize { /// } /// /// impl Deref for IoMem { -/// type Target =3D Io; +/// type Target =3D Mmio; /// /// fn deref(&self) -> &Self::Target { /// // SAFETY: The memory range stored in `self` has been properly= mapped in `Self::new`. -/// unsafe { Io::from_raw(&self.0) } +/// unsafe { Mmio::from_raw(&self.0) } /// } /// } /// @@ -133,29 +135,31 @@ pub fn maxsize(&self) -> usize { /// # } /// ``` #[repr(transparent)] -pub struct Io(IoRaw); +pub struct Mmio(MmioRaw); =20 macro_rules! define_read { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $t= ype_name:ty) =3D> { /// Read IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, offset: usize) -> $type_name { + $vis fn $name(&self, offset: usize) -> $type_name { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(addr as *const c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> = $type_name:ty) =3D> { /// Read IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, offset: usize) -> Result<$type_name> { + $vis fn $try_name(&self, offset: usize) -> Result<$type_name> { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -165,26 +169,28 @@ pub fn $try_name(&self, offset: usize) -> Result<$typ= e_name> { } =20 macro_rules! define_write { - ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_= name:ty) =3D> { + (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $t= ype_name:ty) =3D> { /// Write IO data from a given offset known at compile time. /// /// Bound checks are performed on compile time, hence if the offse= t is not known at compile /// time, the build will fail. $(#[$attr])* #[inline] - pub fn $name(&self, value: $type_name, offset: usize) { + $vis fn $name(&self, value: $type_name, offset: usize) { let addr =3D self.io_addr_assert::<$type_name>(offset); =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. unsafe { bindings::$c_fn(value, addr as *mut c_void) } } + }; =20 + (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- = $type_name:ty) =3D> { /// Write IO data from a given offset. /// /// Bound checks are performed on runtime, it fails if the offset = (plus the type size) is /// out of bounds. $(#[$attr])* - pub fn $try_name(&self, value: $type_name, offset: usize) -> Resul= t { + $vis fn $try_name(&self, value: $type_name, offset: usize) -> Resu= lt { let addr =3D self.io_addr::<$type_name>(offset)?; =20 // SAFETY: By the type invariant `addr` is a valid address for= MMIO operations. @@ -194,43 +200,40 @@ pub fn $try_name(&self, value: $type_name, offset: us= ize) -> Result { }; } =20 -impl Io { - /// Converts an `IoRaw` into an `Io` instance, providing the accessors= to the MMIO mapping. - /// - /// # Safety - /// - /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size - /// `maxsize`. - pub unsafe fn from_raw(raw: &IoRaw) -> &Self { - // SAFETY: `Io` is a transparent wrapper around `IoRaw`. - unsafe { &*core::ptr::from_ref(raw).cast() } +/// Checks whether an access of type `U` at the given `offset` +/// is valid within this region. +#[inline] +const fn offset_valid(offset: usize, size: usize) -> bool { + let type_size =3D core::mem::size_of::(); + if let Some(end) =3D offset.checked_add(type_size) { + end <=3D size && offset % type_size =3D=3D 0 + } else { + false } +} + +/// Represents a region of I/O space of a fixed size. +/// +/// This is an abstract representation to be implemented by arbitrary I/O +/// backends (e.g. MMIO, I2C, etc.). +/// +/// Provides common helpers for offset validation and address +/// calculation on top of a base address and maximum size. +pub trait IoBase { + /// Minimum usable size of this region. + const MIN_SIZE: usize; =20 /// Returns the base address of this mapping. - #[inline] - pub fn addr(&self) -> usize { - self.0.addr() - } + fn addr(&self) -> usize; =20 /// Returns the maximum size of this mapping. - #[inline] - pub fn maxsize(&self) -> usize { - self.0.maxsize() - } - - #[inline] - const fn offset_valid(offset: usize, size: usize) -> bool { - let type_size =3D core::mem::size_of::(); - if let Some(end) =3D offset.checked_add(type_size) { - end <=3D size && offset % type_size =3D=3D 0 - } else { - false - } - } + fn maxsize(&self) -> usize; =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing runtime bound checks. #[inline] fn io_addr(&self, offset: usize) -> Result { - if !Self::offset_valid::(offset, self.maxsize()) { + if !offset_valid::(offset, self.maxsize()) { return Err(EINVAL); } =20 @@ -239,50 +242,198 @@ fn io_addr(&self, offset: usize) -> Result= { self.addr().checked_add(offset).ok_or(EINVAL) } =20 + /// Returns the absolute I/O address for a given `offset`, + /// performing compile-time bound checks. #[inline] fn io_addr_assert(&self, offset: usize) -> usize { - build_assert!(Self::offset_valid::(offset, SIZE)); + build_assert!(offset_valid::(offset, Self::MIN_SIZE)); =20 self.addr() + offset } +} + +/// Types implementing this trait (e.g. MMIO BARs or PCI config regions) +/// can share the same IoKnownSize accessors. +/// +/// In this context, "known size" represents the static guarantee regarding +/// the minimum accessible size requested from the I/O backend. +/// +/// Note that the actual size of the resource provided by the hardware +/// (e.g., the physical BAR size) might be larger than this "known size". +pub trait IoKnownSize: IoBase { + /// Infallible 8-bit read with compile-time bounds check. + fn read8(&self, offset: usize) -> u8; + + /// Infallible 16-bit read with compile-time bounds check. + fn read16(&self, offset: usize) -> u16; + + /// Infallible 32-bit read with compile-time bounds check. + fn read32(&self, offset: usize) -> u32; + + /// Infallible 8-bit write with compile-time bounds check. + fn write8(&self, value: u8, offset: usize); + + /// Infallible 16-bit write with compile-time bounds check. + fn write16(&self, value: u16, offset: usize); =20 - define_read!(read8, try_read8, readb -> u8); - define_read!(read16, try_read16, readw -> u16); - define_read!(read32, try_read32, readl -> u32); + /// Infallible 32-bit write with compile-time bounds check. + fn write32(&self, value: u32, offset: usize); +} + +/// Types implementing this trait (e.g. MMIO BARs or PCI config regions) +/// can share the same Io accessors. +/// +/// This trait defines the accessors for performing runtime-checked +/// operations on an I/O region. Note that due to the runtime checks, these +/// operations may be more expensive than those provided by +/// [`IoKnownSize`]. +/// +/// Implement this trait when: +/// - The I/O backend cannot guarantee a minimum accessible size for the +/// region. +/// - The I/O backend wishes to return meaningful error codes when the +/// driver accesses the region. +pub trait Io: IoBase { + /// Fallible 8-bit read with runtime bounds check. + fn try_read8(&self, offset: usize) -> Result; + + /// Fallible 16-bit read with runtime bounds check. + fn try_read16(&self, offset: usize) -> Result; + + /// Fallible 32-bit read with runtime bounds check. + fn try_read32(&self, offset: usize) -> Result; + + /// Fallible 8-bit write with runtime bounds check. + fn try_write8(&self, value: u8, offset: usize) -> Result; + + /// Fallible 16-bit write with runtime bounds check. + fn try_write16(&self, value: u16, offset: usize) -> Result; + + /// Fallible 32-bit write with runtime bounds check. + fn try_write32(&self, value: u32, offset: usize) -> Result; +} + +/// Represents a region of I/O space of a fixed size with 64-bit accessors. +/// Types implementing this trait can share the same IoKnownSize64 +/// accessors. +#[cfg(CONFIG_64BIT)] +pub trait IoKnownSize64: IoKnownSize { + /// Infallible 64-bit read with compile-time bounds check. + fn read64(&self, offset: usize) -> u64; + + /// Infallible 64-bit write with compile-time bounds check. + fn write64(&self, value: u64, offset: usize); +} + +/// Types implementing this trait can share the same Io64 accessors. +#[cfg(CONFIG_64BIT)] +pub trait Io64: Io { + /// Fallible 64-bit read with runtime bounds check. + fn try_read64(&self, offset: usize) -> Result; + + /// Fallible 64-bit write with runtime bounds check. + fn try_write64(&self, value: u64, offset: usize) -> Result; +} + +impl IoBase for Mmio { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of this mapping. + #[inline] + fn addr(&self) -> usize { + self.0.addr() + } + + /// Returns the maximum size of this mapping. + #[inline] + fn maxsize(&self) -> usize { + self.0.maxsize() + } +} + +impl IoKnownSize for Mmio { + define_read!(infallible, read8, readb -> u8); + define_read!(infallible, read16, readw -> u16); + define_read!(infallible, read32, readl -> u32); + + define_write!(infallible, write8, writeb <- u8); + define_write!(infallible, write16, writew <- u16); + define_write!(infallible, write32, writel <- u32); +} + +impl Io for Mmio { + define_read!(fallible, try_read8, readb -> u8); + define_read!(fallible, try_read16, readw -> u16); + define_read!(fallible, try_read32, readl -> u32); + + define_write!(fallible, try_write8, writeb <- u8); + define_write!(fallible, try_write16, writew <- u16); + define_write!(fallible, try_write32, writel <- u32); +} + +#[cfg(CONFIG_64BIT)] +impl IoKnownSize64 for Mmio { + define_read!(infallible, read64, readq -> u64); + + define_write!(infallible, write64, writeq <- u64); +} + +#[cfg(CONFIG_64BIT)] +impl Io64 for Mmio { + define_read!(fallible, try_read64, readq -> u64); + + define_write!(fallible, try_write64, writeq <- u64); +} + +impl Mmio { + /// Converts an `MmioRaw` into an `Mmio` instance, providing the acces= sors to the MMIO mapping. + /// + /// # Safety + /// + /// Callers must ensure that `addr` is the start of a valid I/O mapped= memory region of size + /// `maxsize`. + pub unsafe fn from_raw(raw: &MmioRaw) -> &Self { + // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`. + unsafe { &*core::ptr::from_ref(raw).cast() } + } + + define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8); + define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16); + define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32); define_read!( + infallible, #[cfg(CONFIG_64BIT)] - read64, - try_read64, - readq -> u64 + pub read64_relaxed, + readq_relaxed -> u64 ); =20 - define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8); - define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16); - define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32); + define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8); + define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16); + define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32); define_read!( + fallible, #[cfg(CONFIG_64BIT)] - read64_relaxed, - try_read64_relaxed, + pub try_read64_relaxed, readq_relaxed -> u64 ); =20 - define_write!(write8, try_write8, writeb <- u8); - define_write!(write16, try_write16, writew <- u16); - define_write!(write32, try_write32, writel <- u32); + define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8); + define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16); + define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32); define_write!( + infallible, #[cfg(CONFIG_64BIT)] - write64, - try_write64, - writeq <- u64 + pub write64_relaxed, + writeq_relaxed <- u64 ); =20 - define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8= ); - define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- = u16); - define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- = u32); + define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8); + define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16= ); + define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32= ); define_write!( + fallible, #[cfg(CONFIG_64BIT)] - write64_relaxed, - try_write64_relaxed, + pub try_write64_relaxed, writeq_relaxed <- u64 ); } diff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs index e4878c131c6d..620022cff401 100644 --- a/rust/kernel/io/mem.rs +++ b/rust/kernel/io/mem.rs @@ -16,8 +16,8 @@ Region, Resource, // }, - Io, - IoRaw, // + Mmio, + MmioRaw, // }, prelude::*, }; @@ -212,7 +212,7 @@ pub fn new<'a>(io_request: IoRequest<'a>) -> impl PinIn= it, Error> + } =20 impl Deref for ExclusiveIoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { &self.iomem @@ -226,10 +226,10 @@ fn deref(&self) -> &Self::Target { /// /// # Invariants /// -/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointe= r to the +/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid poin= ter to the /// start of the I/O memory mapped region. pub struct IoMem { - io: IoRaw, + io: MmioRaw, } =20 impl IoMem { @@ -264,7 +264,7 @@ fn ioremap(resource: &Resource) -> Result { return Err(ENOMEM); } =20 - let io =3D IoRaw::new(addr as usize, size)?; + let io =3D MmioRaw::new(addr as usize, size)?; let io =3D IoMem { io }; =20 Ok(io) @@ -287,10 +287,10 @@ fn drop(&mut self) { } =20 impl Deref for IoMem { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: Safe as by the invariant of `IoMem`. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } diff --git a/rust/kernel/io/poll.rs b/rust/kernel/io/poll.rs index b1a2570364f4..75d1b3e8596c 100644 --- a/rust/kernel/io/poll.rs +++ b/rust/kernel/io/poll.rs @@ -45,12 +45,16 @@ /// # Examples /// /// ```no_run -/// use kernel::io::{Io, poll::read_poll_timeout}; +/// use kernel::io::{ +/// Io, +/// Mmio, +/// poll::read_poll_timeout, // +/// }; /// use kernel::time::Delta; /// /// const HW_READY: u16 =3D 0x01; /// -/// fn wait_for_hardware(io: &Io) -> Result { +/// fn wait_for_hardware(io: &Mmio) -> Result { /// read_poll_timeout( /// // The `op` closure reads the value of a specific status regis= ter. /// || io.try_read16(0x1000), @@ -128,12 +132,16 @@ pub fn read_poll_timeout( /// # Examples /// /// ```no_run -/// use kernel::io::{poll::read_poll_timeout_atomic, Io}; +/// use kernel::io::{ +/// Io, +/// Mmio, +/// poll::read_poll_timeout_atomic, // +/// }; /// use kernel::time::Delta; /// /// const HW_READY: u16 =3D 0x01; /// -/// fn wait_for_hardware(io: &Io) -> Result { +/// fn wait_for_hardware(io: &Mmio) -> Result { /// read_poll_timeout_atomic( /// // The `op` closure reads the value of a specific status regis= ter. /// || io.try_read16(0x1000), diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index 70e3854e7d8d..e3377397666e 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -8,8 +8,8 @@ device, devres::Devres, io::{ - Io, - IoRaw, // + Mmio, + MmioRaw, // }, prelude::*, sync::aref::ARef, // @@ -27,7 +27,7 @@ /// memory mapped PCI BAR and its size. pub struct Bar { pdev: ARef, - io: IoRaw, + io: MmioRaw, num: i32, } =20 @@ -63,7 +63,7 @@ pub(super) fn new(pdev: &Device, num: u32, name: &CStr) -= > Result { return Err(ENOMEM); } =20 - let io =3D match IoRaw::new(ioptr, len as usize) { + let io =3D match MmioRaw::new(ioptr, len as usize) { Ok(io) =3D> io, Err(err) =3D> { // SAFETY: @@ -117,11 +117,11 @@ fn drop(&mut self) { } =20 impl Deref for Bar { - type Target =3D Io; + type Target =3D Mmio; =20 fn deref(&self) -> &Self::Target { // SAFETY: By the type invariant of `Self`, the MMIO range in `sel= f.io` is properly mapped. - unsafe { Io::from_raw(&self.io) } + unsafe { Mmio::from_raw(&self.io) } } } =20 diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci= .rs index ef04c6401e6a..f7130a359768 100644 --- a/samples/rust/rust_driver_pci.rs +++ b/samples/rust/rust_driver_pci.rs @@ -7,6 +7,8 @@ use kernel::{ device::Core, devres::Devres, + io::Io, + io::IoKnownSize, pci, prelude::*, sync::aref::ARef, // --=20 2.51.0