From nobody Sun Feb 8 08:27:55 2026 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E28AA2BD5B9 for ; Thu, 15 Jan 2026 16:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768492930; cv=none; b=I1LI3WZf1+UQ792Aokd1ZskyqUDMXaMbDXuajguZPYWxjBLYtlqpKb+iITKHlIIxsTiVpZp3vP1AFnTMnIJ9OOd2r19VELgavuGQrgQvicuCVbAFD1FjRDflFOYXHdhl6ngSUnuEUqc13TDdcBmGQFPw5uDr8o7E+nxrPax09Pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768492930; c=relaxed/simple; bh=1NPuNKvbnM0G7hC3Q3V9qmseyfP5MXAnk1wgBftYtXc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=nXmyoNZzXSO1xGZPiwVLDBC9NOSPgihlpwE2qPiURMlzBxYhHEl6B4YLboV2KI27UnVMB7reR5+3QOzJcaYi5m5glvZgaqJoEeMVS5Fft97AAT2TzB5+OXoB2GLhzHlutFw/nBRJSWtWnKsx1knG7PnhCO3JdbYXoEsCCIXkqjw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=OI6iFBwE; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="OI6iFBwE" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id 8E8C94E420FC; Thu, 15 Jan 2026 16:02:07 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 48AFF606E0; Thu, 15 Jan 2026 16:02:07 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id F3EE710B685A5; Thu, 15 Jan 2026 17:01:59 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1768492922; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding; bh=XyN7Q0dEIRUyruaphCzrkm+AMluGqYLmuayZqMiQbGc=; b=OI6iFBwEe2gf4+8uFT9KMSTaQhH7VX3DtC2Sa9i6LqhCTts6eiweCy92gwFHRdqJrLcSwV gJ8tuTXNxsDGdmvrJXWznCFlpotACmQlYq2SLsmutWhXkMbxrrQb5Aea6Ja6FUps7/UHjV CCpka4S0JoNAckVRX/lqqqCAbjSUYVs3v87bvwohhRTMg6xMJlIldLkkU1B7rrqTU00UrF gmcce4ogBGbiMNjNYAKC4WaPX4232LEUuZfWglK4qvzQ7nw/LOJAWRh2BVSifKwjc/xXt6 zjc6ORpeOulB9py4acOpZzg1n1dlye6i/euUOR80pgBvjncTRDbl0ktSg/x0hA== From: "Herve Codina (Schneider Electric)" To: Wolfram Sang , Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni , Herve Codina Subject: [PATCH] ARM: dts: renesas: r9a06g032: Add support for CPU frequency scaling Date: Thu, 15 Jan 2026 17:01:44 +0100 Message-ID: <20260115160144.1200270-1-herve.codina@bootlin.com> X-Mailer: git-send-email 2.52.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" From: Herve Codina In RZ/N1 SoCs, CPUs are allowed to work at 125, 250 or 500 MHz when the 'ref' clock frequency value is set to 500 MHz which is the default 'ref' clock frequency value. Add support for CPU frequency scaling defining those 3 frequencies in the opp-table with the assumption that the 'ref' clock is set to its default value. Signed-off-by: Herve Codina Signed-off-by: Herve Codina (Schneider Electric) --- arch/arm/boot/dts/renesas/r9a06g032.dtsi | 35 ++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/r= enesas/r9a06g032.dtsi index 8debb77803bb..9f21d8fba940 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -15,6 +15,39 @@ / { #size-cells =3D <1>; interrupt-parent =3D <&gic>; =20 + /* + * The CPUs clock is based on the 'ref' clock (output of OPPDIV divisor) + * with x1, x2 or x4 ratio between the CPUs clock frequency and this + * 'ref' clock frequency. + * + * The table below is built on the assumption that the 'ref' clock + * frequency is set to 500MHz which is its default value. + * + * The table should be overridden in the board device-tree file based + * on the 'ref' clock frequency if this frequency value is not the + * default one. + */ + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-125000000 { + opp-hz =3D /bits/ 64 <125000000>; + /* ~35 clocks cycles at 125mhz */ + clock-latency-ns =3D <300>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + clock-latency-ns =3D <300>; + }; + + opp-500000000 { + opp-hz =3D /bits/ 64 <500000000>; + clock-latency-ns =3D <300>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -24,6 +57,7 @@ cpu@0 { compatible =3D "arm,cortex-a7"; reg =3D <0>; clocks =3D <&sysctrl R9A06G032_CLK_A7MP>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 cpu@1 { @@ -33,6 +67,7 @@ cpu@1 { clocks =3D <&sysctrl R9A06G032_CLK_A7MP>; enable-method =3D "renesas,r9a06g032-smp"; cpu-release-addr =3D <0 0x4000c204>; + operating-points-v2 =3D <&cpu_opp_table>; }; }; =20 --=20 2.52.0