From nobody Sat Feb 7 21:15:26 2026 Received: from out-183.mta1.migadu.com (out-183.mta1.migadu.com [95.215.58.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0910E272813 for ; Thu, 15 Jan 2026 14:52:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.183 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768488751; cv=none; b=LD3dCZAeHSUtxlz+aoz8jeyUAsuqT6yXDZ0+ezQDmT+Qyj618XJSV2+yQHke1YEFVTB2+b4ZKAV8tDX+wnT6lpMf5gtHsgLZ/tqMkbwdJibTEp4uBja9IU0jgofd8UuUEVwLZlieNmHjmChw+hYd+18CL3/cNG4R3B6W1gXtGHc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768488751; c=relaxed/simple; bh=3mGTmt7q51USQSWbL7vHggUS96PKjkh7P6USlUtbMsE=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=lqL6IuSMallRGAnmZRhYfT0wVpSg+wiR7hKJFgWQGfBE7SUTW8q534mOh7PIW2ophiZGtVY+iSwVEPL13+lpn0XUcYd4cdbi5Cbg2uMkZP4Vw9g3pPMA5GNqyZm50I+m2lrFN64hC/MwNTY+eYduj0Gj+DrxHO8QKFj99dG/A74= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=xrENCad4; arc=none smtp.client-ip=95.215.58.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="xrENCad4" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1768488745; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=cl/D6Y5XRR/X0rVkaamOrKMkHf4HUkXbmNOec8DxBHw=; b=xrENCad4vW3ND5AXKrKq00Hm/S2mXOTqE3I5/NOiiGCGlsmgflNe55U+hMK51pjBwGf/gT v1ZTeg4J6zWWOIf+ZDeO8fV8R2vMNWtn7VaBd9Y89Y90FFibiglAttnkl79Aa1Nv4dhtjv ABZjA8gRuKfqnOQx4nXtRZbiwCGINQE= From: Sean Anderson To: Thinh Nguyen , linux-usb@vger.kernel.org Cc: Radhey Shyam Pandey , Neal Frager , Philipp Zabel , Michal Simek , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Greg Kroah-Hartman , Sean Anderson Subject: [PATCH v2] usb: dwc3: Always deassert xilinx resets Date: Thu, 15 Jan 2026 09:51:53 -0500 Message-Id: <20260115145153.3332570-1-sean.anderson@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" I am working on moving serdes initialization to the phy (and consumer) drivers to improve flexibility and boot times (depending on configuration). Currently, core resets are released in the bootloader by init_serdes() in psu_init_gpl.c. In order to remove init_serdes, we need to handle the case where the bootloader never released the core resets. If we don't have a usb3 phy we don't need to assert the core resets, but deassert them anyway to handle this case. We could assert all resets every boot, but I believe the existing procedure is an optimization to reduce boot time when the bootloader has already initialized USB. So this patch preserves the separate code paths. Signed-off-by: Sean Anderson Acked-by: Thinh Nguyen --- Changes in v2: - Update commit message drivers/usb/dwc3/dwc3-xilinx.c | 67 ++++++++++++++++------------------ 1 file changed, 32 insertions(+), 35 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c index 0a8c47876ff9..f41b0da5e89d 100644 --- a/drivers/usb/dwc3/dwc3-xilinx.c +++ b/drivers/usb/dwc3/dwc3-xilinx.c @@ -132,21 +132,6 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *pri= v_data) goto err; } =20 - /* - * The following core resets are not required unless a USB3 PHY - * is used, and the subsequent register settings are not required - * unless a core reset is performed (they should be set properly - * by the first-stage boot loader, but may be reverted by a core - * reset). They may also break the configuration if USB3 is actually - * in use but the usb3-phy entry is missing from the device tree. - * Therefore, skip these operations in this case. - */ - if (!priv_data->usb3_phy) { - /* Deselect the PIPE Clock Select bit in FPD PIPE Clock register */ - writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); - goto skip_usb3_phy; - } - crst =3D devm_reset_control_get_exclusive(dev, "usb_crst"); if (IS_ERR(crst)) { ret =3D PTR_ERR(crst); @@ -171,22 +156,31 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *pr= iv_data) goto err; } =20 - ret =3D reset_control_assert(crst); - if (ret < 0) { - dev_err(dev, "Failed to assert core reset\n"); - goto err; - } + /* + * Asserting the core resets is not required unless a USB3 PHY is used. + * They may also break the configuration if USB3 is actually in use but + * the usb3-phy entry is missing from the device tree. Therefore, skip + * a full reset cycle and just deassert the resets if the phy is + * absent. + */ + if (priv_data->usb3_phy) { + ret =3D reset_control_assert(crst); + if (ret < 0) { + dev_err(dev, "Failed to assert core reset\n"); + goto err; + } =20 - ret =3D reset_control_assert(hibrst); - if (ret < 0) { - dev_err(dev, "Failed to assert hibernation reset\n"); - goto err; - } + ret =3D reset_control_assert(hibrst); + if (ret < 0) { + dev_err(dev, "Failed to assert hibernation reset\n"); + goto err; + } =20 - ret =3D reset_control_assert(apbrst); - if (ret < 0) { - dev_err(dev, "Failed to assert APB reset\n"); - goto err; + ret =3D reset_control_assert(apbrst); + if (ret < 0) { + dev_err(dev, "Failed to assert APB reset\n"); + goto err; + } } =20 ret =3D phy_init(priv_data->usb3_phy); @@ -201,11 +195,15 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *pr= iv_data) goto err; } =20 - /* Set PIPE Power Present signal in FPD Power Present Register*/ - writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT= ); - - /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ - writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + if (priv_data->usb3_phy) { + /* Set PIPE Power Present signal in FPD Power Present Register*/ + writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSN= T); + /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ + writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + } else { + /* Deselect the PIPE Clock Select bit in FPD PIPE Clock register */ + writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); + } =20 ret =3D reset_control_deassert(crst); if (ret < 0) { @@ -225,7 +223,6 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv= _data) goto err; } =20 -skip_usb3_phy: /* ulpi reset via gpio-modepin or gpio-framework driver */ reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(reset_gpio)) { --=20 2.35.1.1320.gc452695387.dirty