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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:41 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v5 08/11] arm64: dts: microchip: add LAN969x support Date: Thu, 15 Jan 2026 12:37:33 +0100 Message-ID: <20260115114021.111324-9-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Microchip LAN969x switch SoC series by adding the SoC DTSI. Signed-off-by: Robert Marko Reviewed-by: Claudiu Beznea Acked-by: Daniel Machon --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v4: * Adapt to clock indexes now being in a DTS header only Changes in v2: * Rename to lan9691 * Split SoC DTSI and evaluation board commits * Use SoC specific compatibles for devices * Alphanumerically sort remaining nodes * Apply DTS coding style arch/arm64/boot/dts/microchip/lan9691.dtsi | 488 +++++++++++++++++++++ 1 file changed, 488 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/lan9691.dtsi diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/d= ts/microchip/lan9691.dtsi new file mode 100644 index 000000000000..235e56bebbdb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include + +#include "clk-lan9691.h" + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + model =3D "Microchip LAN969x"; + compatible =3D "microchip,lan9691"; + interrupt-parent =3D <&gic>; + + clocks { + fx100_clk: fx100-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <320000000>; + }; + + cpu_clk: cpu-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + ddr_clk: ddr-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <600000000>; + }; + + fabric_clk: fabric-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <250000000>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <0x0 0x0>; + next-level-cache =3D <&l2_0>; + }; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* Secure Phys IRQ */ + , /* Non-secure Phys IRQ */ + , /* Virt IRQ */ + ; /* Hyp IRQ */ + }; + + axi: axi { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + usb: usb@300000 { + compatible =3D "microchip,lan9691-dwc3", "snps,dwc3"; + reg =3D <0x300000 0x80000>; + interrupts =3D ; + clocks =3D <&clks GCK_GATE_USB_DRD>, + <&clks GCK_ID_USB_REFCLK>; + clock-names =3D "bus_early", "ref"; + assigned-clocks =3D <&clks GCK_ID_USB_REFCLK>; + assigned-clock-rates =3D <60000000>; + maximum-speed =3D "high-speed"; + dr_mode =3D "host"; + status =3D "disabled"; + }; + + flx0: flexcom@e0040000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0040000 0x100>; + ranges =3D <0x0 0xe0040000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart0: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c0: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + flx1: flexcom@e0044000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0044000 0x100>; + ranges =3D <0x0 0xe0044000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM1>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart1: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + trng: rng@e0048000 { + compatible =3D "microchip,lan9691-trng", "atmel,at91sam9g45-trng"; + reg =3D <0xe0048000 0x100>; + clocks =3D <&fabric_clk>; + status =3D "disabled"; + }; + + aes: crypto@e004c000 { + compatible =3D "microchip,lan9691-aes", "atmel,at91sam9g46-aes"; + reg =3D <0xe004c000 0x100>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(12)>, + <&dma AT91_XDMAC_DT_PERID(13)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "aes_clk"; + status =3D "disabled"; + }; + + flx2: flexcom@e0060000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0060000 0x100>; + ranges =3D <0x0 0xe0060000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart2: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + flx3: flexcom@e0064000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0064000 0x100>; + ranges =3D <0x0 0xe0064000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart3: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + dma: dma-controller@e0068000 { + compatible =3D "microchip,lan9691-dma", "microchip,sama7g5-dma"; + reg =3D <0xe0068000 0x1000>; + interrupts =3D ; + dma-channels =3D <16>; + #dma-cells =3D <1>; + clocks =3D <&fabric_clk>; + clock-names =3D "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible =3D "microchip,lan9691-sha", "atmel,at91sam9g46-sha"; + reg =3D <0xe006c000 0xec>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(14)>; + dma-names =3D "tx"; + clocks =3D <&fabric_clk>; + clock-names =3D "sha_clk"; + status =3D "disabled"; + }; + + timer: timer@e008c000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xe008c000 0x400>; + clocks =3D <&fabric_clk>; + clock-names =3D "timer"; + interrupts =3D ; + status =3D "disabled"; + }; + + watchdog: watchdog@e0090000 { + compatible =3D "snps,dw-wdt"; + reg =3D <0xe0090000 0x1000>; + interrupts =3D ; + clocks =3D <&fabric_clk>; + }; + + cpu_ctrl: syscon@e00c0000 { + compatible =3D "microchip,lan966x-cpu-syscon", "syscon"; + reg =3D <0xe00c0000 0x350>; + }; + + switch: switch@e00c0000 { + compatible =3D "microchip,lan9691-switch"; + reg =3D <0xe00c0000 0x0010000>, + <0xe2010000 0x1410000>; + reg-names =3D "cpu", "devices"; + interrupt-names =3D "xtr", "fdma", "ptp"; + interrupts =3D , + , + ; + resets =3D <&reset 0>; + reset-names =3D "switch"; + status =3D "disabled"; + }; + + clks: clock-controller@e00c00b4 { + compatible =3D "microchip,lan9691-gck"; + reg =3D <0xe00c00b4 0x30>, <0xe00c0308 0x4>; + #clock-cells =3D <1>; + clocks =3D <&cpu_clk>, <&ddr_clk>, <&fx100_clk>; + clock-names =3D "cpu", "ddr", "sys"; + }; + + reset: reset-controller@e201000c { + compatible =3D "microchip,lan9691-switch-reset", + "microchip,lan966x-switch-reset"; + reg =3D <0xe201000c 0x4>; + reg-names =3D "gcb"; + #reset-cells =3D <1>; + cpu-syscon =3D <&cpu_ctrl>; + }; + + gpio: pinctrl@e20100d4 { + compatible =3D "microchip,lan9691-pinctrl"; + reg =3D <0xe20100d4 0xd4>, + <0xe2010370 0xa8>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&gpio 0 0 66>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + mdio0: mdio@e20101a8 { + compatible =3D "microchip,lan9691-miim", "mscc,ocelot-miim"; + reg =3D <0xe20101a8 0x24>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&fx100_clk>; + status =3D "disabled"; + }; + + mdio1: mdio@e20101cc { + compatible =3D "microchip,lan9691-miim", "mscc,ocelot-miim"; + reg =3D <0xe20101cc 0x24>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&fx100_clk>; + status =3D "disabled"; + }; + + sgpio: gpio@e2010230 { + compatible =3D "microchip,lan9691-sgpio", "microchip,sparx5-sgpio"; + reg =3D <0xe2010230 0x118>; + clocks =3D <&fx100_clk>; + resets =3D <&reset 0>; + reset-names =3D "switch"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + sgpio_in: gpio@0 { + compatible =3D "microchip,lan9691-sgpio-bank", + "microchip,sparx5-sgpio-bank"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <3>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + sgpio_out: gpio@1 { + compatible =3D "microchip,lan9691-sgpio-bank", + "microchip,sparx5-sgpio-bank"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <3>; + }; + }; + + tmon: hwmon@e2020100 { + compatible =3D "microchip,lan9691-temp", "microchip,sparx5-temp"; + reg =3D <0xe2020100 0xc>; + clocks =3D <&fx100_clk>; + #thermal-sensor-cells =3D <0>; + }; + + serdes: serdes@e3410000 { + compatible =3D "microchip,lan9691-serdes"; + reg =3D <0xe3410000 0x150000>; + #phy-cells =3D <1>; + clocks =3D <&fabric_clk>; + }; + + gic: interrupt-controller@e8c11000 { + compatible =3D "arm,gic-400"; + reg =3D <0xe8c11000 0x1000>, /* Distributor GICD_ */ + <0xe8c12000 0x2000>, /* CPU interface GICC_ */ + <0xe8c14000 0x2000>, /* Virt interface control */ + <0xe8c16000 0x2000>; /* Virt CPU interface */ + #interrupt-cells =3D <3>; + interrupt-controller; + interrupts =3D ; + }; + }; +}; --=20 2.52.0