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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.40.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:40:45 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v5 01/11] dt-bindings: mfd: atmel,sama5d2-flexcom: add microchip,lan9691-flexcom Date: Thu, 15 Jan 2026 12:37:26 +0100 Message-ID: <20260115114021.111324-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add binding documentation for Microchip LAN969x. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v3: * Pick Acked-by from Conor Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.ya= ml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index c7d6cf96796c..5e5dec2f6564 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -20,6 +20,7 @@ properties: - const: atmel,sama5d2-flexcom - items: - enum: + - microchip,lan9691-flexcom - microchip,sam9x7-flexcom - microchip,sama7d65-flexcom - microchip,sama7g5-flexcom --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f50.google.com (mail-dl1-f50.google.com [74.125.82.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0211379994 for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.40.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:40:53 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v5 02/11] dt-bindings: serial: atmel,at91-usart: add microchip,lan9691-usart Date: Thu, 15 Jan 2026 12:37:27 +0100 Message-ID: <20260115114021.111324-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Microchip LAN969x USART compatible. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v3: * Pick Acked-by from Conor Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml= b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 087a8926f8b4..375cd50bc5cc 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -24,6 +24,7 @@ properties: - const: atmel,at91sam9260-usart - items: - enum: + - microchip,lan9691-usart - microchip,sam9x60-usart - microchip,sam9x7-usart - microchip,sama7d65-usart --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f45.google.com (mail-dl1-f45.google.com [74.125.82.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F379E37BE6F for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.40.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:01 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v5 03/11] dt-bindings: rng: atmel,at91-trng: add microchip,lan9691-trng Date: Thu, 15 Jan 2026 12:37:28 +0100 Message-ID: <20260115114021.111324-4-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Microchip LAN969X TRNG compatible. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v3: * Pick Acked-by from Conor Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml b/D= ocumentation/devicetree/bindings/rng/atmel,at91-trng.yaml index f78614100ea8..3628251b8c51 100644 --- a/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml +++ b/Documentation/devicetree/bindings/rng/atmel,at91-trng.yaml @@ -19,6 +19,7 @@ properties: - microchip,sam9x60-trng - items: - enum: + - microchip,lan9691-trng - microchip,sama7g5-trng - const: atmel,at91sam9g45-trng - items: --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f43.google.com (mail-dl1-f43.google.com [74.125.82.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3474B37B416 for ; Thu, 15 Jan 2026 11:41:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.82.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768477272; cv=none; b=o1eAS9Mk8zw1SEuJUZ7z8jWDvVXvixr1qDKu/xDVsNxvJoZjBwKQTwqBZc3I5pwn4s1fNrBgdJXc4/PkSqQgMMshX7i5zBB6syiZvPMA5Zrq69p3sgrNfqLHcuwZLOE82yVXNDzknSixWSWOw9SckPrcv0QZUZP7CYTij6ckbDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768477272; c=relaxed/simple; bh=ooKaWydLYAU6ZinUS3YSKV/BPM0KTw6HZzaYhJx/zZg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XRykarMIXa/VseMWVESPnQEEWRJ0mIC8qBh1IcWRQq+Ij3oWLTj7/P7W1TaeRNgps4uQpfG3s2320zvvxyhKyjKIK1EmIoDY7pfb8gemh0HcgTVnVDKDllxKPv2I2B3ujQK4QY2bwaLauDYevbwgn874ffeb2cf4NOTIQHae/wo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sartura.hr; spf=pass smtp.mailfrom=sartura.hr; dkim=pass (2048-bit key) header.d=sartura.hr header.i=@sartura.hr header.b=O5lnGvCp; arc=none smtp.client-ip=74.125.82.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sartura.hr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sartura.hr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sartura.hr header.i=@sartura.hr header.b="O5lnGvCp" Received: by mail-dl1-f43.google.com with SMTP id a92af1059eb24-12336c0a8b6so1524288c88.1 for ; Thu, 15 Jan 2026 03:41:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura.hr; s=sartura; t=1768477270; x=1769082070; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jyqWPUPdksTIWYuKZmgo4nd2lHSjHXcu6SXb4jlQ4Xc=; b=O5lnGvCp5bru6pC2QaWeoBDVHfK15uwu/E3xAeyAUrr9SjEKNdMJFD808ELIWWp8/P cT1hffs6A20FXgIcfPjrhRBE/hnQ4mT7Cdn5difSKDrwyd2hfnL+VBgve9xW0YEZo/mK BWpmhZEsY0pVJb3Ze+8VNhQ3fjwCJFeMmyElICoDzR9t7Tm46dWQKLCA3fYhx4CQVHT2 qxTosX+FWOY8D4BqXIDxbpEGADEzw9xh+L8NnwM67RGSd7pTqsiUedvqnRJm6445hNaA pK/cG0ss6J5hDKrm1Ag3z2x/qoAeHC3xbnYbZ8jcUMwAMJUqeCEBR1fGzp9vT/vOqmX6 FI5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768477270; x=1769082070; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=jyqWPUPdksTIWYuKZmgo4nd2lHSjHXcu6SXb4jlQ4Xc=; b=K6vPRLO6sp4R7ZziSipPiBoVtAt9RI6zQmVNcQ7h+q5wWcdnwc8A9yOxFyCsMrUyRQ JFQXHmSIiyqP1iXtARgeUoqJhJHk4Pk48jPLKaOI+h6TPOLiAwG+u1ZY5845yfK6aogb PytY23uUaEtbcZ2hTJJi4aYwV1idyEwdHiozuYsjLdnlsev6UjToBVq1dK4FVobLPVNd 20BOG8b6vpqKP4zVhHdZ+Y+F6uj3Wj7WPR7wilNLm4+Zl0ejfAkSRVOMeLHbyMLEAOxm xSEc7ip2LDD0tt4KK59WJGovQyr2QtMgGokGqzr54ZS9SXPFUUED2EEUxHzlXGGzdSC+ er5g== X-Forwarded-Encrypted: i=1; AJvYcCVt+54/MTVCrFWzfZnuLB8+JvHm1f0tT9RHucy1S52pXiUX4TtKpBFyhZlLK4LO+CMPy+fZlYTncWF157c=@vger.kernel.org X-Gm-Message-State: AOJu0YxT1cNIa8ZUY0p+uvQk7V+Xtxzi6CLl4bDHzWcjvTSMauT4WUfX arsvt00nfjC7rH8U6DMVwjtoBvFN5rypGu/TIrtvmJHBjhUuotgUKql7ehvLHox8Fao= X-Gm-Gg: AY/fxX53v2Js97vgdKE076bRR0x11dCexyMBo5s2cUsHCrz1glUAn6I9tqeUdVaUtrt /dzWdcLtoxfRe4Qk8kXmIrNyQrCfgSjB+mtWIMbvNC0+7YrnPdAPxXMHw24CPhdwiWmR/sDhEL/ sOejr7OcilCB7G1pwyxMsbNyoHY2FYeiFVk1xkm/ypuG9QqEccl+jOehFj5fnazp4zq4Rt/tQZW uYRPTaAUGT0NUiCdDS2gqwQlmf40mublfqoV+Ze+vJzVWewvA/8KJjHZJ6Vc6x/WzVpLNKHbCE0 yvgJcbPJvE8N+ZRLsb8NAPkXhQE/nrNrPKSU7HnmIIXLwSIQFj0A7m2F7KFutaHbQ5qOaE1BvVP eZ1MXqD+cYz/aZZHOc2bPY9aK23WZFoyTQiOEpiwXaA6hB8pGGq/51r70Xe8omjo2v7phx6eJVf 8HcSFx8xjCq8rfmMrcFxL0+oHzPml/ApWR3caHuj/InxVW0JLDkV7CaqC7n4XaFmRqdX+SisCh9 YbVWef3 X-Received: by 2002:a05:701a:ca0e:b0:123:2c98:f6af with SMTP id a92af1059eb24-12336a45a0bmr7461678c88.14.1768477270097; Thu, 15 Jan 2026 03:41:10 -0800 (PST) Received: from fedora (dh207-14-52.xnet.hr. [88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:09 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v5 04/11] dt-bindings: crypto: atmel,at91sam9g46-aes: add microchip,lan9691-aes Date: Thu, 15 Jan 2026 12:37:29 +0100 Message-ID: <20260115114021.111324-5-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Microchip LAN969x AES compatible. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v3: * Pick Acked-by from Conor .../devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes= .yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml index 19010f90198a..f3b6af6baf15 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -16,6 +16,7 @@ properties: - const: atmel,at91sam9g46-aes - items: - enum: + - microchip,lan9691-aes - microchip,sam9x7-aes - microchip,sama7d65-aes - const: atmel,at91sam9g46-aes --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f50.google.com (mail-dl1-f50.google.com [74.125.82.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB7E337F74A for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:17 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v5 05/11] dt-bindings: crypto: atmel,at91sam9g46-sha: add microchip,lan9691-sha Date: Thu, 15 Jan 2026 12:37:30 +0100 Message-ID: <20260115114021.111324-6-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Microchip LAN969x SHA compatible. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v3: * Pick Acked-by from Conor .../devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha= .yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml index 39e076b275b3..16704ff0dd7f 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -16,6 +16,7 @@ properties: - const: atmel,at91sam9g46-sha - items: - enum: + - microchip,lan9691-sha - microchip,sam9x7-sha - microchip,sama7d65-sha - const: atmel,at91sam9g46-sha --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f43.google.com (mail-dl1-f43.google.com [74.125.82.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF9BB37F8A9 for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:25 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v5 06/11] dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x Date: Thu, 15 Jan 2026 12:37:31 +0100 Message-ID: <20260115114021.111324-7-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document LAN969x compatibles for SGPIO. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v3: * Pick Acked-by from Conor .../pinctrl/microchip,sparx5-sgpio.yaml | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgp= io.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.= yaml index fa47732d7cef..9fbbafcdc063 100644 --- a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -21,10 +21,15 @@ properties: pattern: '^gpio@[0-9a-f]+$' =20 compatible: - enum: - - microchip,sparx5-sgpio - - mscc,ocelot-sgpio - - mscc,luton-sgpio + oneOf: + - enum: + - microchip,sparx5-sgpio + - mscc,ocelot-sgpio + - mscc,luton-sgpio + - items: + - enum: + - microchip,lan9691-sgpio + - const: microchip,sparx5-sgpio =20 '#address-cells': const: 1 @@ -80,7 +85,12 @@ patternProperties: type: object properties: compatible: - const: microchip,sparx5-sgpio-bank + oneOf: + - items: + - enum: + - microchip,lan9691-sgpio-bank + - const: microchip,sparx5-sgpio-bank + - const: microchip,sparx5-sgpio-bank =20 reg: description: | --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f47.google.com (mail-dl1-f47.google.com [74.125.82.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E609537F72C for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:33 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v5 07/11] arm64: dts: microchip: add LAN969x clock header file Date: Thu, 15 Jan 2026 12:37:32 +0100 Message-ID: <20260115114021.111324-8-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LAN969x uses hardware clock indexes, so document theses in a header to make them humanly readable. Signed-off-by: Robert Marko Reviewed-by: Claudiu Beznea --- Changes in v5: * Relicense to GPL-2.0-or-later OR MIT to match DTSI arch/arm64/boot/dts/microchip/clk-lan9691.h | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/clk-lan9691.h diff --git a/arch/arm64/boot/dts/microchip/clk-lan9691.h b/arch/arm64/boot/= dts/microchip/clk-lan9691.h new file mode 100644 index 000000000000..0f2d7a0f881e --- /dev/null +++ b/arch/arm64/boot/dts/microchip/clk-lan9691.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */ + +#ifndef _DTS_CLK_LAN9691_H +#define _DTS_CLK_LAN9691_H + +#define GCK_ID_QSPI0 0 +#define GCK_ID_QSPI2 1 +#define GCK_ID_SDMMC0 2 +#define GCK_ID_SDMMC1 3 +#define GCK_ID_MCAN0 4 +#define GCK_ID_MCAN1 5 +#define GCK_ID_FLEXCOM0 6 +#define GCK_ID_FLEXCOM1 7 +#define GCK_ID_FLEXCOM2 8 +#define GCK_ID_FLEXCOM3 9 +#define GCK_ID_TIMER 10 +#define GCK_ID_USB_REFCLK 11 + +/* Gate clocks */ +#define GCK_GATE_USB_DRD 12 +#define GCK_GATE_MCRAMC 13 +#define GCK_GATE_HMATRIX 14 + +#endif --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f41.google.com (mail-dl1-f41.google.com [74.125.82.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1335F37F8A8 for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:41 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v5 08/11] arm64: dts: microchip: add LAN969x support Date: Thu, 15 Jan 2026 12:37:33 +0100 Message-ID: <20260115114021.111324-9-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Microchip LAN969x switch SoC series by adding the SoC DTSI. Signed-off-by: Robert Marko Reviewed-by: Claudiu Beznea Acked-by: Daniel Machon --- Changes in v5: * Pick Reviewed-by from Claudiu Changes in v4: * Adapt to clock indexes now being in a DTS header only Changes in v2: * Rename to lan9691 * Split SoC DTSI and evaluation board commits * Use SoC specific compatibles for devices * Alphanumerically sort remaining nodes * Apply DTS coding style arch/arm64/boot/dts/microchip/lan9691.dtsi | 488 +++++++++++++++++++++ 1 file changed, 488 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/lan9691.dtsi diff --git a/arch/arm64/boot/dts/microchip/lan9691.dtsi b/arch/arm64/boot/d= ts/microchip/lan9691.dtsi new file mode 100644 index 000000000000..235e56bebbdb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/lan9691.dtsi @@ -0,0 +1,488 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include + +#include "clk-lan9691.h" + +/ { + #address-cells =3D <1>; + #size-cells =3D <1>; + + model =3D "Microchip LAN969x"; + compatible =3D "microchip,lan9691"; + interrupt-parent =3D <&gic>; + + clocks { + fx100_clk: fx100-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <320000000>; + }; + + cpu_clk: cpu-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <1000000000>; + }; + + ddr_clk: ddr-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <600000000>; + }; + + fabric_clk: fabric-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <250000000>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a53"; + device_type =3D "cpu"; + reg =3D <0x0 0x0>; + next-level-cache =3D <&l2_0>; + }; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + }; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D ; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , /* Secure Phys IRQ */ + , /* Non-secure Phys IRQ */ + , /* Virt IRQ */ + ; /* Hyp IRQ */ + }; + + axi: axi { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + usb: usb@300000 { + compatible =3D "microchip,lan9691-dwc3", "snps,dwc3"; + reg =3D <0x300000 0x80000>; + interrupts =3D ; + clocks =3D <&clks GCK_GATE_USB_DRD>, + <&clks GCK_ID_USB_REFCLK>; + clock-names =3D "bus_early", "ref"; + assigned-clocks =3D <&clks GCK_ID_USB_REFCLK>; + assigned-clock-rates =3D <60000000>; + maximum-speed =3D "high-speed"; + dr_mode =3D "host"; + status =3D "disabled"; + }; + + flx0: flexcom@e0040000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0040000 0x100>; + ranges =3D <0x0 0xe0040000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart0: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi0: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c0: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + flx1: flexcom@e0044000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0044000 0x100>; + ranges =3D <0x0 0xe0044000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM1>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart1: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi1: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c1: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + trng: rng@e0048000 { + compatible =3D "microchip,lan9691-trng", "atmel,at91sam9g45-trng"; + reg =3D <0xe0048000 0x100>; + clocks =3D <&fabric_clk>; + status =3D "disabled"; + }; + + aes: crypto@e004c000 { + compatible =3D "microchip,lan9691-aes", "atmel,at91sam9g46-aes"; + reg =3D <0xe004c000 0x100>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(12)>, + <&dma AT91_XDMAC_DT_PERID(13)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "aes_clk"; + status =3D "disabled"; + }; + + flx2: flexcom@e0060000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0060000 0x100>; + ranges =3D <0x0 0xe0060000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM2>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart2: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi2: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c2: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + flx3: flexcom@e0064000 { + compatible =3D "microchip,lan9691-flexcom", "atmel,sama5d2-flexcom"; + reg =3D <0xe0064000 0x100>; + ranges =3D <0x0 0xe0064000 0x800>; + clocks =3D <&clks GCK_ID_FLEXCOM3>; + #address-cells =3D <1>; + #size-cells =3D <1>; + status =3D "disabled"; + + usart3: serial@200 { + compatible =3D "microchip,lan9691-usart", "atmel,at91sam9260-usart"; + reg =3D <0x200 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "usart"; + atmel,fifo-size =3D <32>; + atmel,usart-mode =3D ; + status =3D "disabled"; + }; + + spi3: spi@400 { + compatible =3D "microchip,lan9691-spi", "atmel,at91rm9200-spi"; + reg =3D <0x400 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + clock-names =3D "spi_clk"; + #address-cells =3D <1>; + #size-cells =3D <0>; + atmel,fifo-size =3D <32>; + status =3D "disabled"; + }; + + i2c3: i2c@600 { + compatible =3D "microchip,lan9691-i2c", "microchip,sam9x60-i2c"; + reg =3D <0x600 0x200>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names =3D "tx", "rx"; + clocks =3D <&fabric_clk>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + }; + + dma: dma-controller@e0068000 { + compatible =3D "microchip,lan9691-dma", "microchip,sama7g5-dma"; + reg =3D <0xe0068000 0x1000>; + interrupts =3D ; + dma-channels =3D <16>; + #dma-cells =3D <1>; + clocks =3D <&fabric_clk>; + clock-names =3D "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible =3D "microchip,lan9691-sha", "atmel,at91sam9g46-sha"; + reg =3D <0xe006c000 0xec>; + interrupts =3D ; + dmas =3D <&dma AT91_XDMAC_DT_PERID(14)>; + dma-names =3D "tx"; + clocks =3D <&fabric_clk>; + clock-names =3D "sha_clk"; + status =3D "disabled"; + }; + + timer: timer@e008c000 { + compatible =3D "snps,dw-apb-timer"; + reg =3D <0xe008c000 0x400>; + clocks =3D <&fabric_clk>; + clock-names =3D "timer"; + interrupts =3D ; + status =3D "disabled"; + }; + + watchdog: watchdog@e0090000 { + compatible =3D "snps,dw-wdt"; + reg =3D <0xe0090000 0x1000>; + interrupts =3D ; + clocks =3D <&fabric_clk>; + }; + + cpu_ctrl: syscon@e00c0000 { + compatible =3D "microchip,lan966x-cpu-syscon", "syscon"; + reg =3D <0xe00c0000 0x350>; + }; + + switch: switch@e00c0000 { + compatible =3D "microchip,lan9691-switch"; + reg =3D <0xe00c0000 0x0010000>, + <0xe2010000 0x1410000>; + reg-names =3D "cpu", "devices"; + interrupt-names =3D "xtr", "fdma", "ptp"; + interrupts =3D , + , + ; + resets =3D <&reset 0>; + reset-names =3D "switch"; + status =3D "disabled"; + }; + + clks: clock-controller@e00c00b4 { + compatible =3D "microchip,lan9691-gck"; + reg =3D <0xe00c00b4 0x30>, <0xe00c0308 0x4>; + #clock-cells =3D <1>; + clocks =3D <&cpu_clk>, <&ddr_clk>, <&fx100_clk>; + clock-names =3D "cpu", "ddr", "sys"; + }; + + reset: reset-controller@e201000c { + compatible =3D "microchip,lan9691-switch-reset", + "microchip,lan966x-switch-reset"; + reg =3D <0xe201000c 0x4>; + reg-names =3D "gcb"; + #reset-cells =3D <1>; + cpu-syscon =3D <&cpu_ctrl>; + }; + + gpio: pinctrl@e20100d4 { + compatible =3D "microchip,lan9691-pinctrl"; + reg =3D <0xe20100d4 0xd4>, + <0xe2010370 0xa8>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&gpio 0 0 66>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + }; + + mdio0: mdio@e20101a8 { + compatible =3D "microchip,lan9691-miim", "mscc,ocelot-miim"; + reg =3D <0xe20101a8 0x24>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&fx100_clk>; + status =3D "disabled"; + }; + + mdio1: mdio@e20101cc { + compatible =3D "microchip,lan9691-miim", "mscc,ocelot-miim"; + reg =3D <0xe20101cc 0x24>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&fx100_clk>; + status =3D "disabled"; + }; + + sgpio: gpio@e2010230 { + compatible =3D "microchip,lan9691-sgpio", "microchip,sparx5-sgpio"; + reg =3D <0xe2010230 0x118>; + clocks =3D <&fx100_clk>; + resets =3D <&reset 0>; + reset-names =3D "switch"; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + sgpio_in: gpio@0 { + compatible =3D "microchip,lan9691-sgpio-bank", + "microchip,sparx5-sgpio-bank"; + reg =3D <0>; + gpio-controller; + #gpio-cells =3D <3>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + + sgpio_out: gpio@1 { + compatible =3D "microchip,lan9691-sgpio-bank", + "microchip,sparx5-sgpio-bank"; + reg =3D <1>; + gpio-controller; + #gpio-cells =3D <3>; + }; + }; + + tmon: hwmon@e2020100 { + compatible =3D "microchip,lan9691-temp", "microchip,sparx5-temp"; + reg =3D <0xe2020100 0xc>; + clocks =3D <&fx100_clk>; + #thermal-sensor-cells =3D <0>; + }; + + serdes: serdes@e3410000 { + compatible =3D "microchip,lan9691-serdes"; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:49 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko , Conor Dooley Subject: [PATCH v5 09/11] dt-bindings: arm: AT91: document EV23X71A board Date: Thu, 15 Jan 2026 12:37:34 +0100 Message-ID: <20260115114021.111324-10-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Microchip EV23X71A board is an LAN9696 based evaluation board. Signed-off-by: Robert Marko Acked-by: Conor Dooley Reviewed-by: Claudiu Beznea --- Changes in v5: * Pick Acked-by from Conor * Pick Reviewed-by from Claudiu Documentation/devicetree/bindings/arm/atmel-at91.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Docume= ntation/devicetree/bindings/arm/atmel-at91.yaml index 68d306d17c2a..bf161e0950ea 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -243,6 +243,12 @@ properties: - const: microchip,lan9668 - const: microchip,lan966 =20 + - description: Microchip LAN9696 EV23X71A Evaluation Board + items: + - const: microchip,ev23x71a + - const: microchip,lan9696 + - const: microchip,lan9691 + - description: Kontron KSwitch D10 MMT series items: - enum: --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f50.google.com (mail-dl1-f50.google.com [74.125.82.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E80837BE8D for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:41:57 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v5 10/11] dt-bindings: net: sparx5: do not require phys when RGMII is used Date: Thu, 15 Jan 2026 12:37:35 +0100 Message-ID: <20260115114021.111324-11-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LAN969x has 2 dedicated RGMII ports, so regular SERDES lanes are not used for RGMII. So, lets not require phys to be defined when any of the rgmii phy-modes are set. Signed-off-by: Robert Marko Reviewed-by: Rob Herring (Arm) --- .../bindings/net/microchip,sparx5-switch.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.= yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index 5491d0775ede..75c7c8d1f411 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -151,10 +151,23 @@ properties: =20 required: - reg - - phys - phy-mode - microchip,bandwidth =20 + if: + not: + properties: + phy-mode: + contains: + enum: + - rgmii + - rgmii-id + - rgmii-rxid + - rgmii-txid + then: + required: + - phys + oneOf: - required: - phy-handle --=20 2.52.0 From nobody Mon Feb 9 15:11:34 2026 Received: from mail-dl1-f42.google.com (mail-dl1-f42.google.com [74.125.82.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C36DD37C114 for ; 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[88.207.14.52]) by smtp.googlemail.com with ESMTPSA id a92af1059eb24-123370a051esm4875347c88.15.2026.01.15.03.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 03:42:05 -0800 (PST) From: Robert Marko To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@tuxon.dev, herbert@gondor.apana.org.au, davem@davemloft.net, lee@kernel.org, andrew+netdev@lunn.ch, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, Steen.Hegelund@microchip.com, daniel.machon@microchip.com, UNGLinuxDriver@microchip.com, linusw@kernel.org, olivia@selenic.com, richard.genoud@bootlin.com, radu_nicolae.pirea@upb.ro, gregkh@linuxfoundation.org, richardcochran@gmail.com, horatiu.vultur@microchip.com, Ryan.Wanner@microchip.com, tudor.ambarus@linaro.org, kavyasree.kotagiri@microchip.com, lars.povlsen@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, netdev@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org Cc: luka.perkov@sartura.hr, Robert Marko Subject: [PATCH v5 11/11] arm64: dts: microchip: add EV23X71A board Date: Thu, 15 Jan 2026 12:37:36 +0100 Message-ID: <20260115114021.111324-12-robert.marko@sartura.hr> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260115114021.111324-1-robert.marko@sartura.hr> References: <20260115114021.111324-1-robert.marko@sartura.hr> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Microchip EV23X71A is an LAN9696 based evaluation board. Signed-off-by: Robert Marko Acked-by: Daniel Machon Reviewed-by: Claudiu Beznea Tested-by: Daniel Machon --- Changes in v5: * Remove phys property from port 29 * Alphanumericaly sort pin nodes Changes in v2: * Split from SoC DTSI commit * Apply DTS coding style * Enclose array in i2c-mux * Alphanumericaly sort nodes * Change management port mode to RGMII-ID=20 arch/arm64/boot/dts/microchip/Makefile | 1 + .../boot/dts/microchip/lan9696-ev23x71a.dts | 756 ++++++++++++++++++ 2 files changed, 757 insertions(+) create mode 100644 arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/m= icrochip/Makefile index c6e0313eea0f..09d16fc1ce9a 100644 --- a/arch/arm64/boot/dts/microchip/Makefile +++ b/arch/arm64/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_LAN969X) +=3D lan9696-ev23x71a.dtb dtb-$(CONFIG_ARCH_SPARX5) +=3D sparx5_pcb125.dtb dtb-$(CONFIG_ARCH_SPARX5) +=3D sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb dtb-$(CONFIG_ARCH_SPARX5) +=3D sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb diff --git a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts b/arch/arm6= 4/boot/dts/microchip/lan9696-ev23x71a.dts new file mode 100644 index 000000000000..4012ea7d07bb --- /dev/null +++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts @@ -0,0 +1,756 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include "lan9691.dtsi" + +/ { + model =3D "Microchip EV23X71A"; + compatible =3D "microchip,ev23x71a", "microchip,lan9696", "microchip,lan9= 691"; + + aliases { + serial0 =3D &usart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + gpio-restart { + compatible =3D "gpio-restart"; + gpios =3D <&gpio 60 GPIO_ACTIVE_LOW>; + open-source; + priority =3D <200>; + }; + + i2c-mux { + compatible =3D "i2c-mux-gpio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + i2c-parent =3D <&i2c3>; + idle-state =3D <0x8>; + mux-gpios =3D <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>, + <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>; + settle-time-us =3D <100>; + + i2c_sfp0: i2c@0 { + reg =3D <0x0>; + }; + + i2c_sfp1: i2c@1 { + reg =3D <0x1>; + }; + + i2c_sfp2: i2c@2 { + reg =3D <0x2>; + }; + + i2c_sfp3: i2c@3 { + reg =3D <0x3>; + }; + + i2c_poe: i2c@7 { + reg =3D <0x7>; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-status { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio 61 GPIO_ACTIVE_LOW>; + }; + + led-sfp1-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + gpios =3D <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp1-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <0>; + gpios =3D <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp2-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + gpios =3D <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp2-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <1>; + gpios =3D <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp3-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <2>; + gpios =3D <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp3-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <2>; + gpios =3D <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp4-green { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <3>; + gpios =3D <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + + led-sfp4-yellow { + color =3D ; + function =3D LED_FUNCTION_LAN; + function-enumerator =3D <3>; + gpios =3D <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; + default-state =3D "off"; + }; + }; + + mux-controller { + compatible =3D "gpio-mux"; + #mux-control-cells =3D <0>; + mux-gpios =3D <&sgpio_out 1 2 GPIO_ACTIVE_LOW>, + <&sgpio_out 1 3 GPIO_ACTIVE_LOW>; + }; + + sfp0: sfp0 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp0>; + tx-disable-gpios =3D <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp1>; + tx-disable-gpios =3D <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp2 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp2>; + tx-disable-gpios =3D <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible =3D "sff,sfp"; + i2c-bus =3D <&i2c_sfp3>; + tx-disable-gpios =3D <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; + los-gpios =3D <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios =3D <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios =3D <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio { + emmc_sd_pins: emmc-sd-pins { + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ + pins =3D "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", + "GPIO_22", "GPIO_23", "GPIO_24"; + function =3D "emmc_sd"; + }; + + fan_pins: fan-pins { + pins =3D "GPIO_25", "GPIO_26"; + function =3D "fan"; + }; + + fc0_pins: fc0-pins { + pins =3D "GPIO_3", "GPIO_4"; + function =3D "fc"; + }; + + fc2_pins: fc2-pins { + pins =3D "GPIO_64", "GPIO_65", "GPIO_66"; + function =3D "fc"; + }; + + fc3_pins: fc3-pins { + pins =3D "GPIO_55", "GPIO_56"; + function =3D "fc"; + }; + + mdio_irq_pins: mdio-irq-pins { + pins =3D "GPIO_11"; + function =3D "miim_irq"; + }; + + mdio_pins: mdio-pins { + pins =3D "GPIO_9", "GPIO_10"; + function =3D "miim"; + }; + + ptp_ext_pins: ptp-ext-pins { + pins =3D "GPIO_59"; + function =3D "ptpsync_5"; + }; + + ptp_out_pins: ptp-out-pins { + pins =3D "GPIO_58"; + function =3D "ptpsync_4"; + }; + + sgpio_pins: sgpio-pins { + /* SCK, D0, D1, LD */ + pins =3D "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; + function =3D "sgpio_a"; + }; + + usb_over_pins: usb-over-pins { + pins =3D "GPIO_13"; + function =3D "usb_over_detect"; + }; + + usb_power_pins: usb-power-pins { + pins =3D "GPIO_1"; + function =3D "usb_power"; + }; + + usb_rst_pins: usb-rst-pins { + pins =3D "GPIO_12"; + function =3D "usb2phy_rst"; + }; + + usb_ulpi_pins: usb-ulpi-pins { + pins =3D "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; + function =3D "usb_ulpi"; + }; +}; + +&flx0 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&flx2 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&flx3 { + atmel,flexcom-mode =3D ; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-0 =3D <&fc3_pins>; + pinctrl-names =3D "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns =3D <35>; + i2c-sda-hold-time-ns =3D <1500>; + status =3D "okay"; +}; + +&mdio0 { + pinctrl-0 =3D <&mdio_pins>, <&mdio_irq_pins>; + pinctrl-names =3D "default"; + reset-gpios =3D <&gpio 62 GPIO_ACTIVE_LOW>; + status =3D "okay"; + + phy3: phy@3 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <3>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy4: phy@4 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <4>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy5: phy@5 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <5>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy6: phy@6 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <6>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy7: phy@7 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <7>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy8: phy@8 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <8>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy9: phy@9 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <9>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy10: phy@10 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <10>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy11: phy@11 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <11>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy12: phy@12 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <12>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy13: phy@13 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <13>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy14: phy@14 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <14>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy15: phy@15 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <15>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy16: phy@16 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <16>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy17: phy@17 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <17>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy18: phy@18 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <18>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy19: phy@19 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <19>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy20: phy@20 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <20>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy21: phy@21 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <21>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy22: phy@22 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <22>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy23: phy@23 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <23>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy24: phy@24 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <24>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy25: phy@25 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <25>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy26: phy@26 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <26>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; + + phy27: phy@27 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <27>; + interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent =3D <&gpio>; + }; +}; + +&serdes { + status =3D "okay"; +}; + +&sgpio { + pinctrl-0 =3D <&sgpio_pins>; + pinctrl-names =3D "default"; + microchip,sgpio-port-ranges =3D <0 1>, <6 9>; + status =3D "okay"; + + gpio@0 { + ngpios =3D <128>; + }; + gpio@1 { + ngpios =3D <128>; + }; +}; + +&spi2 { + pinctrl-0 =3D <&fc2_pins>; + pinctrl-names =3D "default"; + cs-gpios =3D <&gpio 63 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&switch { + pinctrl-0 =3D <&ptp_out_pins>, <&ptp_ext_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port0: port@0 { + reg =3D <0>; + phy-handle =3D <&phy4>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port1: port@1 { + reg =3D <1>; + phy-handle =3D <&phy5>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port2: port@2 { + reg =3D <2>; + phy-handle =3D <&phy6>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port3: port@3 { + reg =3D <3>; + phy-handle =3D <&phy7>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 0>; + microchip,bandwidth =3D <1000>; + }; + + port4: port@4 { + reg =3D <4>; + phy-handle =3D <&phy8>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port5: port@5 { + reg =3D <5>; + phy-handle =3D <&phy9>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port6: port@6 { + reg =3D <6>; + phy-handle =3D <&phy10>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port7: port@7 { + reg =3D <7>; + phy-handle =3D <&phy11>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 1>; + microchip,bandwidth =3D <1000>; + }; + + port8: port@8 { + reg =3D <8>; + phy-handle =3D <&phy12>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port9: port@9 { + reg =3D <9>; + phy-handle =3D <&phy13>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port10: port@10 { + reg =3D <10>; + phy-handle =3D <&phy14>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port11: port@11 { + reg =3D <11>; + phy-handle =3D <&phy15>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 2>; + microchip,bandwidth =3D <1000>; + }; + + port12: port@12 { + reg =3D <12>; + phy-handle =3D <&phy16>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port13: port@13 { + reg =3D <13>; + phy-handle =3D <&phy17>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port14: port@14 { + reg =3D <14>; + phy-handle =3D <&phy18>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port15: port@15 { + reg =3D <15>; + phy-handle =3D <&phy19>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 3>; + microchip,bandwidth =3D <1000>; + }; + + port16: port@16 { + reg =3D <16>; + phy-handle =3D <&phy20>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port17: port@17 { + reg =3D <17>; + phy-handle =3D <&phy21>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port18: port@18 { + reg =3D <18>; + phy-handle =3D <&phy22>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port19: port@19 { + reg =3D <19>; + phy-handle =3D <&phy23>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 4>; + microchip,bandwidth =3D <1000>; + }; + + port20: port@20 { + reg =3D <20>; + phy-handle =3D <&phy24>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port21: port@21 { + reg =3D <21>; + phy-handle =3D <&phy25>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port22: port@22 { + reg =3D <22>; + phy-handle =3D <&phy26>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port23: port@23 { + reg =3D <23>; + phy-handle =3D <&phy27>; + phy-mode =3D "qsgmii"; + phys =3D <&serdes 5>; + microchip,bandwidth =3D <1000>; + }; + + port24: port@24 { + reg =3D <24>; + phys =3D <&serdes 6>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp0>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <24>; + }; + + port25: port@25 { + reg =3D <25>; + phys =3D <&serdes 7>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp1>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <28>; + }; + + port26: port@26 { + reg =3D <26>; + phys =3D <&serdes 8>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp2>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <32>; + }; + + port27: port@27 { + reg =3D <27>; + phys =3D <&serdes 9>; + phy-mode =3D "10gbase-r"; + sfp =3D <&sfp3>; + managed =3D "in-band-status"; + microchip,bandwidth =3D <10000>; + microchip,sd-sgpio =3D <36>; + }; + + port29: port@29 { + reg =3D <29>; + phy-handle =3D <&phy3>; + phy-mode =3D "rgmii-id"; + microchip,bandwidth =3D <1000>; + }; + }; +}; + +&tmon { + pinctrl-0 =3D <&fan_pins>; + pinctrl-names =3D "default"; +}; + +&usart0 { + pinctrl-0 =3D <&fc0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&usb { + pinctrl-0 =3D <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_= power_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; --=20 2.52.0