From nobody Mon Feb 9 17:34:38 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B03C387560 for ; Thu, 15 Jan 2026 09:29:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469354; cv=none; b=pCqbwzupfhm/mThAG2PZa/2lKdHRID+IXtHJcM/o/wDdU/0J7VIoFYRfHFxWLYItdkl4Lq906xhKwTAIdmoPLNGPmvp6D62d32sPmECj28qQQ6VjGbzjxjTZB8e7k+4fypeYeta/tMBcNarkK7fA0P6kL2EZT/u3AKfIFLBeijo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768469354; c=relaxed/simple; bh=s19WZGnVsjnU3CIa2pjMzvDcR1778Z6ip689C/D4ewo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=EQsVgdpqA30/pjYs0/K6sIEnujDRPf/u31iqrnIrksjQ7NC30GnP28CUTR+eaJ8ddcfZP6M12IUSis5LEzKFD0lXBjc1ccgT4J73rZBw2pyF0k32DdFzCh2Jp7JPUFaQQcdkTyZU7NexOXFYo16qPlNGOhjQIghTxbNvjNT1fqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=B3AduXVj; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=K4/XY2cS; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="B3AduXVj"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="K4/XY2cS" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 60F6gLoV1745958 for ; Thu, 15 Jan 2026 09:29:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=I87OukHNOgS eTgoOXQALSi1N6P0XQunpMCBrwQ4g5NU=; b=B3AduXVji1zoURleuuOhK3oQdx7 6NRuvXB+sflMwvuDIv1ZbZwrMlthUaCrt+U4unJw/WxvIWFyNwrXg82klH8/5um2 pPqulZV8fDFIXu4C0uAeQ7lwhEC3BHYelfi3xQII+X0dDph5cur20zGmuIJNIFjz sukWJw5FFfiY3hiUXzejcvu17NNZv7lEQ7+Hy181VvHmpO2zdXB6jtPXNgOa4NJp 2GuM1PTYnV7tsRlcEtklwvSgdVR554fx3ultDjj1frl9uwGI+/NBDGSVcyK54zb1 Oyaw2y6qyWIh9M6Lch2vmoBVfemxVw+c+pd+M3MpjH9mxvsAvQTsUOq3PGQ== Received: from mail-qv1-f71.google.com (mail-qv1-f71.google.com [209.85.219.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4bptu2gj6y-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 15 Jan 2026 09:29:12 +0000 (GMT) Received: by mail-qv1-f71.google.com with SMTP id 6a1803df08f44-8823f4666abso18260326d6.0 for ; Thu, 15 Jan 2026 01:29:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1768469352; x=1769074152; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I87OukHNOgSeTgoOXQALSi1N6P0XQunpMCBrwQ4g5NU=; b=K4/XY2cSGH2fB5+sZN6mhYPiHKqdjKeM6QptVMCD1+AoiLsr9wychy8Fx7NcpURJdG OfO3w4wnKcsyw2IFYX9cGoPvSYPX+sV7qGqEeJo0fyl7kl6AAHUqo0n5JFPB9Ef0nsno orp4BwUmM2kUgVe9O6GktufCpFk21KREtx8L8fD/RtHIvzOwyswj0vj2BSNfJHhpTn3E kk1Fb9u9ILWZMQX8ZWYVdZyre6/l2D19BKIWJseQxrW5OFYa33IYvigSF2Ay8eZD7bW5 mELtoZAsV+R+Yl7VKVhxqS+TvWaukftlfSAo3fHE1rMDbqcGQLMLBl4Ae4gl/eos7c2D AcHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768469352; x=1769074152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=I87OukHNOgSeTgoOXQALSi1N6P0XQunpMCBrwQ4g5NU=; b=R3GGo/HrUIItMKioVA4Pq7Bw/cCT38oRUXMbNCOijXv7JaSOr/ubeFbPiOTcasf96I gdQQpFwPjiW6Z2kAixzol/H8v2OvIoIo+I5mFs3/HVtAVp3dvUd5wSTLuVcg5hEv9k+q 5gCOimK7e3alKWJx0SurJjPXkLs/KZXlgQqQ3wbQHg8Opj4GcqkS8GK2YIwxqdMH/y0i RLbF0hgQ90JaSCfErFn8VkJ3yWkixxnq81LILbYzA6bdYTgkiVZim2s63sHwLpVOcG42 /VC8XeEQ35gHqsZcB6IFn+I4mdk4DwKoPiV4RCBQ2StLySbMqiEUIX6qRg9CQqYmx+Rl fNpw== X-Forwarded-Encrypted: i=1; AJvYcCVwU6JbkBmivSvkqWfaK68ZBG5D35TQofHyn/e/vR8NfqWCuViLTyoLLEBsxDh4iYwDEiQAFhPTYb3g8ck=@vger.kernel.org X-Gm-Message-State: AOJu0YzBReCU0xq1odKP8OBeoNP1Jt2oqrn96mQOGY8lPdKXnzxu5QBG 2+R2mi7aBxWKYUkaXpxwvyPWtJV8RSfswG+ScirPBWhPFPMMlmQ43DD95c859OyuCBA8Tjmk9SQ jR79DbCy/YLEYy464QwVLOCqOazG0Wr6qCrrQrbDpRJgvX3K4/cpS2XNnhFMw5WzO9/8= X-Gm-Gg: AY/fxX71l3JBfTcFNllZ7awt54YcEDfXYiFtSQmn8eEMq7AdRO4WX873fUvpyHLuR0d YxEihAKk0lYCqua0BV/cZX6hPR+y6fZAKIfdUZlVzG86lq7HiBOAxOxJmMABJFdP8smvNS33qJ6 MM2aaf7FNNXd+uDzxR1PrnigHjkCM+r6Z4xEKUwjRaljZ6HNaG6DmWoYqyZVMCbpJ2E3xmfPK3N 5ZJSJ4DeTJCUhaF4IFaF6FQ/LjpwkZbWp3kG/ZOuzoKL5+a3HIvFXHsm3IjvIxue1bqFV5mxQBI f6LQM0wf5g1vVMSlontzCbkM4ThbkioVs1HZ6jy4FtH/wHPLw2zkTmGeTA3z8kuvJoTcA5QQh2M jisk3Z8U9BQhvCQDaNJ5CljgLTV4tXf9onTm/GB1sxf5n4CB+pv8ul9m3t8sd6pWQClE= X-Received: by 2002:a05:6214:5182:b0:880:5193:10fb with SMTP id 6a1803df08f44-892743c8cc0mr83008346d6.54.1768469351672; Thu, 15 Jan 2026 01:29:11 -0800 (PST) X-Received: by 2002:a05:6214:5182:b0:880:5193:10fb with SMTP id 6a1803df08f44-892743c8cc0mr83008096d6.54.1768469351265; Thu, 15 Jan 2026 01:29:11 -0800 (PST) Received: from yuanjiey.qualcomm.com (Global_NAT1_IAD_FW.qualcomm.com. [129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-892668a2419sm64388416d6.30.2026.01.15.01.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 01:29:11 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v6 08/12] drm/msm/dpu: Add interrupt registers for DPU 13.0.0 Date: Thu, 15 Jan 2026 17:27:45 +0800 Message-Id: <20260115092749.533-9-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260115092749.533-1-yuanjie.yang@oss.qualcomm.com> References: <20260115092749.533-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE1MDA2NSBTYWx0ZWRfXwt2k/OJQ3TJS 0XdlIQYetvhAXqYbo2azYddAjkCMelzjL/hpAkEvfELYZkpq+1iDA1cWK/gEif1F1FpQrQ8LT8s PulGmUwCwJSs6Iwf4zP5CtBitKwg2rJZvkkCKUd8pNGFEKsMS9agYUCgpbYU09xhu9qGLMFRvVo E+0PzTGaJWKhwbrK9KpZKW8vGNnjVIOTQzzSZ/3j88lZ4WGnHRNzi0W5SFckB4lSA769htCl+Rh /uIuycBToNTTJ71q0AjBdD+1WTuAsUsnBRpqcwYPINFoQIvUZVqf4+neKnHFzs2V4WMyJXplWtv vxNAiJBgcHNMQQdD6bfAyl1o5oeUvuYqDwTXluzvc6yY+q8gg6+rDyVyQFZytpxhVgTeGJp+k57 3Ad0QA58PepyeIH/tiCK5x7toPd1+HeA3VD5C/BmTEhWdxDBLYVcBBqu6LkghTPUpVnjh4ak6Xo MuVfk0ymKSJ0NMGGJWQ== X-Proofpoint-ORIG-GUID: eJ9PAsDSsFrZ7U9844r5AxVHPjWnPeLg X-Authority-Analysis: v=2.4 cv=W6Y1lBWk c=1 sm=1 tr=0 ts=6968b368 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=RfJNy9JZAWTFlj1jTG0A:9 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-GUID: eJ9PAsDSsFrZ7U9844r5AxVHPjWnPeLg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-15_02,2026-01-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601150065 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang DPU version 13.0.0 introduces changes to the interrupt register layout. Update the driver to support these modifications for proper interrupt handling. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 ++++++++++++++++++- 1 file changed, 88 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gp= u/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 49bd77a755aa..5b7cd5241f45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -40,6 +40,15 @@ #define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x004) #define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_7xxx_TEAR_O= FF(intf) + 0x008) =20 +#define MDP_INTF_REV_13xx_OFF(intf) (0x18d000 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_EN(intf) (MDP_INTF_REV_13xx_OFF(intf) + 0= x1c0) +#define MDP_INTF_REV_13xx_INTR_STATUS(intf) (MDP_INTF_REV_13xx_OFF(intf) = + 0x1c4) +#define MDP_INTF_REV_13xx_INTR_CLEAR(intf) (MDP_INTF_REV_13xx_OFF(intf) += 0x1c8) +#define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18d800 + 0x1000 * (intf)) +#define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) (MDP_INTF_REV_13xx_TEAR_OFF(= intf) + 0x000) +#define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x004) +#define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) (MDP_INTF_REV_13xx_TEAR_O= FF(intf) + 0x008) + /** * struct dpu_intr_reg - array of DPU register sets * @clr_off: offset to CLEAR reg @@ -199,6 +208,82 @@ static const struct dpu_intr_reg dpu_intr_set_7xxx[] = =3D { }, }; =20 +/* + * dpu_intr_set_13xx - List of DPU interrupt registers for DPU >=3D 13.0 + */ +static const struct dpu_intr_reg dpu_intr_set_13xx[] =3D { + [MDP_SSPP_TOP0_INTR] =3D { + INTR_CLEAR, + INTR_EN, + INTR_STATUS + }, + [MDP_SSPP_TOP0_INTR2] =3D { + INTR2_CLEAR, + INTR2_EN, + INTR2_STATUS + }, + [MDP_SSPP_TOP0_HIST_INTR] =3D { + HIST_INTR_CLEAR, + HIST_INTR_EN, + HIST_INTR_STATUS + }, + [MDP_INTF0_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(0), + MDP_INTF_REV_13xx_INTR_EN(0), + MDP_INTF_REV_13xx_INTR_STATUS(0) + }, + [MDP_INTF1_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_EN(1), + MDP_INTF_REV_13xx_INTR_STATUS(1) + }, + [MDP_INTF1_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(1), + MDP_INTF_REV_13xx_INTR_TEAR_EN(1), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(1) + }, + [MDP_INTF2_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_EN(2), + MDP_INTF_REV_13xx_INTR_STATUS(2) + }, + [MDP_INTF2_TEAR_INTR] =3D { + MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(2), + MDP_INTF_REV_13xx_INTR_TEAR_EN(2), + MDP_INTF_REV_13xx_INTR_TEAR_STATUS(2) + }, + [MDP_INTF3_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(3), + MDP_INTF_REV_13xx_INTR_EN(3), + MDP_INTF_REV_13xx_INTR_STATUS(3) + }, + [MDP_INTF4_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(4), + MDP_INTF_REV_13xx_INTR_EN(4), + MDP_INTF_REV_13xx_INTR_STATUS(4) + }, + [MDP_INTF5_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(5), + MDP_INTF_REV_13xx_INTR_EN(5), + MDP_INTF_REV_13xx_INTR_STATUS(5) + }, + [MDP_INTF6_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(6), + MDP_INTF_REV_13xx_INTR_EN(6), + MDP_INTF_REV_13xx_INTR_STATUS(6) + }, + [MDP_INTF7_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(7), + MDP_INTF_REV_13xx_INTR_EN(7), + MDP_INTF_REV_13xx_INTR_STATUS(7) + }, + [MDP_INTF8_INTR] =3D { + MDP_INTF_REV_13xx_INTR_CLEAR(8), + MDP_INTF_REV_13xx_INTR_EN(8), + MDP_INTF_REV_13xx_INTR_STATUS(8) + }, +}; + #define DPU_IRQ_MASK(irq_idx) (BIT(DPU_IRQ_BIT(irq_idx))) =20 static inline bool dpu_core_irq_is_valid(unsigned int irq_idx) @@ -507,7 +592,9 @@ struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device = *dev, if (!intr) return ERR_PTR(-ENOMEM); =20 - if (m->mdss_ver->core_major_ver >=3D 7) + if (m->mdss_ver->core_major_ver >=3D 13) + intr->intr_set =3D dpu_intr_set_13xx; + else if (m->mdss_ver->core_major_ver >=3D 7) intr->intr_set =3D dpu_intr_set_7xxx; else intr->intr_set =3D dpu_intr_set_legacy; --=20 2.34.1