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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-892668a2419sm64388416d6.30.2026.01.15.01.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 01:29:27 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com Subject: [PATCH v6 10/12] drm/msm/dpu: Add Kaanapali SSPP sub-block support Date: Thu, 15 Jan 2026 17:27:47 +0800 Message-Id: <20260115092749.533-11-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260115092749.533-1-yuanjie.yang@oss.qualcomm.com> References: <20260115092749.533-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: gmAXLgMQ1HqDopxsGor91PmDbCfyMgkz X-Proofpoint-ORIG-GUID: gmAXLgMQ1HqDopxsGor91PmDbCfyMgkz X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE1MDA2NSBTYWx0ZWRfX+MFLRhtjkYy6 EWtNC54xN5eoMqbtrAuwb5zcgcz5LsQ1FHfzwt/ANFt4NffRVT6dpFovMSxhui/GCEWDQB6oH8B 85PjiO/EwxJxH/IlVAX8HqUFn2VpnzzyiiYXyzrC5h2NbLwzvaojf5np/Zrx4a+ysAbuKCfqp/C MaI0iBQ/hwgNxqog9LZOLI+keMRXVCnzfcgI7DUKu9oM56w7zS/f6nfyNl2yEId2WD0snGOZgqT CdvwuR7VN74jQhMlmyDDoJz04evude5cLOLPajY4/LRwRLvmpn21dAEBJEg9nwwckh5LgNtzlp3 SIgl4iP2Nn95g5rDj5XubeCdNFDtc50AG2xgMMCwDfMQy2b6/dF3FwVUX1XGE53PKJq4VkGREkl U9P4WdVh8JM1oW3iVOYbglFHjIS3mjXBBHlbtG5+za0MoWiIJuisCF4ZRdJNIAHYG/tHO/aHdIH iZKuZwSNM9u7nDyagvQ== X-Authority-Analysis: v=2.4 cv=fsHRpV4f c=1 sm=1 tr=0 ts=6968b378 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=IoldKcXwaph4SihcyF8A:9 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-15_02,2026-01-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601150065 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang Add support for Kaanapali platform SSPP sub-blocks, which introduce structural changes including register additions, removals, and relocations. Add the new common and rectangle blocks, and update register definitions and handling to ensure compatibility with DPU v13.0. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Signed-off-by: Yuanjie Yang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/Makefile | 1 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 14 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 4 + .../gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c | 321 ++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 3 + 7 files changed, 371 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 8aa7d07303fb..8b94c5f1cb68 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -86,6 +86,7 @@ msm-display-$(CONFIG_DRM_MSM_DPU) +=3D \ disp/dpu1/dpu_hw_lm.o \ disp/dpu1/dpu_hw_pingpong.o \ disp/dpu1/dpu_hw_sspp.o \ + disp/dpu1/dpu_hw_sspp_v13.o \ disp/dpu1/dpu_hw_dspp.o \ disp/dpu1/dpu_hw_merge3d.o \ disp/dpu1/dpu_hw_top.o \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 4964e70610d1..a056920f890a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -208,6 +208,18 @@ struct dpu_dsc_blk { u32 len; }; =20 +/** + * struct dpu_sspp_v13_rec_blk - SSPP REC sub-blk information + * @name: string name for debug purposes + * @base: offset of this sub-block relative to the block offset + * @len: register block length of this sub-block + */ +struct dpu_sspp_v13_rec_blk { + char name[DPU_HW_BLK_NAME_LEN]; + u32 base; + u32 len; +}; + /** * enum dpu_qos_lut_usage - define QoS LUT use cases */ @@ -294,6 +306,8 @@ struct dpu_sspp_sub_blks { u32 qseed_ver; struct dpu_scaler_blk scaler_blk; struct dpu_pp_blk csc_blk; + struct dpu_sspp_v13_rec_blk sspp_rec0_blk; + struct dpu_sspp_v13_rec_blk sspp_rec1_blk; =20 const u32 *format_list; u32 num_formats; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 197a2c584c73..3a9a14291fff 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -234,6 +234,12 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pip= e *pipe, format_off =3D SSPP_SRC_FORMAT_REC1; } =20 + if (fmt->fetch_mode !=3D MDP_FETCH_LINEAR) { + DPU_REG_WRITE(&ctx->hw, SSPP_FETCH_CONFIG, + DPU_FETCH_CONFIG_RESET_VALUE | + ctx->ubwc->highest_bank_bit << 18); + } + dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off, unpack_pat_off, format_off, SSPP_UBWC_STATIC_CTRL, SSPP_UBWC_ERROR_STATUS); @@ -291,9 +297,6 @@ void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe,= const struct msm_format if (MSM_FORMAT_IS_UBWC(fmt)) opmode |=3D MDSS_MDP_OP_BWC_EN; src_format |=3D (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ - DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, - DPU_FETCH_CONFIG_RESET_VALUE | - ctx->ubwc->highest_bank_bit << 18); switch (ctx->ubwc->ubwc_enc_version) { case UBWC_1_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; @@ -724,7 +727,10 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device= *dev, =20 hw_pipe->mdss_ver =3D mdss_rev; =20 - _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); + if (mdss_rev->core_major_ver >=3D 13) + dpu_hw_sspp_init_v13(hw_pipe, hw_pipe->cap->features, mdss_rev); + else + _setup_layer_ops(hw_pipe, hw_pipe->cap->features, mdss_rev); =20 return hw_pipe; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index df3a320a9151..69d68cc916b2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -384,5 +384,9 @@ void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pi= pe, void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx, bool danger_safe_en, u32 ctrl_off); =20 +void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c, + unsigned long features, + const struct dpu_mdss_version *mdss_rev); + #endif /*_DPU_HW_SSPP_H */ =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c b/drivers/gpu/= drm/msm/disp/dpu1/dpu_hw_sspp_v13.c new file mode 100644 index 000000000000..e65f1fc026fd --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "dpu_hw_sspp.h" + +/* >=3D v13 DPU */ +/* CMN Registers -> Source Surface Processing Pipe Common SSPP registers */ +/* Name Offset */ +#define SSPP_CMN_CLK_CTRL 0x0 +#define SSPP_CMN_CLK_STATUS 0x4 +#define SSPP_CMN_MULTI_REC_OP_MODE 0x10 +#define SSPP_CMN_ADDR_CONFIG 0x14 +#define SSPP_CMN_CAC_CTRL 0x20 +#define SSPP_CMN_SYS_CACHE_MODE 0x24 +#define SSPP_CMN_QOS_CTRL 0x28 + +#define SSPP_CMN_FILL_LEVEL_SCALE 0x3c +#define SSPP_CMN_FILL_LEVELS 0x40 +#define SSPP_CMN_STATUS 0x44 +#define SSPP_CMN_FETCH_DMA_RD_OTS 0x48 +#define SSPP_CMN_FETCH_DTB_WR_PLANE0 0x4c +#define SSPP_CMN_FETCH_DTB_WR_PLANE1 0x50 +#define SSPP_CMN_FETCH_DTB_WR_PLANE2 0x54 +#define SSPP_CMN_DTB_UNPACK_RD_PLANE0 0x58 +#define SSPP_CMN_DTB_UNPACK_RD_PLANE1 0x5c +#define SSPP_CMN_DTB_UNPACK_RD_PLANE2 0x60 +#define SSPP_CMN_UNPACK_LINE_COUNT 0x64 +#define SSPP_CMN_TPG_CONTROL 0x68 +#define SSPP_CMN_TPG_CONFIG 0x6c +#define SSPP_CMN_TPG_COMPONENT_LIMITS 0x70 +#define SSPP_CMN_TPG_RECTANGLE 0x74 +#define SSPP_CMN_TPG_BLACK_WHITE_PATTERN_FRAMES 0x78 +#define SSPP_CMN_TPG_RGB_MAPPING 0x7c +#define SSPP_CMN_TPG_PATTERN_GEN_INIT_VAL 0x80 + +/*RECRegisterset*/ +/*Name Offset*/ +#define SSPP_REC_SRC_FORMAT 0x0 +#define SSPP_REC_SRC_UNPACK_PATTERN 0x4 +#define SSPP_REC_SRC_OP_MODE 0x8 +#define SSPP_REC_SRC_CONSTANT_COLOR 0xc +#define SSPP_REC_SRC_IMG_SIZE 0x10 +#define SSPP_REC_SRC_SIZE 0x14 +#define SSPP_REC_SRC_XY 0x18 +#define SSPP_REC_OUT_SIZE 0x1c +#define SSPP_REC_OUT_XY 0x20 +#define SSPP_REC_SW_PIX_EXT_LR 0x24 +#define SSPP_REC_SW_PIX_EXT_TB 0x28 +#define SSPP_REC_SRC_SIZE_ODX 0x30 +#define SSPP_REC_SRC_XY_ODX 0x34 +#define SSPP_REC_OUT_SIZE_ODX 0x38 +#define SSPP_REC_OUT_XY_ODX 0x3c +#define SSPP_REC_SW_PIX_EXT_LR_ODX 0x40 +#define SSPP_REC_SW_PIX_EXT_TB_ODX 0x44 +#define SSPP_REC_PRE_DOWN_SCALE 0x48 +#define SSPP_REC_SRC0_ADDR 0x4c +#define SSPP_REC_SRC1_ADDR 0x50 +#define SSPP_REC_SRC2_ADDR 0x54 +#define SSPP_REC_SRC3_ADDR 0x58 +#define SSPP_REC_SRC_YSTRIDE0 0x5c +#define SSPP_REC_SRC_YSTRIDE1 0x60 +#define SSPP_REC_CURRENT_SRC0_ADDR 0x64 +#define SSPP_REC_CURRENT_SRC1_ADDR 0x68 +#define SSPP_REC_CURRENT_SRC2_ADDR 0x6c +#define SSPP_REC_CURRENT_SRC3_ADDR 0x70 +#define SSPP_REC_SRC_ADDR_SW_STATUS 0x74 +#define SSPP_REC_CDP_CNTL 0x78 +#define SSPP_REC_TRAFFIC_SHAPER 0x7c +#define SSPP_REC_TRAFFIC_SHAPER_PREFILL 0x80 +#define SSPP_REC_PD_MEM_ALLOC 0x84 +#define SSPP_REC_QOS_CLAMP 0x88 +#define SSPP_REC_UIDLE_CTRL_VALUE 0x8c +#define SSPP_REC_UBWC_STATIC_CTRL 0x90 +#define SSPP_REC_UBWC_STATIC_CTRL_OVERRIDE 0x94 +#define SSPP_REC_UBWC_STATS_ROI 0x98 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI0 0x9c +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI0 0xa0 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI1 0xa4 +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI1 0xa8 +#define SSPP_REC_UBWC_STATS_WORST_TILE_ROW_BW_ROI2 0xac +#define SSPP_REC_UBWC_STATS_TOTAL_BW_ROI2 0xb0 +#define SSPP_REC_EXCL_REC_CTRL 0xb4 +#define SSPP_REC_EXCL_REC_SIZE 0xb8 +#define SSPP_REC_EXCL_REC_XY 0xbc +#define SSPP_REC_LINE_INSERTION_CTRL 0xc0 +#define SSPP_REC_LINE_INSERTION_OUT_SIZE 0xc4 +#define SSPP_REC_FETCH_PIPE_ACTIVE 0xc8 +#define SSPP_REC_META_ERROR_STATUS 0xcc +#define SSPP_REC_UBWC_ERROR_STATUS 0xd0 +#define SSPP_REC_FLUSH_CTRL 0xd4 +#define SSPP_REC_INTR_EN 0xd8 +#define SSPP_REC_INTR_STATUS 0xdc +#define SSPP_REC_INTR_CLEAR 0xe0 +#define SSPP_REC_HSYNC_STATUS 0xe4 +#define SSPP_REC_FP16_CONFIG 0x150 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_0 0x154 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_R_1 0x158 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_0 0x15c +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_G_1 0x160 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_0 0x164 +#define SSPP_REC_FP16_CSC_MATRIX_COEFF_B_1 0x168 +#define SSPP_REC_FP16_CSC_PRE_CLAMP_R 0x16c +#define SSPP_REC_FP16_CSC_PRE_CLAMP_G 0x170 +#define SSPP_REC_FP16_CSC_PRE_CLAMP_B 0x174 +#define SSPP_REC_FP16_CSC_POST_CLAMP 0x178 + +static inline u32 dpu_hw_sspp_calculate_rect_off(enum dpu_sspp_multirect_i= ndex rect_index, + struct dpu_hw_sspp *ctx) +{ + return (rect_index =3D=3D DPU_SSPP_RECT_SOLO || rect_index =3D=3D DPU_SSP= P_RECT_0) ? + ctx->cap->sblk->sspp_rec0_blk.base : ctx->cap->sblk->sspp_rec1_blk.base; +} + +static void dpu_hw_sspp_setup_multirect_v13(struct dpu_sw_pipe *pipe) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + + if (!ctx) + return; + + dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_CMN_MULTI_REC_OP_MODE); +} + +static void dpu_hw_sspp_setup_format_v13(struct dpu_sw_pipe *pipe, + const struct msm_format *fmt, u32 flags) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 op_mode_off, unpack_pat_off, format_off; + u32 ubwc_ctrl_off, ubwc_err_off; + u32 offset; + + if (!ctx || !fmt) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + + op_mode_off =3D offset + SSPP_REC_SRC_OP_MODE; + unpack_pat_off =3D offset + SSPP_REC_SRC_UNPACK_PATTERN; + format_off =3D offset + SSPP_REC_SRC_FORMAT; + ubwc_ctrl_off =3D offset + SSPP_REC_UBWC_STATIC_CTRL; + ubwc_err_off =3D offset + SSPP_REC_UBWC_ERROR_STATUS; + + dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off, + unpack_pat_off, format_off, ubwc_ctrl_off, ubwc_err_off); +} + +static void dpu_hw_sspp_setup_pe_config_v13(struct dpu_hw_sspp *ctx, + struct dpu_hw_pixel_ext *pe_ext) +{ + struct dpu_hw_blk_reg_map *c; + u8 color; + u32 lr_pe[4], tb_pe[4]; + const u32 bytemask =3D 0xff; + u32 offset =3D ctx->cap->sblk->sspp_rec0_blk.base; + + if (!ctx || !pe_ext) + return; + + c =3D &ctx->hw; + /* program SW pixel extension override for all pipes*/ + for (color =3D 0; color < DPU_MAX_PLANES; color++) { + /* color 2 has the same set of registers as color 1 */ + if (color =3D=3D 2) + continue; + + lr_pe[color] =3D ((pe_ext->right_ftch[color] & bytemask) << 24) | + ((pe_ext->right_rpt[color] & bytemask) << 16) | + ((pe_ext->left_ftch[color] & bytemask) << 8) | + (pe_ext->left_rpt[color] & bytemask); + + tb_pe[color] =3D ((pe_ext->btm_ftch[color] & bytemask) << 24) | + ((pe_ext->btm_rpt[color] & bytemask) << 16) | + ((pe_ext->top_ftch[color] & bytemask) << 8) | + (pe_ext->top_rpt[color] & bytemask); + } + + /* color 0 */ + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR + offset, lr_pe[0]); + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB + offset, tb_pe[0]); + + /* color 1 and color 2 */ + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_LR_ODX + offset, lr_pe[1]); + DPU_REG_WRITE(c, SSPP_REC_SW_PIX_EXT_TB_ODX + offset, tb_pe[1]); +} + +static void dpu_hw_sspp_setup_rects_v13(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *cfg) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 src_size_off, src_xy_off, out_size_off, out_xy_off; + u32 offset; + + if (!ctx || !cfg) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + + src_size_off =3D offset + SSPP_REC_SRC_SIZE; + src_xy_off =3D offset + SSPP_REC_SRC_XY; + out_size_off =3D offset + SSPP_REC_OUT_SIZE; + out_xy_off =3D offset + SSPP_REC_OUT_XY; + + dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off, + src_xy_off, out_size_off, out_xy_off); +} + +static void dpu_hw_sspp_setup_sourceaddress_v13(struct dpu_sw_pipe *pipe, + struct dpu_hw_fmt_layout *layout) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + int i; + u32 offset, ystride0, ystride1; + + if (!ctx) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + + for (i =3D 0; i < ARRAY_SIZE(layout->plane_addr); i++) + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC0_ADDR + i * 0x4, + layout->plane_addr[i]); + + ystride0 =3D (layout->plane_pitch[0]) | (layout->plane_pitch[2] << 16); + ystride1 =3D (layout->plane_pitch[1]) | (layout->plane_pitch[3] << 16); + + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE0, ystride0); + DPU_REG_WRITE(&ctx->hw, offset + SSPP_REC_SRC_YSTRIDE1, ystride1); +} + +static void dpu_hw_sspp_setup_solidfill_v13(struct dpu_sw_pipe *pipe, u32 = color) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 const_clr_off; + u32 offset; + + if (!ctx) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + const_clr_off =3D offset + SSPP_REC_SRC_CONSTANT_COLOR; + + dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off); +} + +static void dpu_hw_sspp_setup_qos_lut_v13(struct dpu_hw_sspp *ctx, + struct dpu_hw_qos_cfg *cfg) +{ + if (!ctx || !cfg) + return; + + dpu_hw_setup_qos_lut_v13(&ctx->hw, cfg); +} + +static void dpu_hw_sspp_setup_qos_ctrl_v13(struct dpu_hw_sspp *ctx, + bool danger_safe_en) +{ + if (!ctx) + return; + + dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_CMN_QOS_CTRL); +} + +static void dpu_hw_sspp_setup_cdp_v13(struct dpu_sw_pipe *pipe, + const struct msm_format *fmt, + bool enable) +{ + struct dpu_hw_sspp *ctx =3D pipe->sspp; + u32 offset =3D 0; + + if (!ctx) + return; + + offset =3D dpu_hw_sspp_calculate_rect_off(pipe->multirect_index, ctx); + dpu_setup_cdp(&ctx->hw, offset + SSPP_REC_CDP_CNTL, fmt, enable); +} + +static bool dpu_hw_sspp_setup_clk_force_ctrl_v13(struct dpu_hw_sspp *ctx, = bool enable) +{ + static const struct dpu_clk_ctrl_reg sspp_clk_ctrl =3D { + .reg_off =3D SSPP_CMN_CLK_CTRL, + .bit_off =3D 0 + }; + + return dpu_hw_clk_force_ctrl(&ctx->hw, &sspp_clk_ctrl, enable); +} + +void dpu_hw_sspp_init_v13(struct dpu_hw_sspp *c, + unsigned long features, const struct dpu_mdss_version *mdss_rev) +{ + c->ops.setup_format =3D dpu_hw_sspp_setup_format_v13; + c->ops.setup_rects =3D dpu_hw_sspp_setup_rects_v13; + c->ops.setup_sourceaddress =3D dpu_hw_sspp_setup_sourceaddress_v13; + c->ops.setup_solidfill =3D dpu_hw_sspp_setup_solidfill_v13; + c->ops.setup_pe =3D dpu_hw_sspp_setup_pe_config_v13; + + if (test_bit(DPU_SSPP_QOS, &features)) { + c->ops.setup_qos_lut =3D dpu_hw_sspp_setup_qos_lut_v13; + c->ops.setup_qos_ctrl =3D dpu_hw_sspp_setup_qos_ctrl_v13; + } + + if (test_bit(DPU_SSPP_CSC, &features) || + test_bit(DPU_SSPP_CSC_10BIT, &features)) + c->ops.setup_csc =3D dpu_hw_sspp_setup_csc; + + if (test_bit(DPU_SSPP_SMART_DMA_V1, &c->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) + c->ops.setup_multirect =3D dpu_hw_sspp_setup_multirect_v13; + + if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features)) + c->ops.setup_scaler =3D dpu_hw_sspp_setup_scaler3; + + if (test_bit(DPU_SSPP_CDP, &features)) + c->ops.setup_cdp =3D dpu_hw_sspp_setup_cdp_v13; + + c->ops.setup_clk_force_ctrl =3D dpu_hw_sspp_setup_clk_force_ctrl_v13; +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.c index 486be346d40d..c7a5f4a0d054 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -81,6 +81,13 @@ static u32 dpu_hw_util_log_mask =3D DPU_DBG_MASK_NONE; #define QOS_CREQ_LUT_0 0x14 #define QOS_CREQ_LUT_1 0x18 =20 +/* CMN_QOS_LUT */ +#define SSPP_CMN_QOS_CTRL 0x28 +#define SSPP_CMN_DANGER_LUT 0x2c +#define SSPP_CMN_SAFE_LUT 0x30 +#define SSPP_CMN_CREQ_LUT_0 0x34 +#define SSPP_CMN_CREQ_LUT_1 0x38 + /* QOS_QOS_CTRL */ #define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0) #define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4) @@ -475,6 +482,17 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *= c, u32 offset, cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); } =20 +void dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, + const struct dpu_hw_qos_cfg *cfg) +{ + DPU_REG_WRITE(c, SSPP_CMN_DANGER_LUT, cfg->danger_lut); + DPU_REG_WRITE(c, SSPP_CMN_SAFE_LUT, cfg->safe_lut); + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_0, cfg->creq_lut); + DPU_REG_WRITE(c, SSPP_CMN_CREQ_LUT_1, cfg->creq_lut >> 32); + DPU_REG_WRITE(c, SSPP_CMN_QOS_CTRL, + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); +} + /* * note: Aside from encoders, input_sel should be set to 0x0 by default */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_util.h index 6fe65bc3bff4..628befc65ce3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -367,6 +367,9 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c= , u32 offset, bool qos_8lvl, const struct dpu_hw_qos_cfg *cfg); =20 +void dpu_hw_setup_qos_lut_v13(struct dpu_hw_blk_reg_map *c, + const struct dpu_hw_qos_cfg *cfg); + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, u8 input_sel); =20 --=20 2.34.1