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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-892668a2419sm64388416d6.30.2026.01.15.01.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 01:29:19 -0800 (PST) From: yuanjie yang To: robin.clark@oss.qualcomm.com, lumag@kernel.org, jesszhan0024@gmail.com, sean@poorly.run, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, tingwei.zhang@oss.qualcomm.com, aiqun.yu@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, Dmitry Baryshkov Subject: [PATCH v6 09/12] drm/msm/dpu: Refactor SSPP to compatible DPU 13.0.0 Date: Thu, 15 Jan 2026 17:27:46 +0800 Message-Id: <20260115092749.533-10-yuanjie.yang@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260115092749.533-1-yuanjie.yang@oss.qualcomm.com> References: <20260115092749.533-1-yuanjie.yang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=NvncssdJ c=1 sm=1 tr=0 ts=6968b370 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Qg1eW3vjq6ATntrd7kwA:9 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-ORIG-GUID: _ux9EoWMngQXzPurNyO2RTNZIbdRKfLB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTE1MDA2NSBTYWx0ZWRfXxxVkePeLNHPZ 488BkFWGlnFj++czSRK9WkhHe1lrhpJM6PJHCvnCJ5IIBg2bEdefbUbpWtT3BFy28mz7knL6BOd gm9JAScKecA2l4/pOuIOHbG6VmvwWfdveuM0OjZIfmyRPICPssgidvSbCAfzIa7OX2LG2axhZQm APE0C/Tm+IjWgDRUpsh3Nzk0nvlOif8DrLNMU2KJEgu0Xt5onDmaxIHVCmoSl5jJe/DmAgWQDPo 4KJleIzgaTj+yq58+5PZgc2d7Jc+VFvztJxPTDnH5SDo5yVpABealez6RlEWjhazFVsusRFN3Oo C4pb/Hc6UuDtrGk1M0cbuO4HyQCs+C2uAa5zaZ9af9ZR2L/xPxqBYvGKxlhNV17bX+D75hY1Y+I qUQuUacViWpXo9fs2yT3hooFQgpefs5/3he6zcgFm8bVfPocieH3w+V0FOoP7m4HGarq5sYQV1/ ixlDsZfuYVrLZuA5hdw== X-Proofpoint-GUID: _ux9EoWMngQXzPurNyO2RTNZIbdRKfLB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-15_02,2026-01-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 suspectscore=0 bulkscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601150065 Content-Type: text/plain; charset="utf-8" From: Yuanjie Yang DPU version 13.0.0 introduces structural changes including register additions, removals, and relocations. Refactor SSPP-related code to be compatible with DPU 13.0.0 modifications. Co-developed-by: Yongxing Mou Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Signed-off-by: Yuanjie Yang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 110 ++++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 52 +++++++++ 2 files changed, 116 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.c index 6f1fc790ad6d..197a2c584c73 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -145,11 +145,18 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_pipe *pipe) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - u32 mode_mask; =20 if (!ctx) return; =20 + dpu_hw_setup_multirect_impl(pipe, ctx, SSPP_MULTIRECT_OPMODE); +} + +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, u32 op_mode_off) +{ + u32 mode_mask; + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO) { /** * if rect index is RECT_SOLO, we cannot expect a @@ -158,7 +165,7 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw_p= ipe *pipe) */ mode_mask =3D 0; } else { - mode_mask =3D DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE); + mode_mask =3D DPU_REG_READ(&ctx->hw, op_mode_off); mode_mask |=3D pipe->multirect_index; if (pipe->multirect_mode =3D=3D DPU_SSPP_MULTIRECT_TIME_MX) mode_mask |=3D BIT(2); @@ -166,10 +173,10 @@ static void dpu_hw_sspp_setup_multirect(struct dpu_sw= _pipe *pipe) mode_mask &=3D ~BIT(2); } =20 - DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE, mode_mask); + DPU_REG_WRITE(&ctx->hw, op_mode_off, mode_mask); } =20 -static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; @@ -189,7 +196,7 @@ static void _sspp_setup_opmode(struct dpu_hw_sspp *ctx, DPU_REG_WRITE(&ctx->hw, sblk->scaler_blk.base + SSPP_VIG_OP_MODE, opmode); } =20 -static void _sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, u32 mask, u8 en) { const struct dpu_sspp_sub_blks *sblk =3D ctx->cap->sblk; @@ -211,10 +218,6 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pip= e *pipe, const struct msm_format *fmt, u32 flags) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 chroma_samp, unpack, src_format; - u32 opmode =3D 0; - u32 fast_clear =3D 0; u32 op_mode_off, unpack_pat_off, format_off; =20 if (!ctx || !fmt) @@ -231,6 +234,21 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pip= e *pipe, format_off =3D SSPP_SRC_FORMAT_REC1; } =20 + dpu_hw_setup_format_impl(pipe, fmt, flags, ctx, op_mode_off, + unpack_pat_off, format_off, + SSPP_UBWC_STATIC_CTRL, SSPP_UBWC_ERROR_STATUS); +} + +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_f= ormat *fmt, + u32 flags, struct dpu_hw_sspp *ctx, u32 op_mode_off, + u32 unpack_pat_off, u32 format_off, u32 ubwc_ctrl_off, + u32 ubwc_err_off) +{ + struct dpu_hw_blk_reg_map *c; + u32 chroma_samp, unpack, src_format; + u32 opmode; + u32 fast_clear; + c =3D &ctx->hw; opmode =3D DPU_REG_READ(c, op_mode_off); opmode &=3D ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | @@ -279,24 +297,24 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, switch (ctx->ubwc->ubwc_enc_version) { case UBWC_1_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | BIT(8) | (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_2_0: fast_clear =3D fmt->alpha_enable ? BIT(31) : 0; - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, fast_clear | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_3_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, BIT(30) | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; case UBWC_4_0: - DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, + DPU_REG_WRITE(c, ubwc_ctrl_off, MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; } @@ -313,10 +331,10 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pi= pe *pipe, =20 /* update scaler opmode, if appropriate */ if (test_bit(DPU_SSPP_CSC, &ctx->cap->features)) - _sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, + dpu_hw_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT, MSM_FORMAT_IS_YUV(fmt)); else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features)) - _sspp_setup_csc10_opmode(ctx, + dpu_hw_sspp_setup_csc10_opmode(ctx, VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, MSM_FORMAT_IS_YUV(fmt)); =20 @@ -325,7 +343,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe= *pipe, DPU_REG_WRITE(c, op_mode_off, opmode); =20 /* clear previous UBWC error */ - DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS, BIT(31)); + DPU_REG_WRITE(c, ubwc_err_off, BIT(31)); } =20 static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_sspp *ctx, @@ -385,7 +403,7 @@ static void dpu_hw_sspp_setup_pe_config(struct dpu_hw_s= spp *ctx, tot_req_pixels[3]); } =20 -static void _dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, struct dpu_hw_scaler3_cfg *scaler3_cfg, const struct msm_format *format) { @@ -405,15 +423,11 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pip= e *pipe, struct dpu_sw_pipe_cfg *cfg) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_blk_reg_map *c; - u32 src_size, src_xy, dst_size, dst_xy; u32 src_size_off, src_xy_off, out_size_off, out_xy_off; =20 if (!ctx || !cfg) return; =20 - c =3D &ctx->hw; - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) { src_size_off =3D SSPP_SRC_SIZE; @@ -427,20 +441,8 @@ static void dpu_hw_sspp_setup_rects(struct dpu_sw_pipe= *pipe, out_xy_off =3D SSPP_OUT_XY_REC1; } =20 - - /* src and dest rect programming */ - src_xy =3D (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; - src_size =3D (drm_rect_height(&cfg->src_rect) << 16) | - drm_rect_width(&cfg->src_rect); - dst_xy =3D (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; - dst_size =3D (drm_rect_height(&cfg->dst_rect) << 16) | - drm_rect_width(&cfg->dst_rect); - - /* rectangle register programming */ - DPU_REG_WRITE(c, src_size_off, src_size); - DPU_REG_WRITE(c, src_xy_off, src_xy); - DPU_REG_WRITE(c, out_size_off, dst_size); - DPU_REG_WRITE(c, out_xy_off, dst_xy); + dpu_hw_setup_rects_impl(pipe, cfg, ctx, src_size_off, + src_xy_off, out_size_off, out_xy_off); } =20 static void dpu_hw_sspp_setup_sourceaddress(struct dpu_sw_pipe *pipe, @@ -497,7 +499,7 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_= sw_pipe *pipe, DPU_REG_WRITE(&ctx->hw, SSPP_SRC_YSTRIDE1, ystride1); } =20 -static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, const struct dpu_csc_cfg *data) { u32 offset; @@ -519,21 +521,31 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp = *ctx, static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 colo= r) { struct dpu_hw_sspp *ctx =3D pipe->sspp; - struct dpu_hw_fmt_layout cfg; + u32 const_clr_off; =20 if (!ctx) return; =20 + if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || + pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR; + else + const_clr_off =3D SSPP_SRC_CONSTANT_COLOR_REC1; + + dpu_hw_setup_solidfill_impl(pipe, color, ctx, const_clr_off); +} + +void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe, + u32 color, struct dpu_hw_sspp *ctx, + u32 const_clr_off) +{ + struct dpu_hw_fmt_layout cfg; + /* cleanup source addresses */ memset(&cfg, 0, sizeof(cfg)); ctx->ops.setup_sourceaddress(pipe, &cfg); =20 - if (pipe->multirect_index =3D=3D DPU_SSPP_RECT_SOLO || - pipe->multirect_index =3D=3D DPU_SSPP_RECT_0) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR, color); - else - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1, - color); + DPU_REG_WRITE(&ctx->hw, const_clr_off, color); } =20 static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx, @@ -547,14 +559,20 @@ static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_s= spp *ctx, cfg); } =20 +void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx, + bool danger_safe_en, u32 ctrl_off) +{ + DPU_REG_WRITE(&ctx->hw, ctrl_off, + danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); +} + static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, bool danger_safe_en) { if (!ctx) return; =20 - DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, - danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); + dpu_hw_sspp_setup_qos_ctrl_impl(ctx, danger_safe_en, SSPP_QOS_CTRL); } =20 static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, @@ -609,7 +627,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, c->ops.setup_multirect =3D dpu_hw_sspp_setup_multirect; =20 if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features)) - c->ops.setup_scaler =3D _dpu_hw_sspp_setup_scaler3; + c->ops.setup_scaler =3D dpu_hw_sspp_setup_scaler3; =20 if (test_bit(DPU_SSPP_CDP, &features)) c->ops.setup_cdp =3D dpu_hw_sspp_setup_cdp; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_sspp.h index 3822094f85bc..df3a320a9151 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -332,5 +332,57 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(struct drm_device= *dev, int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms = *kms, struct dentry *entry); =20 +void dpu_hw_sspp_setup_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void dpu_hw_sspp_setup_csc10_opmode(struct dpu_hw_sspp *ctx, + u32 mask, u8 en); + +void dpu_hw_sspp_setup_scaler3(struct dpu_hw_sspp *ctx, + struct dpu_hw_scaler3_cfg *scaler3_cfg, + const struct msm_format *format); + +void dpu_hw_sspp_setup_csc(struct dpu_hw_sspp *ctx, + const struct dpu_csc_cfg *data); + +void dpu_hw_setup_multirect_impl(struct dpu_sw_pipe *pipe, + struct dpu_hw_sspp *ctx, + u32 op_mode_off); + +void dpu_hw_setup_format_impl(struct dpu_sw_pipe *pipe, const struct msm_f= ormat *fmt, + u32 flags, struct dpu_hw_sspp *ctx, + u32 op_mode_off, u32 unpack_pat_off, u32 format_off, + u32 ubwc_ctrl_off, u32 ubwc_err_off); + +static inline void dpu_hw_setup_rects_impl(struct dpu_sw_pipe *pipe, struc= t dpu_sw_pipe_cfg *cfg, + struct dpu_hw_sspp *ctx, u32 src_size_off, + u32 src_xy_off, u32 out_size_off, u32 out_xy_off) +{ + struct dpu_hw_blk_reg_map *c; + u32 src_size, src_xy, dst_size, dst_xy; + + c =3D &ctx->hw; + + /* src and dest rect programming */ + src_xy =3D (cfg->src_rect.y1 << 16) | cfg->src_rect.x1; + src_size =3D (drm_rect_height(&cfg->src_rect) << 16) | + drm_rect_width(&cfg->src_rect); + dst_xy =3D (cfg->dst_rect.y1 << 16) | cfg->dst_rect.x1; + dst_size =3D (drm_rect_height(&cfg->dst_rect) << 16) | + drm_rect_width(&cfg->dst_rect); + + /* rectangle register programming */ + DPU_REG_WRITE(c, src_size_off, src_size); + DPU_REG_WRITE(c, src_xy_off, src_xy); + DPU_REG_WRITE(c, out_size_off, dst_size); + DPU_REG_WRITE(c, out_xy_off, dst_xy); +} + +void dpu_hw_setup_solidfill_impl(struct dpu_sw_pipe *pipe, + u32 color, struct dpu_hw_sspp *ctx, u32 const_clr_off); + +void dpu_hw_sspp_setup_qos_ctrl_impl(struct dpu_hw_sspp *ctx, + bool danger_safe_en, u32 ctrl_off); + #endif /*_DPU_HW_SSPP_H */ =20 --=20 2.34.1