From nobody Sun Feb 8 04:23:32 2026 Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 012FE27E04C for ; Thu, 15 Jan 2026 04:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768450316; cv=none; b=ei1wpR2+CAJfY0YCGynujJDm2mItJ58AR43vIfqWJuqw8XLSDRVn9J8WlfoQaGMJ5MallkWC7xjnTkkWfKo21YZXWHC1qPTepEVl/b2x8p7V6ijIMVAXtO8+W7hOvVqcL8kL3/3RbFGKeJ2udojpI0Ob5ebUWXJlIjBuRKnvZEI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768450316; c=relaxed/simple; bh=eH05iNFww19kcMZ0contcs3Ur4Aq0Uioewvs0Ol8TEA=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=t4zFxxgMb/cAhizczu0eziEYJZrQnToI//TCQZNu9wV3GWQNO+QTy6T+Cti9XKTHFOWWrQi5MAXgbi5DOxmuG93HKAsUdauQ1E+IW2xZXdUhukqaoBR/B8PAASFb2pXbTpWrKIn7/5kQ+CET86UpdCE2sKjleul3xzUl44LOca4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NjBBA6I8; arc=none smtp.client-ip=209.85.215.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NjBBA6I8" Received: by mail-pg1-f196.google.com with SMTP id 41be03b00d2f7-bc09b3d3afeso212140a12.0 for ; Wed, 14 Jan 2026 20:11:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768450314; x=1769055114; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=bInY6G+fRPU4N4S6clAbFXdycHArb+K858x2QHnaCgU=; b=NjBBA6I8zTjR+COaFg4APBqhFb9KxKXmTsf+mmmk029wc0laJtRNRxybaRYW2oeJwU EEDTvo/ZzKUloYLMqwLXvGpFDGMPor8ovCmtxWVppkMsEoEsQ/9N+qRnm09k6g1paFko XLz4u+PcEav30JWiCrBB9azJm2ktXvDL67a4BP8IyU7+aRfogXPVzZi1pGQ4sK8jk1lI iu//9GagC0pDm+FUr4gErOWug8JaQYZAD39sNL9jh2ANJH/7KB8ynKj8mBRyXkCCEVkJ eQI4aYYNPuYo2v/DIwalqjG+zEw8GPBu+m9lhQDECfmGqDhIWZOM/dd7U0EpDYdXP6nc yLoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768450314; x=1769055114; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=bInY6G+fRPU4N4S6clAbFXdycHArb+K858x2QHnaCgU=; b=dUcgqy98AKhPpIPxHNWAhmjKFw8weoF9hhxoChB5cszPJhJG5FELA1tniSVbm5rqt5 PyicAMThvT2sQrrX6x0U41Tf31rTKjxbnov0db7+YqjYlnYHTCD3V59RVq0AOFQJkRXm KwQMIW7qTzUpKQyuDSPOy82CCMKsRv5i2GimIn3nCIuZ4buFyZSd7T8McPivp0FWeS0u pYNlCugU5/5fPNY1ZRnGMVX8e+ODGCn4kNZOpwHFv4dMbSly2GCfx6Kv4tEUdq7/LRfm EKdHyCxQ74vWXi7eekfCiEyqNHSN6I8X+sh2/mvOdC8OZwWj2q9oQ+kfNezDqcra94Bg jt6A== X-Gm-Message-State: AOJu0YwqEiRnB4C3F/7uDER8fgGYZ0T/t/WggnVmNf/MZ3ITwUArw61N U5g3NNOMaavs99UnLYGY7zcI461ENL8sRM2/PQGq7JawqyLNVgW7o8tnzylEbMoQ910= X-Gm-Gg: AY/fxX4tpJSUSu4hTamniVAnLbMN/Uo2twd/XaqoxaTaNH8rQ9yihqplc+CDmELSCpv Bl+YlBfmftiH9Umiai5At7HayflRlxloPECz029vRsjCrAxHFx+5VNfjJlKsJmrQzdXUNOJ605P oHAHKybwHz2EyhGtbHPcPFG6/jOnKWrd2jk9eQBvlZy8Tqj7LCFFfpDyChebn7ju6OozclxdfIj 6j1+s3hkZGwo30vsdms6YpYqO0EB+3hgVXzURDxM6pqjqz+eWP5YA3aFVY95P/o1d/qje/oyg7M jbIPOElQATBi1gKVXCXYBx2ZGgLqxf8QJh5z39Ecj9AbjXg4X7wwCwG0URxAY+W2S4i5Uvwg0XU wFvg8qI/oc4ttgGBp0z4PUxeB7Yc/GNmjKA2sV0Q4IlRMQsWlSm7AESJMuqPzV8PF+asqXVj41e pUYVfrmSYTLXBQ6jUSdhfYcddXJ6sJc9oga8/ZCP2ygp1z5lJV X-Received: by 2002:a17:90b:3806:b0:34c:635f:f855 with SMTP id 98e67ed59e1d1-351090bde3cmr5297541a91.7.1768450313919; Wed, 14 Jan 2026 20:11:53 -0800 (PST) Received: from fric.. ([210.73.43.101]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-351099e2fbesm1626399a91.3.2026.01.14.20.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 20:11:53 -0800 (PST) From: Jiakai Xu X-Google-Original-From: Jiakai Xu To: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org Cc: Jonathan Corbet , Paolo Bonzini , Jiakai Xu Subject: [PATCH] RISC-V: KVM: Document scounteren and senvcfg in CSRs Date: Thu, 15 Jan 2026 04:11:46 +0000 Message-Id: <20260115041146.807967-1-jiakaiPeanut@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jiakai Xu Extend the documentation of guest supervisor-mode CSRs to include scounteren and senvcfg. These registers are part of the RISC-V supervisor CSR set but were previously missing from the documented encoding table. Also adjust the table formatting to keep column alignment consistent. Signed-off-by: Jiakai Xu --- Documentation/virt/kvm/api.rst | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 01a3abef8abb..6dab20637c7b 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -2837,19 +2837,21 @@ of a Guest VCPU and it has the following id bit pat= terns:: =20 Following are the RISC-V csr registers: =20 -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - Encoding Register Description -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - 0x80x0 0000 0300 0000 sstatus Supervisor status - 0x80x0 0000 0300 0001 sie Supervisor interrupt enable - 0x80x0 0000 0300 0002 stvec Supervisor trap vector base - 0x80x0 0000 0300 0003 sscratch Supervisor scratch register - 0x80x0 0000 0300 0004 sepc Supervisor exception program counter - 0x80x0 0000 0300 0005 scause Supervisor trap cause - 0x80x0 0000 0300 0006 stval Supervisor bad address or instruction - 0x80x0 0000 0300 0007 sip Supervisor interrupt pending - 0x80x0 0000 0300 0008 satp Supervisor address translation and prote= ction -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + Encoding Register Description +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + 0x80x0 0000 0300 0000 sstatus Supervisor status + 0x80x0 0000 0300 0001 sie Supervisor interrupt enable + 0x80x0 0000 0300 0002 stvec Supervisor trap vector base + 0x80x0 0000 0300 0003 sscratch Supervisor scratch register + 0x80x0 0000 0300 0004 sepc Supervisor exception program counter + 0x80x0 0000 0300 0005 scause Supervisor trap cause + 0x80x0 0000 0300 0006 stval Supervisor bad address or instruction + 0x80x0 0000 0300 0007 sip Supervisor interrupt pending + 0x80x0 0000 0300 0008 satp Supervisor address translation and prot= ection + 0x80x0 0000 0300 0009 scounteren Supervisor counter-enable + 0x80x0 0000 0300 000a senvcfg Supervisor environment configuration +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =20 RISC-V timer registers represent the timer state of a Guest VCPU and it has the following id bit patterns:: --=20 2.34.1