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Wed, 14 Jan 2026 22:53:04 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:45 +0800 Subject: [PATCH v5 6/7] riscv: dts: spacemit: add initial support for K3 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com> References: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> In-Reply-To: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen , Thomas Gleixner , Thomas Gleixner Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. Add nodes of uarts, timer and interrupt-controllers. Also add M-mode APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware topology and ready for potential firmware usage. Signed-off-by: Guodong Xu --- v5: Update the copyright year to 2026. Set M-mode maplic and mimsic status to "reserved". Update the commit message per Yixun's suggestion. In maplic node, use riscv,delegation to match kernel binding. OpenSBI accepts both delegate and delegation, but the binding documents only riscv,delegation. v4: Fix missing blank space after commas in compatible string. Add m-mode imsic and aplic node. Reorder properties in simsic, saplic, mimsic, and maplic nodes to match DTS coding style. v3: Remove "supm" from the riscv,isa-extensions list. v2: Remove aliases from k3.dtsi, they should be in board DTS. Updated riscv,isa-extensions with new extensions from the extensions.ya= ml. --- arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 590 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spa= cemit/k3.dtsi new file mode 100644 index 000000000000..53425badfea9 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu + */ + +#include + +/dts-v1/; + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SpacemiT K3"; + compatible =3D "spacemit,k3"; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <24000000>; + + cpu_0: cpu@0 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_1: cpu@1 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_2: cpu@2 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_3: cpu@3 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_4: cpu@4 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <4>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_5: cpu@5 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <5>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_6: cpu@6 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <6>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_7: cpu@7 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <7>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <4194304>; + cache-sets =3D <4096>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <4194304>; + cache-sets =3D <4096>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_0>; + }; + core1 { + cpu =3D <&cpu_1>; + }; + core2 { + cpu =3D <&cpu_2>; + }; + core3 { + cpu =3D <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu_4>; + }; + core1 { + cpu =3D <&cpu_5>; + }; + core2 { + cpu =3D <&cpu_6>; + }; + core3 { + cpu =3D <&cpu_7>; + }; + }; + }; + }; + + soc: soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&saplic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart2: serial@d4017100 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017100 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart3: serial@d4017200 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017200 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart4: serial@d4017300 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017300 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart5: serial@d4017400 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017400 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart6: serial@d4017500 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017500 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart7: serial@d4017600 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017600 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart8: serial@d4017700 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017700 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart9: serial@d4017800 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017800 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart10: serial@d401f000 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd401f000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <281 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + simsic: interrupt-controller@e0400000 { + compatible =3D "spacemit,k3-imsics", "riscv,imsics"; + reg =3D <0x0 0xe0400000 0x0 0x200000>; + #interrupt-cells =3D <0>; + #msi-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>, + <&cpu6_intc 9>, <&cpu7_intc 9>; + msi-controller; + riscv,guest-index-bits =3D <6>; + riscv,hart-index-bits =3D <4>; + riscv,num-guest-ids =3D <511>; + riscv,num-ids =3D <511>; + }; + + saplic: interrupt-controller@e0804000 { + compatible =3D "spacemit,k3-aplic", "riscv,aplic"; + reg =3D <0x0 0xe0804000 0x0 0x4000>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&simsic>; + riscv,num-sources =3D <512>; + }; + + clint: timer@e081c000 { + compatible =3D "spacemit,k3-clint", "sifive,clint0"; + reg =3D <0x0 0xe081c000 0x0 0x4000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + mimsic: interrupt-controller@f1000000 { + compatible =3D "spacemit,k3-imsics", "riscv,imsics"; + reg =3D <0x0 0xf1000000 0x0 0x10000>; + #interrupt-cells =3D <0>; + #msi-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu6_intc 11>, <&cpu7_intc 11>; + msi-controller; + riscv,guest-index-bits =3D <6>; + riscv,hart-index-bits =3D <4>; + riscv,num-guest-ids =3D <511>; + riscv,num-ids =3D <511>; + + status =3D "reserved"; + }; + + maplic: interrupt-controller@f1800000 { + compatible =3D "spacemit,k3-aplic", "riscv,aplic"; + reg =3D <0x0 0xf1800000 0x0 0x4000>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&mimsic>; + riscv,children =3D <&saplic>; + riscv,delegation =3D <&saplic 1 512>; + riscv,num-sources =3D <512>; + + status =3D "reserved"; + }; + }; +}; --=20 2.43.0