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Wed, 14 Jan 2026 22:52:12 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:40 +0800 Subject: [PATCH v5 1/7] dt-bindings: riscv: add SpacemiT X100 CPU compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com> References: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> In-Reply-To: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen , Thomas Gleixner , Thomas Gleixner Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Krzysztof Kozlowski , Heinrich Schuchardt X-Mailer: b4 0.14.3 Add compatible string for the SpacemiT X100 core. [1] The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 supports the RISC-V vector and hypervisor extensions and all mandatory extersions as required by the RVA23U64 and RVA23S64 profiles, per the definition in 'RVA23 Profile, Version 1.0'. [2] From a microarchieture viewpoint, the X100 features a 4-issue out-of-order pipeline. X100 is used in SpacemiT K3 SoC. Acked-by: Paul Walmsley Acked-by: Krzysztof Kozlowski Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-pr= ofile.pdf [2] Reviewed-by: Yixun Lan Reviewed-by: Heinrich Schuchardt Signed-off-by: Guodong Xu --- v5: Added Acked-by from Paul. v4: No change. v3: Added Acked-by from Krzysztof. v2: Fixed alphanumeric sorting of compatible strings, put x100 before x60, as per Krzysztof's feedback. Added reviewed-by from Yixun and Heinrich. Updated the commit message to provide more information about X100. --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index d733c0bd534f..5feeb2203050 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -61,6 +61,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x100 - spacemit,x60 - thead,c906 - thead,c908 --=20 2.43.0 From nobody Sun Feb 8 06:04:25 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D66373C38 for ; Thu, 15 Jan 2026 06:52:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; 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Wed, 14 Jan 2026 22:52:21 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e7a3c6fdsm235081015ad.15.2026.01.14.22.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 22:52:21 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:41 +0800 Subject: [PATCH v5 2/7] dt-bindings: timer: add SpacemiT K3 CLINT Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-k3-basic-dt-v5-2-6990ac9f4308@riscstar.com> References: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> In-Reply-To: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen , Thomas Gleixner , Thomas Gleixner Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Conor Dooley X-Mailer: b4 0.14.3 Add compatible string for SpacemiT K3 CLINT. Acked-by: Conor Dooley Signed-off-by: Guodong Xu --- v5: No change. v4: No change. v3: No change. v2: Add Conor's Acked-by. --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index 0d3b8dc362ba..3bab40500df9 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - eswin,eic7700-clint # ESWIN EIC7700 - sifive,fu540-c000-clint # SiFive FU540 - spacemit,k1-clint # SpacemiT K1 + - spacemit,k3-clint # SpacemiT K3 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 --=20 2.43.0 From nobody Sun Feb 8 06:04:25 2026 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 504F12F3622 for ; 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Acked-by: Conor Dooley Signed-off-by: Guodong Xu --- v5: No change. v4: No change. v3: No change. v2: Add Conor's Acked-by. --- Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml | = 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,a= plic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,ap= lic.yaml index bef00521d5da..0718071444d2 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.ya= ml @@ -28,6 +28,7 @@ properties: items: - enum: - qemu,aplic + - spacemit,k3-aplic - const: riscv,aplic =20 reg: --=20 2.43.0 From nobody Sun Feb 8 06:04:25 2026 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D16E30C347 for ; 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Acked-by: Krzysztof Kozlowski Signed-off-by: Guodong Xu --- v5: No change. v4: No change. v3: Add Acked-by from Krzysztof. v2: Fix the order to keep things alphabetically. --- Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,i= msics.yaml index c23b5c09fdb9..feec122bddde 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.y= aml @@ -48,6 +48,7 @@ properties: items: - enum: - qemu,imsics + - spacemit,k3-imsics - const: riscv,imsics =20 reg: --=20 2.43.0 From nobody Sun Feb 8 06:04:25 2026 Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B84D030DD1F for ; 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Wed, 14 Jan 2026 22:52:53 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e7a3c6fdsm235081015ad.15.2026.01.14.22.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 22:52:53 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:44 +0800 Subject: [PATCH v5 5/7] dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com> References: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> In-Reply-To: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen , Thomas Gleixner , Thomas Gleixner Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu , Conor Dooley X-Mailer: b4 0.14.3 Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX which is a 2.5-inch single-board computer. Acked-by: Conor Dooley Reviewed-by: Yixun Lan Signed-off-by: Guodong Xu --- v5: Add Reviewed-by from Yixun. Add Acked-by from Conor. v4: Adjust maintainers list in alphabetic order. Declare spacemit,k3-pico-itx as an enum, which can save future code change when adding new boards. v3: No change. v2: Use one-blank-space between name and email address. --- Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Docume= ntation/devicetree/bindings/riscv/spacemit.yaml index 9c49482002f7..b958b94a924d 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: SpacemiT SoC-based boards =20 maintainers: + - Guodong Xu - Yangyu Chen - Yixun Lan =20 @@ -26,6 +27,10 @@ properties: - xunlong,orangepi-r2s - xunlong,orangepi-rv2 - const: spacemit,k1 + - items: + - enum: + - spacemit,k3-pico-itx + - const: spacemit,k3 =20 additionalProperties: true =20 --=20 2.43.0 From nobody Sun Feb 8 06:04:25 2026 Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1BA630E0C0 for ; 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Wed, 14 Jan 2026 22:53:04 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e7a3c6fdsm235081015ad.15.2026.01.14.22.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 22:53:04 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:45 +0800 Subject: [PATCH v5 6/7] riscv: dts: spacemit: add initial support for K3 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-k3-basic-dt-v5-6-6990ac9f4308@riscstar.com> References: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> In-Reply-To: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen , Thomas Gleixner , Thomas Gleixner Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. Add nodes of uarts, timer and interrupt-controllers. Also add M-mode APLIC (maplic) and IMSIC (mimsic) nodes to represent the hardware topology and ready for potential firmware usage. Signed-off-by: Guodong Xu --- v5: Update the copyright year to 2026. Set M-mode maplic and mimsic status to "reserved". Update the commit message per Yixun's suggestion. In maplic node, use riscv,delegation to match kernel binding. OpenSBI accepts both delegate and delegation, but the binding documents only riscv,delegation. v4: Fix missing blank space after commas in compatible string. Add m-mode imsic and aplic node. Reorder properties in simsic, saplic, mimsic, and maplic nodes to match DTS coding style. v3: Remove "supm" from the riscv,isa-extensions list. v2: Remove aliases from k3.dtsi, they should be in board DTS. Updated riscv,isa-extensions with new extensions from the extensions.ya= ml. --- arch/riscv/boot/dts/spacemit/k3.dtsi | 590 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 590 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spa= cemit/k3.dtsi new file mode 100644 index 000000000000..53425badfea9 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu + */ + +#include + +/dts-v1/; + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + model =3D "SpacemiT K3"; + compatible =3D "spacemit,k3"; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <24000000>; + + cpu_0: cpu@0 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_1: cpu@1 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_2: cpu@2 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_3: cpu@3 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_4: cpu@4 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <4>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_5: cpu@5 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <5>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_6: cpu@6 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <6>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu_7: cpu@7 { + compatible =3D "spacemit,x100", "riscv"; + device_type =3D "cpu"; + reg =3D <7>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "h", + "sha", "shcounterenw", "shgatpa", "shtvala", + "shvsatpa", "shvstvala", "shvstvecd", "smaia", + "smstateen", "ssaia", "ssccptr", "sscofpmf", + "sscounterenw", "ssnpm", "ssstateen", "sstc", + "sstvala", "sstvecd", "ssu64xl", "svade", + "svinval", "svnapot", "svpbmt", "za64rs", + "zawrs", "zba", "zbb", "zbc", "zbs", "zca", + "zcb", "zcd", "zcmop", "zfa", "zfbfmin", + "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", + "ziccamoa", "ziccif", "zicclsm", "zicntr", + "zicond", "zicsr", "zifencei", "zihintntl", + "zihintpause", "zihpm", "zimop", "zkt", "zvbb", + "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", + "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", + "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", + "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; + riscv,cbom-block-size =3D <64>; + riscv,cbop-block-size =3D <64>; + riscv,cboz-block-size =3D <64>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <256>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <256>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + l2_cache0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <4194304>; + cache-sets =3D <4096>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <4194304>; + cache-sets =3D <4096>; + cache-unified; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu_0>; + }; + core1 { + cpu =3D <&cpu_1>; + }; + core2 { + cpu =3D <&cpu_2>; + }; + core3 { + cpu =3D <&cpu_3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu_4>; + }; + core1 { + cpu =3D <&cpu_5>; + }; + core2 { + cpu =3D <&cpu_6>; + }; + core3 { + cpu =3D <&cpu_7>; + }; + }; + }; + }; + + soc: soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&saplic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + ranges; + + uart0: serial@d4017000 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <42 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart2: serial@d4017100 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017100 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart3: serial@d4017200 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017200 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart4: serial@d4017300 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017300 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart5: serial@d4017400 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017400 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart6: serial@d4017500 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017500 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart7: serial@d4017600 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017600 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart8: serial@d4017700 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017700 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <50 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart9: serial@d4017800 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd4017800 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <51 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + uart10: serial@d401f000 { + compatible =3D "spacemit,k3-uart", "intel,xscale-uart"; + reg =3D <0x0 0xd401f000 0x0 0x100>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clock-frequency =3D <14700000>; + interrupts =3D <281 IRQ_TYPE_LEVEL_HIGH>; + + status =3D "disabled"; + }; + + simsic: interrupt-controller@e0400000 { + compatible =3D "spacemit,k3-imsics", "riscv,imsics"; + reg =3D <0x0 0xe0400000 0x0 0x200000>; + #interrupt-cells =3D <0>; + #msi-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>, + <&cpu6_intc 9>, <&cpu7_intc 9>; + msi-controller; + riscv,guest-index-bits =3D <6>; + riscv,hart-index-bits =3D <4>; + riscv,num-guest-ids =3D <511>; + riscv,num-ids =3D <511>; + }; + + saplic: interrupt-controller@e0804000 { + compatible =3D "spacemit,k3-aplic", "riscv,aplic"; + reg =3D <0x0 0xe0804000 0x0 0x4000>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&simsic>; + riscv,num-sources =3D <512>; + }; + + clint: timer@e081c000 { + compatible =3D "spacemit,k3-clint", "sifive,clint0"; + reg =3D <0x0 0xe081c000 0x0 0x4000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>, + <&cpu6_intc 3>, <&cpu6_intc 7>, + <&cpu7_intc 3>, <&cpu7_intc 7>; + }; + + mimsic: interrupt-controller@f1000000 { + compatible =3D "spacemit,k3-imsics", "riscv,imsics"; + reg =3D <0x0 0xf1000000 0x0 0x10000>; + #interrupt-cells =3D <0>; + #msi-cells =3D <0>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu6_intc 11>, <&cpu7_intc 11>; + msi-controller; + riscv,guest-index-bits =3D <6>; + riscv,hart-index-bits =3D <4>; + riscv,num-guest-ids =3D <511>; + riscv,num-ids =3D <511>; + + status =3D "reserved"; + }; + + maplic: interrupt-controller@f1800000 { + compatible =3D "spacemit,k3-aplic", "riscv,aplic"; + reg =3D <0x0 0xf1800000 0x0 0x4000>; + #interrupt-cells =3D <2>; + interrupt-controller; + msi-parent =3D <&mimsic>; + riscv,children =3D <&saplic>; + riscv,delegation =3D <&saplic 1 512>; + riscv,num-sources =3D <512>; + + status =3D "reserved"; + }; + }; +}; --=20 2.43.0 From nobody Sun Feb 8 06:04:25 2026 Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D3892FE56A for ; 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Wed, 14 Jan 2026 22:53:14 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e7a3c6fdsm235081015ad.15.2026.01.14.22.53.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 22:53:14 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 14:51:46 +0800 Subject: [PATCH v5 7/7] riscv: dts: spacemit: add K3 Pico-ITX board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-k3-basic-dt-v5-7-6990ac9f4308@riscstar.com> References: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> In-Reply-To: <20260115-k3-basic-dt-v5-0-6990ac9f4308@riscstar.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Samuel Holland , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen , Thomas Gleixner , Thomas Gleixner Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Anup Patel , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Guodong Xu X-Mailer: b4 0.14.3 K3 Pico-ITX is a 2.5-inch single-board computer equipted with a SpacemiT K3 SoC. This minimal device tree enables booting into a serial console with UART output. Signed-off-by: Guodong Xu --- v5: Update the commit message subject per Yixun's suggestion. Remove the unused aliases. Update the copyright year to 2026. v4: No change. v3: No change. v2: Add aliases node in this board DT. Update the memory node to reflect the hardware truth. Address starts at 0x100000000 (4G) boundary. --- arch/riscv/boot/dts/spacemit/Makefile | 1 + arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 29 ++++++++++++++++++++++++= ++++ 2 files changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/sp= acemit/Makefile index 95889e7269d1..7e2b87702571 100644 --- a/arch/riscv/boot/dts/spacemit/Makefile +++ b/arch/riscv/boot/dts/spacemit/Makefile @@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-milkv-jupiter.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-musepi-pro.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-orangepi-r2s.dtb dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k1-orangepi-rv2.dtb +dtb-$(CONFIG_ARCH_SPACEMIT) +=3D k3-pico-itx.dtb diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot= /dts/spacemit/k3-pico-itx.dts new file mode 100644 index 000000000000..b691304d4b74 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd + * Copyright (c) 2026 Guodong Xu + */ + +#include "k3.dtsi" + +/ { + model =3D "SpacemiT K3 Pico-ITX"; + compatible =3D "spacemit,k3-pico-itx", "spacemit,k3"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0"; + }; + + memory@100000000 { + device_type =3D "memory"; + reg =3D <0x1 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.43.0