From nobody Tue Feb 10 16:22:05 2026 Received: from mail-yw1-f175.google.com (mail-yw1-f175.google.com [209.85.128.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC838331A7B for ; Thu, 15 Jan 2026 23:42:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768520582; cv=none; b=hgClFgDl23UNb3KCGUbw6oAKMRjYcWBTy4jtDp7HO7feWhRrZt+9e00n/qqpHCSAaV6AWZ7sANjefJTXDs3sFzRVif40mLqUlQR6wZFyUbbM1TtRz6CiryJUEvdRYxU7E0dkfJyeOHced7QfgW11VbNHUrYJpnMi2FlUaVYnM3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768520582; c=relaxed/simple; bh=qcaaZANCOEyqZ0KFVkNT48fIf3U6ZGNHU51PyrXz1GA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VpFJktBhKnWB0gEfGp4Db9tmcpNOSAXpq/MnyuV45PCTXNkv6TolqJmr+kHz5zZz6UeFWUwbYE4VChwM5fK2WviHVcCS4awNgpa1iqU7+xgde/WIG9Oas/Fz8nORreNJGoEnzwKL8zIabXCyhiW9dnpE1PhmPs6lTgKKezxSDZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=oss.tenstorrent.com; spf=pass smtp.mailfrom=tenstorrent.com; dkim=pass (2048-bit key) header.d=tenstorrent.com header.i=@tenstorrent.com header.b=PiqemR/Z; arc=none smtp.client-ip=209.85.128.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=oss.tenstorrent.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tenstorrent.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tenstorrent.com header.i=@tenstorrent.com header.b="PiqemR/Z" Received: by mail-yw1-f175.google.com with SMTP id 00721157ae682-79275e61c2cso15934757b3.3 for ; Thu, 15 Jan 2026 15:42:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tenstorrent.com; s=google; t=1768520572; x=1769125372; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YuXosatL7jUspS52kKMFA09e6GoDFcrqO+bX2qZbTEM=; b=PiqemR/Z3CQgL9AoZBmnoOLSN8JoNuKLheviRkzkPdslJMJoUZVu09XQtUleD5MtJB 6d9Rv+k1pd6i3xO58KhZMEhVeTG9cRqCfE8iFc/B6RSLWgRZNmtaaB6eRJYQM+gZXcNr OpswYjgJkHSZgStB+2qptpDqpk3Ts+syBVfKDfDDLALWFHT7O7+fYcoeMXxAFQvhjq1F YEFRvycHJV2JX+UxHMwCLjm3eYRW3vAq3NHPT/9BAexW9JcZPYv39hcr1HWAL5eUS3KR aBzy5zAxKFrjs3fPa0/M7Yg6u/gH5A7UT4p8hnGbtvWY7s/GogwHcditiFiZOysxr/Hl Gufg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768520572; x=1769125372; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YuXosatL7jUspS52kKMFA09e6GoDFcrqO+bX2qZbTEM=; b=wdlONpCi8vqavc+ozj0k20dOT+maeiPXS0MCCfLvck9TE7as9jA5pCCwzcTNt3NJoM XOgYBnevQiGO2tKi99KAsvIq2vtnL3s2fjE85VcdCuMui+t54CrDDkB0IoF3//OTWWpU V1rUXz62jekVgGOt2ku8PrJ6hlsbZ0AmXieDwrgebw70S8kb1u0EdfKPWBxCBJ96IgxT mMIOsbme7RUf9JSoun0fgjtTSbS0gP6rKF7yS2lh/ZEhiT8K6AeAG+LU7rAi+VbUg4qw LPcNOJRyxVFuDHHWFMtahX7SA8SeohbH4jqjzNRUWYxWEAHmeco48iU5fuB2HAcr0zts LTqA== X-Forwarded-Encrypted: i=1; AJvYcCU1a5AeoNcXwRX95IIlxMnxInFaLxoyEi1G66aqRWoqy9KpLFMAtn7gv6QTDbCKZqaL1s/zVCKjQSvJHdg=@vger.kernel.org X-Gm-Message-State: AOJu0YxlYBEhOPu1XHp4bD3OvBCfjd7KC9ROu5Ec10xMDFYUzy/mHIpV OY6wv/FYhc/tgcI0OfApzFp+EX/HJeOhTeFMAq7gnPM+btNbCpr239vF7dOoXyqsghQ= X-Gm-Gg: AY/fxX66j3X6ppStqUZE/OvZ76aMduNL/Bux/maYoXdrKlnE+KvVfaCu+F+fR4YaVtb uobAR5LX3eKF/FJ6B8F1Y9IBsu0lxlJ+qczapI4nrhZL5P2lTQkxh2S0bfJyLUY1hOzjean4Xug 3x26+qoVf8QSFMj9Vcpsc2LFdg5rGQCX0tPr6cbP1eM/dO7NIy7Mx0X5hmL1L+B3SIR59E2m44v DdBnON/St82o7EQZbUo3t61Br8PBwd0sWr/7HofXxrJUcoUk9vjla2s31rxxWQkvC9YXWFPRs/c S00nPUxUD9lkVvkcQd5NWJ+VfpKJH+5N+40NxmSPhbDDnvYY6KLJxLs3yW6wN9M5tv2Si+YzipE uHsXuISrfjL/vljkPjeD3h2QQRFv1iSxJue1dK7Nw+o/KydHmaqHk9p2ge9aCmyy14B4Pe2Ng6s H0eH5gKE8Jho9BR6T8rhEi9ZqYBM9blWu/fdH9M9cpSwhA+pwLoJyvFxDRM8f7UbBdzLa9y4g= X-Received: by 2002:a05:690c:e3e9:b0:792:7374:7ff4 with SMTP id 00721157ae682-793c66ac5e1mr8413757b3.11.1768520571893; Thu, 15 Jan 2026 15:42:51 -0800 (PST) Received: from [192.168.5.15] ([68.95.197.245]) by smtp.gmail.com with ESMTPSA id 00721157ae682-793c66c72aesm3027117b3.11.2026.01.15.15.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Jan 2026 15:42:51 -0800 (PST) From: Anirudh Srinivasan Date: Thu, 15 Jan 2026 17:42:06 -0600 Subject: [PATCH 7/8] reset: tenstorrent: Add reset controller for Atlantis Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-atlantis-clocks-v1-7-7356e671f28b@oss.tenstorrent.com> References: <20260115-atlantis-clocks-v1-0-7356e671f28b@oss.tenstorrent.com> In-Reply-To: <20260115-atlantis-clocks-v1-0-7356e671f28b@oss.tenstorrent.com> To: Drew Fustini , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Anirudh Srinivasan , Philipp Zabel Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, joel@jms.id.au, fustini@kernel.org, mpe@kernel.org, mpe@oss.tenstorrent.com, npiggin@oss.tenstorrent.com, agross@kernel.org, agross@oss.tenstorrent.com X-Mailer: b4 0.14.3 Implement reset controller as an auxiliary device of the clock controller, sharing the same regmap interface. This version of the driver covers resets from the RCPU syscon. Signed-off-by: Anirudh Srinivasan --- MAINTAINERS | 1 + drivers/reset/Kconfig | 11 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-tenstorrent-atlantis.c | 164 +++++++++++++++++++++++++= ++++ 4 files changed, 177 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 93d941d2886b..31c3e5bcb32d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22538,6 +22538,7 @@ F: Documentation/devicetree/bindings/riscv/tenstorr= ent.yaml F: Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-= syscon.yaml F: arch/riscv/boot/dts/tenstorrent/ F: drivers/clk/tenstorrent/ +F: drivers/reset/reset-tenstorrent-atlantis.c F: include/dt-bindings/clock/tenstorrent,atlantis-syscon.h F: include/soc/tenstorrent/ =20 diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6e5d6deffa7d..cade77717492 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -324,6 +324,17 @@ config RESET_SUNXI help This enables the reset driver for Allwinner SoCs. =20 +config RESET_TENSTORRENT_ATLANTIS + tristate "Tenstorrent atlantis reset driver" + depends on ARCH_TENSTORRENT || COMPILE_TEST + select AUXILIARY_BUS + default ARCH_TENSTORRENT + help + This enables the driver for the reset controller + present in the Tenstorrent Atlantis SoC. + Enable this option to be able to use hardware + resets on Atalantis based systems. + config RESET_TH1520 tristate "T-HEAD TH1520 reset controller" depends on ARCH_THEAD || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 9c3e484dfd81..a31959da0a88 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o obj-$(CONFIG_RESET_SPACEMIT) +=3D reset-spacemit.o obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) +=3D reset-sunxi.o +obj-$(CONFIG_RESET_TENSTORRENT_ATLANTIS) +=3D reset-tenstorrent-atlantis.o obj-$(CONFIG_RESET_TH1520) +=3D reset-th1520.o obj-$(CONFIG_RESET_TI_SCI) +=3D reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) +=3D reset-ti-syscon.o diff --git a/drivers/reset/reset-tenstorrent-atlantis.c b/drivers/reset/res= et-tenstorrent-atlantis.c new file mode 100644 index 000000000000..b1e934a5b054 --- /dev/null +++ b/drivers/reset/reset-tenstorrent-atlantis.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026 Tenstorrent + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +struct atlantis_reset_data { + u8 bit; + u16 reg; + bool active_low; +}; + +struct atlantis_reset_controller_data { + const struct atlantis_reset_data *reset_data; + size_t count; +}; + +struct atlantis_reset_controller { + struct reset_controller_dev rcdev; + const struct atlantis_reset_controller_data *data; + struct regmap *regmap; +}; + +#define to_atlantis_reset_controller(_rcdev) \ + container_of((_rcdev), struct atlantis_reset_controller, rcdev) + +#define RESET_DATA(_reg, _bit, _active_low) \ + { \ + .bit =3D _bit, .reg =3D _reg, .active_low =3D _active_low, \ + } + +static const struct atlantis_reset_data atlantis_rcpu_resets[] =3D { + [RST_SMNDMA0] =3D RESET_DATA(RCPU_BLK_RST_REG, 0, true), + [RST_SMNDMA1] =3D RESET_DATA(RCPU_BLK_RST_REG, 1, true), + [RST_WDT0] =3D RESET_DATA(RCPU_BLK_RST_REG, 2, true), + [RST_WDT1] =3D RESET_DATA(RCPU_BLK_RST_REG, 3, true), + [RST_TMR] =3D RESET_DATA(RCPU_BLK_RST_REG, 4, true), + [RST_PVTC] =3D RESET_DATA(RCPU_BLK_RST_REG, 12, true), + [RST_PMU] =3D RESET_DATA(RCPU_BLK_RST_REG, 13, true), + [RST_MAILBOX] =3D RESET_DATA(RCPU_BLK_RST_REG, 14, true), + [RST_SPACC] =3D RESET_DATA(RCPU_BLK_RST_REG, 26, true), + [RST_OTP] =3D RESET_DATA(RCPU_BLK_RST_REG, 28, true), + [RST_TRNG] =3D RESET_DATA(RCPU_BLK_RST_REG, 29, true), + [RST_CRC] =3D RESET_DATA(RCPU_BLK_RST_REG, 30, true), + + [RST_QSPI] =3D RESET_DATA(LSIO_BLK_RST_REG, 0, true), + [RST_I2C0] =3D RESET_DATA(LSIO_BLK_RST_REG, 1, true), + [RST_I2C1] =3D RESET_DATA(LSIO_BLK_RST_REG, 2, true), + [RST_I2C2] =3D RESET_DATA(LSIO_BLK_RST_REG, 3, true), + [RST_I2C3] =3D RESET_DATA(LSIO_BLK_RST_REG, 4, true), + [RST_I2C4] =3D RESET_DATA(LSIO_BLK_RST_REG, 5, true), + [RST_UART0] =3D RESET_DATA(LSIO_BLK_RST_REG, 6, true), + [RST_UART1] =3D RESET_DATA(LSIO_BLK_RST_REG, 7, true), + [RST_UART2] =3D RESET_DATA(LSIO_BLK_RST_REG, 8, true), + [RST_UART3] =3D RESET_DATA(LSIO_BLK_RST_REG, 9, true), + [RST_UART4] =3D RESET_DATA(LSIO_BLK_RST_REG, 10, true), + [RST_SPI0] =3D RESET_DATA(LSIO_BLK_RST_REG, 11, true), + [RST_SPI1] =3D RESET_DATA(LSIO_BLK_RST_REG, 12, true), + [RST_SPI2] =3D RESET_DATA(LSIO_BLK_RST_REG, 13, true), + [RST_SPI3] =3D RESET_DATA(LSIO_BLK_RST_REG, 14, true), + [RST_GPIO] =3D RESET_DATA(LSIO_BLK_RST_REG, 15, true), + [RST_CAN0] =3D RESET_DATA(LSIO_BLK_RST_REG, 17, true), + [RST_CAN1] =3D RESET_DATA(LSIO_BLK_RST_REG, 18, true), + [RST_I2S0] =3D RESET_DATA(LSIO_BLK_RST_REG, 19, true), + [RST_I2S1] =3D RESET_DATA(LSIO_BLK_RST_REG, 20, true), + +}; + +static const struct atlantis_reset_controller_data atlantis_rcpu_reset_dat= a =3D { + .reset_data =3D atlantis_rcpu_resets, + .count =3D ARRAY_SIZE(atlantis_rcpu_resets), +}; + +static int atlantis_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + unsigned int val; + struct atlantis_reset_controller *rst =3D + to_atlantis_reset_controller(rcdev); + const struct atlantis_reset_data *data =3D &rst->data->reset_data[id]; + unsigned int mask =3D BIT(data->bit); + struct regmap *regmap =3D rst->regmap; + + if (data->active_low ^ assert) + val =3D mask; + else + val =3D ~mask; + + return regmap_update_bits(regmap, data->reg, mask, val); +} + +static int atlantis_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return atlantis_reset_update(rcdev, id, true); +} + +static int atlantis_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return atlantis_reset_update(rcdev, id, false); +} + +static const struct reset_control_ops atlantis_reset_control_ops =3D { + .assert =3D atlantis_reset_assert, + .deassert =3D atlantis_reset_deassert, +}; + +static int +atlantis_reset_controller_register(struct device *dev, + struct atlantis_reset_controller *controller) +{ + struct reset_controller_dev *rcdev =3D &controller->rcdev; + + rcdev->ops =3D &atlantis_reset_control_ops; + rcdev->owner =3D THIS_MODULE; + rcdev->of_node =3D dev->of_node; + rcdev->nr_resets =3D controller->data->count; + + return devm_reset_controller_register(dev, &controller->rcdev); +} +static int atlantis_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct atlantis_ccu_adev *rdev =3D to_atlantis_ccu_adev(adev); + struct atlantis_reset_controller *controller; + struct device *dev =3D &adev->dev; + + controller =3D devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); + if (!controller) + return -ENOMEM; + controller->data =3D + (const struct atlantis_reset_controller_data *)id->driver_data; + controller->regmap =3D rdev->regmap; + + return atlantis_reset_controller_register(dev, controller); +} + +static const struct auxiliary_device_id atlantis_reset_ids[] =3D { + { .name =3D "atlantis_ccu.rcpu-reset", + .driver_data =3D (kernel_ulong_t)&atlantis_rcpu_reset_data }, + {}, +}; +MODULE_DEVICE_TABLE(auxiliary, atlantis_reset_ids); + +static struct auxiliary_driver atlantis_reset_driver =3D { + .probe =3D atlantis_reset_probe, + .id_table =3D atlantis_reset_ids, +}; +module_auxiliary_driver(atlantis_reset_driver); + +MODULE_AUTHOR("Anirudh Srinivasan "); +MODULE_DESCRIPTION("Atlantis reset controller driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0