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Thu, 15 Jan 2026 15:42:45 -0800 (PST) From: Anirudh Srinivasan Date: Thu, 15 Jan 2026 17:42:01 -0600 Subject: [PATCH 2/8] soc: tenstorrent: Add header with Atlantis syscon register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-atlantis-clocks-v1-2-7356e671f28b@oss.tenstorrent.com> References: <20260115-atlantis-clocks-v1-0-7356e671f28b@oss.tenstorrent.com> In-Reply-To: <20260115-atlantis-clocks-v1-0-7356e671f28b@oss.tenstorrent.com> To: Drew Fustini , Joel Stanley , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Anirudh Srinivasan , Philipp Zabel Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, joel@jms.id.au, fustini@kernel.org, mpe@kernel.org, mpe@oss.tenstorrent.com, npiggin@oss.tenstorrent.com, agross@kernel.org, agross@oss.tenstorrent.com X-Mailer: b4 0.14.3 Document register offsets used for controlling clocks in Atlantis Signed-off-by: Anirudh Srinivasan --- MAINTAINERS | 1 + include/soc/tenstorrent/atlantis-syscon.h | 38 +++++++++++++++++++++++++++= ++++ 2 files changed, 39 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 19a98b1fa456..4a2017d647b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22538,6 +22538,7 @@ F: Documentation/devicetree/bindings/riscv/tenstorr= ent.yaml F: Documentation/devicetree/bindings/soc/tenstorrent/tenstorrent,atlantis-= syscon.yaml F: arch/riscv/boot/dts/tenstorrent/ F: include/dt-bindings/clock/tenstorrent,atlantis-syscon.h +F: include/soc/tenstorrent/ =20 RISC-V THEAD SoC SUPPORT M: Drew Fustini diff --git a/include/soc/tenstorrent/atlantis-syscon.h b/include/soc/tensto= rrent/atlantis-syscon.h new file mode 100644 index 000000000000..b15dabfb42b5 --- /dev/null +++ b/include/soc/tenstorrent/atlantis-syscon.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 Tenstorrent + */ +#ifndef __SOC_ATLANTIS_SYSCON_H__ +#define __SOC_ATLANTIS_SYSCON_H__ + +#include +#include + +/* RCPU Clock Register Offsets */ +#define RCPU_PLL_CFG_REG 0x0000 +#define RCPU_NOCC_PLL_CFG_REG 0x0004 +#define RCPU_NOCC_CLK_CFG_REG 0x0008 +#define RCPU_DIV_CFG_REG 0x000C +#define RCPU_BLK_CG_REG 0x0014 +#define LSIO_BLK_CG_REG 0x0018 +#define PLL_RCPU_EN_REG 0x11c +#define PLL_NOCC_EN_REG 0x120 +#define BUS_CG_REG 0x01FC + +/* PLL Bit Definitions */ +#define PLL_CFG_EN_BIT BIT(0) +#define PLL_CFG_BYPASS_BIT BIT(1) +#define PLL_CFG_REFDIV_MASK GENMASK(7, 2) +#define PLL_CFG_REFDIV_SHIFT 2 +#define PLL_CFG_POSTDIV1_MASK GENMASK(10, 8) +#define PLL_CFG_POSTDIV1_SHIFT 8 +#define PLL_CFG_POSTDIV2_MASK GENMASK(13, 11) +#define PLL_CFG_POSTDIV2_SHIFT 11 +#define PLL_CFG_FBDIV_MASK GENMASK(25, 14) +#define PLL_CFG_FBDIV_SHIFT 14 +#define PLL_CFG_LKDT_BIT BIT(30) +#define PLL_CFG_LOCK_BIT BIT(31) +#define PLL_LOCK_TIMEOUT_US 1000 +#define PLL_BYPASS_WAIT_US 500 + +#endif --=20 2.43.0