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Wed, 14 Jan 2026 15:19:22 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:58 +0800 Subject: [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-adding-b-dtsi-v2-2-254dd61cf947@riscstar.com> References: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> In-Reply-To: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Chen Wang , Inochi Amaoto , Yixun Lan , Conor Dooley Cc: Junhui Liu , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update dr1v90.dtsi to conform to this rule. Line balancing is performed to improve readability. Signed-off-by: Guodong Xu Reviewed-by: Junhui Liu --- v2: New patch, a split from the Patch 2 in v1. This patch is for Anlogic dr1v90. --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/= anlogic/dr1v90.dtsi index a5d0765ade32..9fe183f5f5c8 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -27,8 +27,9 @@ cpu@0 { mmu-type =3D "riscv,sv39"; reg =3D <0>; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zba", "zbb", "z= bc", - "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", + "zba", "zbb", "zbc", "zbkc", "zbs", + "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; =20 cpu0_intc: interrupt-controller { --=20 2.43.0