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Wed, 14 Jan 2026 15:19:16 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:57 +0800 Subject: [PATCH v2 1/4] Documentation: riscv: uabi: Clarify ISA spec version for canonical order Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-adding-b-dtsi-v2-1-254dd61cf947@riscstar.com> References: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> In-Reply-To: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Chen Wang , Inochi Amaoto , Yixun Lan , Conor Dooley Cc: Junhui Liu , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 Specify that chapter 27 refers to version 20191213 of the RISC-V ISA Unprivileged Architecture. The chapter numbering differs across specification versions - for example, in version 20250508, the ISA Extension Naming Conventions is chapter 36, not chapter 27. Historical versions of the RISC-V specification can be found via Link [1]. Acked-by: Paul Walmsley Link: https://riscv.org/specifications/ratified/ [1] Fixes: f07b2b3f9d47 ("Documentation: riscv: add a section about ISA string = ordering in /proc/cpuinfo") Signed-off-by: Guodong Xu --- v2: Add Acked-by from Paul. --- Documentation/arch/riscv/uabi.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/riscv/uabi.rst b/Documentation/arch/riscv/u= abi.rst index 243e40062e34..0c5299e00762 100644 --- a/Documentation/arch/riscv/uabi.rst +++ b/Documentation/arch/riscv/uabi.rst @@ -7,7 +7,9 @@ ISA string ordering in /proc/cpuinfo ------------------------------------ =20 The canonical order of ISA extension names in the ISA string is defined in -chapter 27 of the unprivileged specification. +Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA +(Document Version 20191213). + The specification uses vague wording, such as should, when it comes to ord= ering, so for our purposes the following rules apply: =20 --=20 2.43.0 From nobody Sun Feb 8 09:10:59 2026 Received: from mail-pl1-f171.google.com (mail-pl1-f171.google.com [209.85.214.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B547538B990 for ; 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Wed, 14 Jan 2026 15:19:22 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cb2d6csm238591755ad.64.2026.01.14.15.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 15:19:22 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:58 +0800 Subject: [PATCH v2 2/4] riscv: dts: anlogic: dr1v90: Add "b" ISA extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-adding-b-dtsi-v2-2-254dd61cf947@riscstar.com> References: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> In-Reply-To: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Chen Wang , Inochi Amaoto , Yixun Lan , Conor Dooley Cc: Junhui Liu , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update dr1v90.dtsi to conform to this rule. Line balancing is performed to improve readability. Signed-off-by: Guodong Xu Reviewed-by: Junhui Liu --- v2: New patch, a split from the Patch 2 in v1. This patch is for Anlogic dr1v90. --- arch/riscv/boot/dts/anlogic/dr1v90.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi b/arch/riscv/boot/dts/= anlogic/dr1v90.dtsi index a5d0765ade32..9fe183f5f5c8 100644 --- a/arch/riscv/boot/dts/anlogic/dr1v90.dtsi +++ b/arch/riscv/boot/dts/anlogic/dr1v90.dtsi @@ -27,8 +27,9 @@ cpu@0 { mmu-type =3D "riscv,sv39"; reg =3D <0>; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zba", "zbb", "z= bc", - "zbkc", "zbs", "zicntr", "zicsr", "zifencei", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", + "zba", "zbb", "zbc", "zbkc", "zbs", + "zicntr", "zicsr", "zifencei", "zihintpause", "zihpm"; =20 cpu0_intc: interrupt-controller { --=20 2.43.0 From nobody Sun Feb 8 09:10:59 2026 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 876ED38F24B for ; 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Wed, 14 Jan 2026 15:19:29 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cb2d6csm238591755ad.64.2026.01.14.15.19.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 15:19:29 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:59 +0800 Subject: [PATCH v2 3/4] riscv: dts: sophgo: sg2044: Add "b" ISA extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com> References: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> In-Reply-To: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Chen Wang , Inochi Amaoto , Yixun Lan , Conor Dooley Cc: Junhui Liu , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update sg2044-cpus.dtsi to conform to this rule. Signed-off-by: Guodong Xu Reviewed-by: Inochi Amaoto --- v2: New patch, a split from the Patch 2 in v1. This patch is for Sophgo sg2044. --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++++++----------= ---- 1 file changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/= dts/sophgo/sg2044-cpus.dtsi index 523799a1a8b8..3135409c2149 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -24,10 +24,10 @@ cpu0: cpu@0 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache0>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -60,10 +60,10 @@ cpu1: cpu@1 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache0>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -96,10 +96,10 @@ cpu2: cpu@2 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache0>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -132,10 +132,10 @@ cpu3: cpu@3 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache0>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -168,10 +168,10 @@ cpu4: cpu@4 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache1>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -204,10 +204,10 @@ cpu5: cpu@5 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache1>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -240,10 +240,10 @@ cpu6: cpu@6 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache1>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -276,10 +276,10 @@ cpu7: cpu@7 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache1>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -312,10 +312,10 @@ cpu8: cpu@8 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache2>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -348,10 +348,10 @@ cpu9: cpu@9 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache2>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -384,10 +384,10 @@ cpu10: cpu@10 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache2>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -420,10 +420,10 @@ cpu11: cpu@11 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache2>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -456,10 +456,10 @@ cpu12: cpu@12 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache3>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -492,10 +492,10 @@ cpu13: cpu@13 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache3>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -528,10 +528,10 @@ cpu14: cpu@14 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache3>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -564,10 +564,10 @@ cpu15: cpu@15 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache3>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -600,10 +600,10 @@ cpu16: cpu@16 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache4>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -636,10 +636,10 @@ cpu17: cpu@17 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache4>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -672,10 +672,10 @@ cpu18: cpu@18 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache4>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -708,10 +708,10 @@ cpu19: cpu@19 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache4>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -744,10 +744,10 @@ cpu20: cpu@20 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache5>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -780,10 +780,10 @@ cpu21: cpu@21 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache5>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -816,10 +816,10 @@ cpu22: cpu@22 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache5>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -852,10 +852,10 @@ cpu23: cpu@23 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache5>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -888,10 +888,10 @@ cpu24: cpu@24 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache6>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -924,10 +924,10 @@ cpu25: cpu@25 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache6>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -960,10 +960,10 @@ cpu26: cpu@26 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache6>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -996,10 +996,10 @@ cpu27: cpu@27 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache6>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1032,10 +1032,10 @@ cpu28: cpu@28 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache7>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1068,10 +1068,10 @@ cpu29: cpu@29 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache7>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1104,10 +1104,10 @@ cpu30: cpu@30 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache7>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1140,10 +1140,10 @@ cpu31: cpu@31 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache7>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1176,10 +1176,10 @@ cpu32: cpu@32 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache8>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1212,10 +1212,10 @@ cpu33: cpu@33 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache8>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1248,10 +1248,10 @@ cpu34: cpu@34 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache8>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1284,10 +1284,10 @@ cpu35: cpu@35 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache8>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1320,10 +1320,10 @@ cpu36: cpu@36 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache9>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1356,10 +1356,10 @@ cpu37: cpu@37 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache9>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1392,10 +1392,10 @@ cpu38: cpu@38 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache9>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1428,10 +1428,10 @@ cpu39: cpu@39 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache9>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1464,10 +1464,10 @@ cpu40: cpu@40 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache10>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1500,10 +1500,10 @@ cpu41: cpu@41 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache10>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1536,10 +1536,10 @@ cpu42: cpu@42 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache10>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1572,10 +1572,10 @@ cpu43: cpu@43 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache10>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1608,10 +1608,10 @@ cpu44: cpu@44 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache11>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1644,10 +1644,10 @@ cpu45: cpu@45 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache11>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1680,10 +1680,10 @@ cpu46: cpu@46 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache11>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1716,10 +1716,10 @@ cpu47: cpu@47 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache11>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1752,10 +1752,10 @@ cpu48: cpu@48 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache12>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1788,10 +1788,10 @@ cpu49: cpu@49 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache12>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1824,10 +1824,10 @@ cpu50: cpu@50 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache12>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1860,10 +1860,10 @@ cpu51: cpu@51 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache12>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1896,10 +1896,10 @@ cpu52: cpu@52 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache13>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1932,10 +1932,10 @@ cpu53: cpu@53 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache13>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1968,10 +1968,10 @@ cpu54: cpu@54 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache13>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2004,10 +2004,10 @@ cpu55: cpu@55 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache13>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2040,10 +2040,10 @@ cpu56: cpu@56 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache14>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2076,10 +2076,10 @@ cpu57: cpu@57 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache14>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2112,10 +2112,10 @@ cpu58: cpu@58 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache14>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2148,10 +2148,10 @@ cpu59: cpu@59 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache14>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2184,10 +2184,10 @@ cpu60: cpu@60 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache15>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2220,10 +2220,10 @@ cpu61: cpu@61 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache15>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2256,10 +2256,10 @@ cpu62: cpu@62 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache15>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2292,10 +2292,10 @@ cpu63: cpu@63 { device_type =3D "cpu"; mmu-type =3D "riscv,sv48"; next-level-cache =3D <&l2_cache15>; - riscv,isa =3D "rv64imafdcv"; + riscv,isa =3D "rv64imafdcbv"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", --=20 2.43.0 From nobody Sun Feb 8 09:10:59 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E8EB38E5E2 for ; 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Wed, 14 Jan 2026 15:19:36 -0800 (PST) Received: from [127.0.1.1] ([45.8.220.151]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cb2d6csm238591755ad.64.2026.01.14.15.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 15:19:36 -0800 (PST) From: Guodong Xu Date: Thu, 15 Jan 2026 07:19:00 +0800 Subject: [PATCH v2 4/4] riscv: dts: spacemit: k1: Add "b" ISA extension Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260115-adding-b-dtsi-v2-4-254dd61cf947@riscstar.com> References: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> In-Reply-To: <20260115-adding-b-dtsi-v2-0-254dd61cf947@riscstar.com> To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Chen Wang , Inochi Amaoto , Yixun Lan , Conor Dooley Cc: Junhui Liu , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, spacemit@lists.linux.dev, Guodong Xu X-Mailer: b4 0.14.3 "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update k1.dtsi to conform to this rule. Signed-off-by: Guodong Xu Reviewed-by: Yixun Lan --- v2: New patch, a split from the Patch 2 in v1. This patch is for Spacemit K1. --- arch/riscv/boot/dts/spacemit/k1.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 4c045da95d72..2917b315728f 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -54,9 +54,9 @@ cpu_0: cpu@0 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <0>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -84,9 +84,9 @@ cpu_1: cpu@1 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <1>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -114,9 +114,9 @@ cpu_2: cpu@2 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <2>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -144,9 +144,9 @@ cpu_3: cpu@3 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <3>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -174,9 +174,9 @@ cpu_4: cpu@4 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <4>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -204,9 +204,9 @@ cpu_5: cpu@5 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <5>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -234,9 +234,9 @@ cpu_6: cpu@6 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <6>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", @@ -264,9 +264,9 @@ cpu_7: cpu@7 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <7>; - riscv,isa =3D "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zif= encei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svi= nval_svnapot_svpbmt"; + riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; - riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "v", "zicbom", + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihintpause", "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", --=20 2.43.0