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[217.128.226.200]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47f941a670dsm3098195e9.5.2026.01.14.14.12.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 14 Jan 2026 14:12:18 -0800 (PST) From: "benoit.masson" To: Jean Delvare , Guenter Roeck Cc: linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, "benoit.masson" Subject: [PATCH v4 5/5] hwmon: it87: add IT8613E configuration Date: Wed, 14 Jan 2026 23:12:10 +0100 Message-ID: <20260114221210.98071-6-yahoo@perenite.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260114221210.98071-1-yahoo@perenite.com> References: <20260114221210.98071-1-yahoo@perenite.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add IT8613E feature flags, resource counts, ADC scaling, and GPIO quirk handling, then document the chip in the hwmon guide. Signed-off-by: benoit.masson --- Documentation/hwmon/it87.rst | 8 ++++++ drivers/hwmon/it87.c | 52 +++++++++++++++++++++++++++++++++++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/Documentation/hwmon/it87.rst b/Documentation/hwmon/it87.rst index 5cef4f265000..fa968be84f7c 100644 --- a/Documentation/hwmon/it87.rst +++ b/Documentation/hwmon/it87.rst @@ -11,6 +11,14 @@ Supported chips: =20 Datasheet: Not publicly available =20 + * IT8613E + + Prefix: 'it8613' + + Addresses scanned: from Super I/O config space (8 I/O ports) + + Datasheet: Not publicly available + * IT8620E =20 Prefix: 'it8620' diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 4453bf3e8ef4..6a0ee13bc95f 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -333,6 +333,7 @@ struct it87_devices { #define FEAT_FOUR_TEMP BIT(22) #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */ #define FEAT_NEW_TEMPMAP BIT(24) /* PWM uses extended temp map */ +#define FEAT_11MV_ADC BIT(25) =20 static const struct it87_devices it87_devices[] =3D { [it87] =3D { @@ -552,6 +553,14 @@ static const struct it87_devices it87_devices[] =3D { [it8613] =3D { .name =3D "it8613", .model =3D "IT8613E", + .features =3D FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS + | FEAT_TEMP_PECI | FEAT_FIVE_FANS + | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 + | FEAT_AVCC3 | FEAT_NEW_TEMPMAP, + .num_temp_limit =3D 6, + .num_temp_offset =3D 6, + .num_temp_map =3D 6, + .peci_mask =3D 0x07, }, [it8620] =3D { .name =3D "it8620", @@ -612,6 +621,7 @@ static const struct it87_devices it87_devices[] =3D { #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) +#define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC) #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ @@ -641,7 +651,8 @@ static const struct it87_devices it87_devices[] =3D { #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) #define has_noconf(data) ((data)->features & FEAT_NOCONF) #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ - FEAT_10_9MV_ADC)) + FEAT_10_9MV_ADC | \ + FEAT_11MV_ADC)) #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF) #define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP) =20 @@ -748,6 +759,8 @@ static int adc_lsb(const struct it87_data *data, int nr) lsb =3D 120; else if (has_10_9mv_adc(data)) lsb =3D 109; + else if (has_11mv_adc(data)) + lsb =3D 110; else lsb =3D 160; if (data->in_scaled & BIT(nr)) @@ -3171,6 +3184,43 @@ static int __init it87_find(int sioaddr, unsigned sh= ort *address, sio_data->skip_in |=3D BIT(5); /* No VIN5 */ sio_data->skip_in |=3D BIT(6); /* No VIN6 */ =20 + sio_data->beep_pin =3D superio_inb(sioaddr, + IT87_SIO_BEEP_PIN_REG) & 0x3f; + } else if (sio_data->type =3D=3D it8613) { + int reg27, reg29, reg2a; + + superio_select(sioaddr, GPIO); + + /* Check for pwm3, fan3, pwm5, fan5 */ + reg27 =3D superio_inb(sioaddr, IT87_SIO_GPIO3_REG); + if (!(reg27 & BIT(1))) + sio_data->skip_fan |=3D BIT(4); + if (reg27 & BIT(3)) + sio_data->skip_pwm |=3D BIT(4); + if (reg27 & BIT(6)) + sio_data->skip_pwm |=3D BIT(2); + if (reg27 & BIT(7)) + sio_data->skip_fan |=3D BIT(2); + + /* Check for pwm2, fan2 */ + reg29 =3D superio_inb(sioaddr, IT87_SIO_GPIO5_REG); + if (reg29 & BIT(1)) + sio_data->skip_pwm |=3D BIT(1); + if (reg29 & BIT(2)) + sio_data->skip_fan |=3D BIT(1); + + /* Check for pwm4, fan4 */ + reg2a =3D superio_inb(sioaddr, IT87_SIO_PINX1_REG); + if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) { + sio_data->skip_fan |=3D BIT(3); + sio_data->skip_pwm |=3D BIT(3); + } + + sio_data->skip_pwm |=3D BIT(0); /* No pwm1 */ + sio_data->skip_fan |=3D BIT(0); /* No fan1 */ + sio_data->skip_in |=3D BIT(3); /* No VIN3 */ + sio_data->skip_in |=3D BIT(6); /* No VIN6 */ + sio_data->beep_pin =3D superio_inb(sioaddr, IT87_SIO_BEEP_PIN_REG) & 0x3f; } else if (sio_data->type =3D=3D it8620 || sio_data->type =3D=3D it8628) { --=20 2.50.1 (Apple Git-155)