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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ5PEPF000001F4.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.1 via Frontend Transport; Wed, 14 Jan 2026 18:28:13 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 14 Jan 2026 12:28:12 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 33/34] cxl: Update Endpoint correctable protocol error handling Date: Wed, 14 Jan 2026 12:20:54 -0600 Message-ID: <20260114182055.46029-34-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|PH7PR12MB7233:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ef17c50-4e6c-4773-f7d7-08de539aadb2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|1800799024|82310400026|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:28:13.6105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ef17c50-4e6c-4773-f7d7-08de539aadb2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7233 Content-Type: text/plain; charset="utf-8" The CXL drivers must support handling Endpoint CXL and PCI correctable (CE) protocol errors. Update the driver to support both. Introduce cxl_pci_cor_error_detected() to handle PCI correctable errors, replacing cxl_cor_error_detected(). Implement this new function to call the existing CXL correctable handler, cxl_port_cor_error_detected(). Update cxl_port_cor_error_detected() for correct Endpoint handling. Take the CXL memory device lock, check for a valid driver, and handle Restricted CXL Device (RCD) if needed. Signed-off-by: Terry Bowman --- Changes in v13->v14: - New commit - Change cxl_cor_error_detected() parameter to &pdev->dev device from memdev device. (Terry) - Updated commit message (Terry) --- drivers/cxl/core/ras.c | 52 ++++++++++++++++++++++++++---------------- drivers/cxl/cxlpci.h | 6 +++-- drivers/cxl/pci.c | 2 +- 3 files changed, 37 insertions(+), 23 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index dc6e02d64821..427009a8a78a 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -267,8 +267,10 @@ void cxl_handle_cor_ras(struct device *dev, u64 serial= , void __iomem *ras_base) void __iomem *addr; u32 status; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return; + } =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); @@ -345,7 +347,30 @@ pci_ers_result_t cxl_handle_ras(struct device *dev, u6= 4 serial, void __iomem *ra =20 static void cxl_port_cor_error_detected(struct device *dev) { - cxl_handle_cor_ras(dev, 0, cxl_get_ras_base(dev)); + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + u64 serial =3D 0; + + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + + guard(device)(&cxlmd->dev); + + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + serial =3D cxlds->serial; + } + + cxl_handle_cor_ras(dev, serial, cxl_get_ras_base(dev)); } =20 static pci_ers_result_t cxl_port_error_detected(struct device *dev) @@ -376,28 +401,15 @@ static pci_ers_result_t cxl_port_error_detected(struc= t device *dev) return cxl_handle_ras(dev, serial, cxl_get_ras_base(dev)); } =20 -void cxl_cor_error_detected(struct pci_dev *pdev) +void cxl_pci_cor_error_detected(struct pci_dev *pdev) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlds->cxlmd->dev; - - guard(device)(dev); - - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); + guard(device)(&port->dev); =20 - cxl_handle_cor_ras(&cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); + cxl_port_cor_error_detected(&pdev->dev); } -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_pci_cor_error_detected, "CXL"); =20 pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error) diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index f218b343e179..3d70f9b4a193 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -78,7 +78,7 @@ struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS -void cxl_cor_error_detected(struct pci_dev *pdev); +void cxl_pci_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); @@ -90,7 +90,9 @@ int __cxl_await_media_ready(struct cxl_dev_state *cxlds); resource_size_t __cxl_rcd_component_reg_phys(struct device *dev, struct cxl_dport *dport); #else -static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } +static inline void cxl_pci_cor_error_detected(struct pci_dev *pdev) +{ +} static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ff741adc7c7f..328b4ea8dbc5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1055,7 +1055,7 @@ static const struct pci_error_handlers pci_error_hand= lers =3D { .error_detected =3D cxl_pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, - .cor_error_detected =3D cxl_cor_error_detected, + .cor_error_detected =3D cxl_pci_cor_error_detected, .reset_done =3D cxl_reset_done, }; =20 --=20 2.34.1