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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ5PEPF000001F1.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.1 via Frontend Transport; Wed, 14 Jan 2026 18:27:57 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 14 Jan 2026 12:27:56 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 32/34] cxl: Update Endpoint uncorrectable protocol error handling Date: Wed, 14 Jan 2026 12:20:53 -0600 Message-ID: <20260114182055.46029-33-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F1:EE_|BL1PR12MB5922:EE_ X-MS-Office365-Filtering-Correlation-Id: bea2b466-fd31-4ded-710a-08de539aa421 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:27:57.5573 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bea2b466-fd31-4ded-710a-08de539aa421 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5922 Content-Type: text/plain; charset="utf-8" The CXL drivers must support handling Endpoint CXL and PCI uncorrectable (UCE) protocol errors. Update the drivers to support both. Introduce cxl_pci_error_detected() to handle PCI correctable errors, replacing cxl_error_detected(). Implement this new function to call the existing CXL Port uncorrectable handler, cxl_port_error_detected(). Update cxl_port_error_detected() for Endpoint handling. Take the CXL memory device lock, check for a valid driver, and handle restricted CXL device (RCH) if needed. This is the same sequence initially in cxl_error_detected(). But, the UCE handler's logic for the returned result errors is simplified because recovery will not be tried and instead UCE's will result in the CXL driver invoking system panic. Signed-off-by: Terry Bowman --- Changes in v13->v14: - Update commit headline (Bjorn) - Rename pci_error_detected()/pci_cor_error_detected() -> cxl_pci_error_detected/cxl_pci_cor_error_detected() (Jonathan) - Remove now-invalid comment in cxl_error_detected() (Jonathan) - Split into separate patches for UCE and CE (Terry) Changes in v12->v13: - Update commit messaqge (Terry) - Updated all the implementation and commit message. (Terry) - Refactored cxl_cor_error_detected()/cxl_error_detected() to remove pdev (Dave Jiang) Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/cxl/core/core.h | 9 ++-- drivers/cxl/core/ras.c | 92 +++++++++++++++++++---------------------- drivers/cxl/cxlpci.h | 15 ++++--- drivers/cxl/pci.c | 6 +-- 4 files changed, 60 insertions(+), 62 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 39324e1b8940..96c6cf478427 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -4,6 +4,7 @@ #ifndef __CXL_CORE_H__ #define __CXL_CORE_H__ =20 +#include #include #include =20 @@ -147,7 +148,7 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port= *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base= ); +pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, void __iom= em *ras_base); void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); @@ -158,11 +159,11 @@ static inline int cxl_ras_init(void) return 0; } static inline void cxl_ras_exit(void) { } -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) +static inline pci_ers_result_t cxl_handle_ras(struct device *dev, u64 seri= al, void __iomem *ras_base) { - return false; + return PCI_ERS_RESULT_NONE; } -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } +static inline void cxl_handle_cor_ras(struct device *dev, u64 serial, void= __iomem *ras_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 96ce85cc0a46..dc6e02d64821 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -218,6 +218,7 @@ static void __iomem *cxl_get_ras_base(struct device *de= v) return dport->regs.ras; } case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_ENDPOINT: { struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&p= dev->dev); =20 @@ -302,20 +303,22 @@ static void header_log_copy(void __iomem *ras_base, u= 32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) +pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, void __iom= em *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; u32 status; u32 fe; =20 - if (!ras_base) - return false; + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); + return PCI_ERS_RESULT_NONE; + } =20 addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status =3D readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; + return PCI_ERS_RESULT_NONE; =20 /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { @@ -337,7 +340,7 @@ bool cxl_handle_ras(struct device *dev, u64 serial, voi= d __iomem *ras_base) =20 writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 - return true; + return PCI_ERS_RESULT_PANIC; } =20 static void cxl_port_cor_error_detected(struct device *dev) @@ -347,7 +350,30 @@ static void cxl_port_cor_error_detected(struct device = *dev) =20 static pci_ers_result_t cxl_port_error_detected(struct device *dev) { - return cxl_handle_ras(dev, 0, cxl_get_ras_base(dev)); + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + u64 serial =3D 0; + + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + + guard(device)(&cxlmd->dev); + + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_NONE; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + serial =3D cxlds->serial; + } + + return cxl_handle_ras(dev, serial, cxl_get_ras_base(dev)); } =20 void cxl_cor_error_detected(struct pci_dev *pdev) @@ -373,55 +399,21 @@ void cxl_cor_error_detected(struct pci_dev *pdev) } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + pci_ers_result_t rc; =20 - guard(device)(dev); + guard(device)(&port->dev); =20 - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } + rc =3D cxl_port_error_detected(&pdev->dev); + if (rc =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(&cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; + return rc; } -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_pci_error_detected, "CXL"); =20 static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 532506595d0f..f218b343e179 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -79,15 +79,20 @@ void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS void cxl_cor_error_detected(struct pci_dev *pdev); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); void devm_cxl_port_ras_setup(struct cxl_port *port); +void __cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device= *host); +void __cxl_uport_init_ras_reporting(struct cxl_port *port, + struct device *host); +int __cxl_await_media_ready(struct cxl_dev_state *cxlds); +resource_size_t __cxl_rcd_component_reg_phys(struct device *dev, + struct cxl_dport *dport); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } - -static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) { return PCI_ERS_RESULT_NONE; } diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index acb0eb2a13c3..ff741adc7c7f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1051,8 +1051,8 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 -static const struct pci_error_handlers cxl_error_handlers =3D { - .error_detected =3D cxl_error_detected, +static const struct pci_error_handlers pci_error_handlers =3D { + .error_detected =3D cxl_pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, .cor_error_detected =3D cxl_cor_error_detected, @@ -1063,7 +1063,7 @@ static struct pci_driver cxl_pci_driver =3D { .name =3D KBUILD_MODNAME, .id_table =3D cxl_mem_pci_tbl, .probe =3D cxl_pci_probe, - .err_handler =3D &cxl_error_handlers, + .err_handler =3D &pci_error_handlers, .dev_groups =3D cxl_rcd_groups, .driver =3D { .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, --=20 2.34.1