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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ5PEPF000001F7.mail.protection.outlook.com (10.167.242.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.1 via Frontend Transport; Wed, 14 Jan 2026 18:25:57 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 14 Jan 2026 12:25:56 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 23/34] cxl: Map CXL Endpoint Port and CXL Switch Port RAS registers Date: Wed, 14 Jan 2026 12:20:44 -0600 Message-ID: <20260114182055.46029-24-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F7:EE_|IA1PR12MB6234:EE_ X-MS-Office365-Filtering-Correlation-Id: cb042200-02aa-481d-325e-08de539a5cc8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:25:57.8547 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb042200-02aa-481d-325e-08de539a5cc8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6234 Content-Type: text/plain; charset="utf-8" In preparation for CXL VH (Virtual Host) topology protocol error handling, add RAS capability registered mapping for all ports in a CXL VH topology. This includes the RAS capabilities of Switch Upstream Ports, Switch Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports ("downstream") Update cxl_port_add_dport() to map the upstream RAS capability on first 'dport' attach, and downstream RAS capability on each 'dport' attach. Arrange for dport mappings to be released at del_dport() time. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang [djbw: reword changelog, fix devm handling] Co-developed-by: Dan Williams Signed-off-by: Dan Williams --- Changes in v13->v14: - Correct message spelling (Terry) --- drivers/cxl/core/port.c | 2 +- drivers/cxl/core/ras.c | 11 +++++++++++ drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlpci.h | 4 ++++ drivers/cxl/port.c | 37 +++++++++++++++++++++++++++++++++++ tools/testing/cxl/Kbuild | 1 + tools/testing/cxl/test/mock.c | 12 ++++++++++++ 7 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2184c20af011..2c4e28e7975c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1451,7 +1451,7 @@ static void del_dport(struct cxl_dport *dport) { struct cxl_port *port =3D dport->port; =20 - devm_release_action(&port->dev, unlink_dport, dport); + devres_release_group(&port->dev, dport); } =20 static void del_dports(struct cxl_port *port) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 84abcf90fa99..76ac567724e3 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -162,6 +162,17 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport) } EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_ras_setup, "CXL"); =20 +void devm_cxl_port_ras_setup(struct cxl_port *port) +{ + struct cxl_register_map *map =3D &port->reg_map; + + map->host =3D &port->dev; + if (cxl_map_component_regs(map, &port->regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(&port->dev, "Failed to map RAS capability\n"); +} +EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 46491046f101..805923693707 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -607,6 +607,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -628,6 +629,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs regs; int nr_dports; int hdm_end; int commit_end; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index e41bb93d583a..ef4496b4e55e 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -82,6 +82,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); +void devm_cxl_port_ras_setup(struct cxl_port *port); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } =20 @@ -93,6 +94,9 @@ static inline pci_ers_result_t cxl_error_detected(struct = pci_dev *pdev, static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { } +static inline void devm_cxl_port_ras_setup(struct cxl_port *port) +{ +} #endif =20 #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 8f8fc98c1428..0d6e010e21ca 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -176,11 +176,29 @@ static struct cxl_port *cxl_port_devres_group(struct = cxl_port *port) DEFINE_FREE(cxl_port_group_free, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T)) =20 +static struct cxl_dport *cxl_dport_devres_group(struct cxl_dport *dport) +{ + if (!devres_open_group(&dport->port->dev, dport, GFP_KERNEL)) + return ERR_PTR(-ENOMEM); + return dport; +} +DEFINE_FREE(cxl_dport_group_free, struct cxl_dport *, + if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->port->dev, _T)) + static void cxl_port_group_close(struct cxl_port *port) { devres_remove_group(&port->dev, port); } =20 +/* + * Unlike the port group, that just facilitates unwind of setup failures, = the + * dport group needs to stay live for del_dport() to reference. + */ +static void cxl_dport_group_close(struct cxl_dport *dport) +{ + devres_close_group(&dport->port->dev, dport); +} + static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port, struct device *dport_dev) { @@ -209,6 +227,13 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl= _port *port, rc =3D devm_cxl_switch_port_decoders_setup(port); if (rc) return ERR_PTR(rc); + + /* + * RAS setup is optional, either driver operation can continue + * on failure, or the device does not implement RAS registers. + */ + devm_cxl_port_ras_setup(port); + /* * Note, when nr_dports returns to zero the port is unregistered * and triggers cleanup. I.e. no need for open-coded release @@ -220,12 +245,24 @@ static struct cxl_dport *cxl_port_add_dport(struct cx= l_port *port, if (IS_ERR(new_dport)) return new_dport; =20 + /* + * Establish a group for all dport resources that need to be released + * when the dport is deleted. + */ + struct cxl_dport *dport_group __free(cxl_dport_group_free) =3D + cxl_dport_devres_group(new_dport); + if (IS_ERR(dport_group)) + return ERR_CAST(dport_group); + rc =3D cxl_dport_autoremove(new_dport); if (rc) return ERR_PTR(rc); =20 + devm_cxl_dport_ras_setup(new_dport); + cxl_switch_parse_cdat(new_dport); =20 + cxl_dport_group_close(no_free_ptr(dport_group)); cxl_port_group_close(no_free_ptr(port_group)); =20 dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n", diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 7250bedf0448..6c516019600e 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -13,6 +13,7 @@ ldflags-y +=3D --wrap=3Ddevm_cxl_endpoint_decoders_setup ldflags-y +=3D --wrap=3Dhmat_get_extended_linear_cache_size ldflags-y +=3D --wrap=3Dcxl_add_dport_by_dev ldflags-y +=3D --wrap=3Ddevm_cxl_switch_port_decoders_setup +ldflags-y +=3D --wrap=3Ddevm_cxl_port_ras_setup =20 DRIVERS :=3D ../../../drivers CXL_SRC :=3D $(DRIVERS)/cxl diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 8883357ee50d..a0b87bbb2f75 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -246,6 +246,18 @@ void __wrap_devm_cxl_dport_ras_setup(struct cxl_dport = *dport) } EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_dport_ras_setup, "CXL"); =20 +void __wrap_devm_cxl_port_ras_setup(struct cxl_port *port) +{ + int index; + struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); + + if (!ops || !ops->is_mock_port(port->uport_dev)) + devm_cxl_port_ras_setup(port); + + put_cxl_mock_ops(index); +} +EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_port_ras_setup, "CXL"); + struct cxl_dport *__wrap_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_dev) { --=20 2.34.1