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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:21:20.8862 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a034ba28-c9ea-424b-6c41-08de5399b7a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7438 Content-Type: text/plain; charset="utf-8" The CXL DVSECs are currently defined in cxl/core/cxlpci.h. These are not accessible to other subsystems. Move these to uapi/linux/pci_regs.h. The CXL DVSEC definitions will be renamed and reformatted to fit better with existing defines. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams Acked-by: Bjorn Helgaas ---- Changes in v13->v14: - Add Jonathan's and Dan's review-by - Update commit title prefix (Bjorn) - Revert format fix for cxl_sbr_masked() (Jonathan) - Update 'Compute Express Link' comment block (Jonathan) - Move PCI_DVSEC_CXL_FLEXBUS definitions to later patch where used (Jonathan) - Removed stray change (Bjorn) Changes in v12->v13: - Add Dave Jiang's reviewed-by - Remove changes to existing PCI_DVSEC_CXL_PORT* defines. Update commit message. (Jonathan) Changes in v11 -> v12: - Change formatting to be same as existing definitions - Change GENMASK() -> __GENMASK() and BIT() to _BITUL() Changes in v10 -> v11: - New commit --- drivers/cxl/cxlpci.h | 53 ----------------------------- include/uapi/linux/pci_regs.h | 64 ++++++++++++++++++++++++++++++++--- 2 files changed, 59 insertions(+), 58 deletions(-) diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 1d526bea8431..cdb7cf3dbcb4 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -7,59 +7,6 @@ =20 #define CXL_MEMORY_PROGIF 0x10 =20 -/* - * See section 8.1 Configuration Space Registers in the CXL 2.0 - * Specification. Names are taken straight from the specification with "CX= L" and - * "DVSEC" redundancies removed. When obvious, abbreviations may be used. - */ -#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20) - -/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ -#define CXL_DVSEC_PCIE_DEVICE 0 -#define CXL_DVSEC_CAP_OFFSET 0xA -#define CXL_DVSEC_MEM_CAPABLE BIT(2) -#define CXL_DVSEC_HDM_COUNT_MASK GENMASK(5, 4) -#define CXL_DVSEC_CTRL_OFFSET 0xC -#define CXL_DVSEC_MEM_ENABLE BIT(2) -#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) -#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) -#define CXL_DVSEC_MEM_INFO_VALID BIT(0) -#define CXL_DVSEC_MEM_ACTIVE BIT(1) -#define CXL_DVSEC_MEM_SIZE_LOW_MASK GENMASK(31, 28) -#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) -#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) -#define CXL_DVSEC_MEM_BASE_LOW_MASK GENMASK(31, 28) - -#define CXL_DVSEC_RANGE_MAX 2 - -/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */ -#define CXL_DVSEC_FUNCTION_MAP 2 - -/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */ -#define CXL_DVSEC_PORT_EXTENSIONS 3 - -/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */ -#define CXL_DVSEC_PORT_GPF 4 -#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK GENMASK(11, 8) -#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK GENMASK(11, 8) - -/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */ -#define CXL_DVSEC_DEVICE_GPF 5 - -/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */ -#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7 - -/* CXL 2.0 8.1.9: Register Locator DVSEC */ -#define CXL_DVSEC_REG_LOCATOR 8 -#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC -#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16) - /* * NOTE: Currently all the functions which are enabled for CXL require the= ir * vectors to be in the first 16. Use this as the default max. diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3add74ae2594..6c4b6f19b18e 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1253,11 +1253,6 @@ #define PCI_DEV3_STA 0x0c /* Device 3 Status Register */ #define PCI_DEV3_STA_SEGMENT 0x8 /* Segment Captured (end-to-end flit-mod= e detected) */ =20 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ -#define PCI_DVSEC_CXL_PORT 3 -#define PCI_DVSEC_CXL_PORT_CTL 0x0c -#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 - /* Integrity and Data Encryption Extended Capability */ #define PCI_IDE_CAP 0x04 #define PCI_IDE_CAP_LINK 0x1 /* Link IDE Stream Supported */ @@ -1338,4 +1333,63 @@ #define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) #define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZ= E * (nr_assoc)) =20 +/* Compute Express Link (CXL r3.1, sec 8.1.5) */ +#define PCI_DVSEC_CXL_PORT 3 +#define PCI_DVSEC_CXL_PORT_CTL 0x0c +#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 + +/* + * Compute Express Link (CXL r3.2, sec 8.1) + * + * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state + * is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these + * registers on downstream link-up events. + */ +#define PCI_DVSEC_HEADER1_LENGTH_MASK __GENMASK(31, 20) + +/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */ +#define CXL_DVSEC_PCIE_DEVICE 0 +#define CXL_DVSEC_CAP_OFFSET 0xA +#define CXL_DVSEC_MEM_CAPABLE _BITUL(2) +#define CXL_DVSEC_HDM_COUNT_MASK __GENMASK(5, 4) +#define CXL_DVSEC_CTRL_OFFSET 0xC +#define CXL_DVSEC_MEM_ENABLE _BITUL(2) +#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) +#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) +#define CXL_DVSEC_MEM_INFO_VALID _BITUL(0) +#define CXL_DVSEC_MEM_ACTIVE _BITUL(1) +#define CXL_DVSEC_MEM_SIZE_LOW_MASK __GENMASK(31, 28) +#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) +#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) +#define CXL_DVSEC_MEM_BASE_LOW_MASK __GENMASK(31, 28) + +#define CXL_DVSEC_RANGE_MAX 2 + +/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */ +#define CXL_DVSEC_FUNCTION_MAP 2 + +/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */ +#define CXL_DVSEC_PORT 3 +#define CXL_DVSEC_PORT_CTL 0x0c +#define CXL_DVSEC_PORT_CTL_UNMASK_SBR 0x00000001 + +/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */ +#define CXL_DVSEC_PORT_GPF 4 +#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C +#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK __GENMASK(3, 0) +#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK __GENMASK(11, 8) +#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE +#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK __GENMASK(3, 0) +#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK __GENMASK(11, 8) + +/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */ +#define CXL_DVSEC_DEVICE_GPF 5 + +/* CXL 3.2 8.1.9: Register Locator DVSEC */ +#define CXL_DVSEC_REG_LOCATOR 8 +#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC +#define CXL_DVSEC_REG_LOCATOR_BIR_MASK __GENMASK(2, 0) +#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK __GENMASK(15, 8) +#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK __GENMASK(31, 16) + #endif /* LINUX_PCI_REGS_H */ --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013024.outbound.protection.outlook.com [40.107.201.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20455335078; 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Wed, 14 Jan 2026 12:21:33 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 02/34] PCI: Update CXL DVSEC definitions Date: Wed, 14 Jan 2026 12:20:23 -0600 Message-ID: <20260114182055.46029-3-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|CY5PR12MB6059:EE_ X-MS-Office365-Filtering-Correlation-Id: 1bec615a-7ec0-4931-9d0a-08de5399c07f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:21:35.7004 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1bec615a-7ec0-4931-9d0a-08de5399c07f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6059 Content-Type: text/plain; charset="utf-8" CXL DVSEC definitions were recently moved into uapi/pci_regs.h, but the newly added macros do not follow the file's existing naming conventions. The current format uses CXL_DVSEC_XYZ, while the new CXL entries must instead use the PCI_DVSEC_CXL_XYZ prefix to match the conventions already established in pci_regs.h. The new CXL DVSEC macros also introduce _MASK and _OFFSET suffixes, which are not used anywhere else in the file. These suffixes lengthen the identifiers and reduce readability. Remove _MASK and _OFFSET from the recently added definitions. Additionally, remove PCI_DVSEC_HEADER1_LENGTH, as it duplicates the existing PCI_DVSEC_HEADER1_LEN() macro. Update all existing references to use the new macro names. Finally, update the inline documentation to reference the latest revision of the CXL specification. Signed-off-by: Terry Bowman Reviewed-by: Dan Williams Acked-by: Bjorn Helgaas --- Changes in v13->v14: - New patch. Split from previous patch such that there is now a separate move patch and a format fix patch. - Formatting update requested (Bjorn) - Remove PCI_DVSEC_HEADER1_LENGTH_MASK because it duplicates PCI_DVSEC_HEADER1_LEN() (Bjorn) - Add Dan's review-by --- drivers/cxl/core/pci.c | 58 ++++++++++----------- drivers/cxl/core/regs.c | 14 +++--- drivers/cxl/pci.c | 2 +- include/uapi/linux/pci_regs.h | 94 ++++++++++++++++------------------- 4 files changed, 81 insertions(+), 87 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 5b023a0178a4..077b386e0c8d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -86,12 +86,12 @@ static int cxl_dvsec_mem_range_valid(struct cxl_dev_sta= te *cxlds, int id) i =3D 1; do { rc =3D pci_read_config_dword(pdev, - d + CXL_DVSEC_RANGE_SIZE_LOW(id), + d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - valid =3D FIELD_GET(CXL_DVSEC_MEM_INFO_VALID, temp); + valid =3D FIELD_GET(PCI_DVSEC_CXL_MEM_INFO_VALID, temp); if (valid) break; msleep(1000); @@ -121,11 +121,11 @@ static int cxl_dvsec_mem_range_active(struct cxl_dev_= state *cxlds, int id) /* Check MEM ACTIVE bit, up to 60s timeout by default */ for (i =3D media_ready_timeout; i; i--) { rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(id), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(id), &temp); if (rc) return rc; =20 - active =3D FIELD_GET(CXL_DVSEC_MEM_ACTIVE, temp); + active =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ACTIVE, temp); if (active) break; msleep(1000); @@ -154,11 +154,11 @@ int cxl_await_media_ready(struct cxl_dev_state *cxlds) u16 cap; =20 rc =3D pci_read_config_word(pdev, - d + CXL_DVSEC_CAP_OFFSET, &cap); + d + PCI_DVSEC_CXL_CAP, &cap); if (rc) return rc; =20 - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT, cap); for (i =3D 0; i < hdm_count; i++) { rc =3D cxl_dvsec_mem_range_valid(cxlds, i); if (rc) @@ -186,16 +186,16 @@ static int cxl_set_mem_enable(struct cxl_dev_state *c= xlds, u16 val) u16 ctrl; int rc; =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, &ctrl); if (rc < 0) return rc; =20 - if ((ctrl & CXL_DVSEC_MEM_ENABLE) =3D=3D val) + if ((ctrl & PCI_DVSEC_CXL_MEM_ENABLE) =3D=3D val) return 1; - ctrl &=3D ~CXL_DVSEC_MEM_ENABLE; + ctrl &=3D ~PCI_DVSEC_CXL_MEM_ENABLE; ctrl |=3D val; =20 - rc =3D pci_write_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, ctrl); + rc =3D pci_write_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, ctrl); if (rc < 0) return rc; =20 @@ -211,7 +211,7 @@ static int devm_cxl_enable_mem(struct device *host, str= uct cxl_dev_state *cxlds) { int rc; =20 - rc =3D cxl_set_mem_enable(cxlds, CXL_DVSEC_MEM_ENABLE); + rc =3D cxl_set_mem_enable(cxlds, PCI_DVSEC_CXL_MEM_ENABLE); if (rc < 0) return rc; if (rc > 0) @@ -273,11 +273,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return -ENXIO; } =20 - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CAP_OFFSET, &cap); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CAP, &cap); if (rc) return rc; =20 - if (!(cap & CXL_DVSEC_MEM_CAPABLE)) { + if (!(cap & PCI_DVSEC_CXL_MEM_CAPABLE)) { dev_dbg(dev, "Not MEM Capable\n"); return -ENXIO; } @@ -288,7 +288,7 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * driver is for a spec defined class code which must be CXL.mem * capable, there is no point in continuing to enable CXL.mem. */ - hdm_count =3D FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + hdm_count =3D FIELD_GET(PCI_DVSEC_CXL_HDM_COUNT, cap); if (!hdm_count || hdm_count > 2) return -EINVAL; =20 @@ -297,11 +297,11 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, * disabled, and they will remain moot after the HDM Decoder * capability is enabled. */ - rc =3D pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl); + rc =3D pci_read_config_word(pdev, d + PCI_DVSEC_CXL_CTRL, &ctrl); if (rc) return rc; =20 - info->mem_enabled =3D FIELD_GET(CXL_DVSEC_MEM_ENABLE, ctrl); + info->mem_enabled =3D FIELD_GET(PCI_DVSEC_CXL_MEM_ENABLE, ctrl); if (!info->mem_enabled) return 0; =20 @@ -314,35 +314,35 @@ int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, return rc; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i), &temp); if (rc) return rc; =20 size =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_SIZE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_SIZE_LOW(i), &temp); if (rc) return rc; =20 - size |=3D temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; + size |=3D temp & PCI_DVSEC_CXL_MEM_SIZE_LOW; if (!size) { continue; } =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_HIGH(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_HIGH(i), &temp); if (rc) return rc; =20 base =3D (u64)temp << 32; =20 rc =3D pci_read_config_dword( - pdev, d + CXL_DVSEC_RANGE_BASE_LOW(i), &temp); + pdev, d + PCI_DVSEC_CXL_RANGE_BASE_LOW(i), &temp); if (rc) return rc; =20 - base |=3D temp & CXL_DVSEC_MEM_BASE_LOW_MASK; + base |=3D temp & PCI_DVSEC_CXL_MEM_BASE_LOW; =20 info->dvsec_range[ranges++] =3D (struct range) { .start =3D base, @@ -1068,7 +1068,7 @@ u16 cxl_gpf_get_dvsec(struct device *dev) is_port =3D false; =20 dvsec =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - is_port ? CXL_DVSEC_PORT_GPF : CXL_DVSEC_DEVICE_GPF); + is_port ? PCI_DVSEC_CXL_PORT_GPF : PCI_DVSEC_CXL_DEVICE_GPF); if (!dvsec) dev_warn(dev, "%s GPF DVSEC not present\n", is_port ? "Port" : "Device"); @@ -1084,14 +1084,14 @@ static int update_gpf_port_dvsec(struct pci_dev *pd= ev, int dvsec, int phase) =20 switch (phase) { case 1: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE; break; case 2: - offset =3D CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET; - base =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK; - scale =3D CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK; + offset =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL; + base =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE; + scale =3D PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE; break; default: return -EINVAL; diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 5ca7b0eed568..a010b3214342 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -271,10 +271,10 @@ EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, "CXL"); static bool cxl_decode_regblock(struct pci_dev *pdev, u32 reg_lo, u32 reg_= hi, struct cxl_register_map *map) { - u8 reg_type =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK, reg_lo); - int bar =3D FIELD_GET(CXL_DVSEC_REG_LOCATOR_BIR_MASK, reg_lo); + u8 reg_type =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID, reg_lo); + int bar =3D FIELD_GET(PCI_DVSEC_CXL_REG_LOCATOR_BIR, reg_lo); u64 offset =3D ((u64)reg_hi << 32) | - (reg_lo & CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK); + (reg_lo & PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW); =20 if (offset > pci_resource_len(pdev, bar)) { dev_warn(&pdev->dev, @@ -311,15 +311,15 @@ static int __cxl_find_regblock_instance(struct pci_de= v *pdev, enum cxl_regloc_ty }; =20 regloc =3D pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, - CXL_DVSEC_REG_LOCATOR); + PCI_DVSEC_CXL_REG_LOCATOR); if (!regloc) return -ENXIO; =20 pci_read_config_dword(pdev, regloc + PCI_DVSEC_HEADER1, ®loc_size); - regloc_size =3D FIELD_GET(PCI_DVSEC_HEADER1_LENGTH_MASK, regloc_size); + regloc_size =3D PCI_DVSEC_HEADER1_LEN(regloc_size); =20 - regloc +=3D CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET; - regblocks =3D (regloc_size - CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET) / 8; + regloc +=3D PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1; + regblocks =3D (regloc_size - PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1) / 8; =20 for (i =3D 0; i < regblocks; i++, regloc +=3D 8) { u32 reg_lo, reg_hi; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 0be4e508affe..b7f694bda913 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -933,7 +933,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) cxlds->rcd =3D is_cxl_restricted(pdev); cxlds->serial =3D pci_get_dsn(pdev); cxlds->cxl_dvsec =3D pci_find_dvsec_capability( - pdev, PCI_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + pdev, PCI_VENDOR_ID_CXL, PCI_DVSEC_CXL_DEVICE); if (!cxlds->cxl_dvsec) dev_warn(&pdev->dev, "Device DVSEC not present, skip CXL.mem init\n"); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 6c4b6f19b18e..662582bdccf0 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1333,63 +1333,57 @@ #define PCI_IDE_SEL_ADDR_3(x) (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE) #define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc) (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZ= E * (nr_assoc)) =20 -/* Compute Express Link (CXL r3.1, sec 8.1.5) */ -#define PCI_DVSEC_CXL_PORT 3 -#define PCI_DVSEC_CXL_PORT_CTL 0x0c -#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 - /* - * Compute Express Link (CXL r3.2, sec 8.1) + * Compute Express Link (CXL r4.0, sec 8.1) * * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state - * is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these + * is "disconnected" (CXL r4.0, sec 9.12.3). Re-enumerate these * registers on downstream link-up events. */ -#define PCI_DVSEC_HEADER1_LENGTH_MASK __GENMASK(31, 20) - -/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */ -#define CXL_DVSEC_PCIE_DEVICE 0 -#define CXL_DVSEC_CAP_OFFSET 0xA -#define CXL_DVSEC_MEM_CAPABLE _BITUL(2) -#define CXL_DVSEC_HDM_COUNT_MASK __GENMASK(5, 4) -#define CXL_DVSEC_CTRL_OFFSET 0xC -#define CXL_DVSEC_MEM_ENABLE _BITUL(2) -#define CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) -#define CXL_DVSEC_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) -#define CXL_DVSEC_MEM_INFO_VALID _BITUL(0) -#define CXL_DVSEC_MEM_ACTIVE _BITUL(1) -#define CXL_DVSEC_MEM_SIZE_LOW_MASK __GENMASK(31, 28) -#define CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) -#define CXL_DVSEC_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) -#define CXL_DVSEC_MEM_BASE_LOW_MASK __GENMASK(31, 28) + +/* CXL r4.0, 8.1.3: PCIe DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE 0 +#define PCI_DVSEC_CXL_CAP 0xA +#define PCI_DVSEC_CXL_MEM_CAPABLE _BITUL(2) +#define PCI_DVSEC_CXL_HDM_COUNT __GENMASK(5, 4) +#define PCI_DVSEC_CXL_CTRL 0xC +#define PCI_DVSEC_CXL_MEM_ENABLE _BITUL(2) +#define PCI_DVSEC_CXL_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_SIZE_LOW(i) (0x1C + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_INFO_VALID _BITUL(0) +#define PCI_DVSEC_CXL_MEM_ACTIVE _BITUL(1) +#define PCI_DVSEC_CXL_MEM_SIZE_LOW __GENMASK(31, 28) +#define PCI_DVSEC_CXL_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10)) +#define PCI_DVSEC_CXL_RANGE_BASE_LOW(i) (0x24 + (i * 0x10)) +#define PCI_DVSEC_CXL_MEM_BASE_LOW __GENMASK(31, 28) =20 #define CXL_DVSEC_RANGE_MAX 2 =20 -/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */ -#define CXL_DVSEC_FUNCTION_MAP 2 - -/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */ -#define CXL_DVSEC_PORT 3 -#define CXL_DVSEC_PORT_CTL 0x0c -#define CXL_DVSEC_PORT_CTL_UNMASK_SBR 0x00000001 - -/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */ -#define CXL_DVSEC_PORT_GPF 4 -#define CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET 0x0C -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK __GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK __GENMASK(11, 8) -#define CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET 0xE -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK __GENMASK(3, 0) -#define CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK __GENMASK(11, 8) - -/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */ -#define CXL_DVSEC_DEVICE_GPF 5 - -/* CXL 3.2 8.1.9: Register Locator DVSEC */ -#define CXL_DVSEC_REG_LOCATOR 8 -#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC -#define CXL_DVSEC_REG_LOCATOR_BIR_MASK __GENMASK(2, 0) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK __GENMASK(15, 8) -#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK __GENMASK(31, 16) +/* CXL r4.0, 8.1.4: Non-CXL Function Map DVSEC */ +#define PCI_DVSEC_CXL_FUNCTION_MAP 2 + +/* CXL r4.0, 8.1.5: Extensions DVSEC for Ports */ +#define PCI_DVSEC_CXL_PORT 3 +#define PCI_DVSEC_CXL_PORT_CTL 0x0c +#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR 0x00000001 + +/* CXL r4.0, 8.1.6: GPF DVSEC for CXL Port */ +#define PCI_DVSEC_CXL_PORT_GPF 4 +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_CONTROL 0x0C +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_BASE __GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_1_TMO_SCALE __GENMASK(11, 8) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_CONTROL 0xE +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_BASE __GENMASK(3, 0) +#define PCI_DVSEC_CXL_PORT_GPF_PHASE_2_TMO_SCALE __GENMASK(11, 8) + +/* CXL r4.0, 8.1.7: GPF DVSEC for CXL Device */ +#define PCI_DVSEC_CXL_DEVICE_GPF 5 + +/* CXL r4.0, 8.1.9: Register Locator DVSEC */ +#define PCI_DVSEC_CXL_REG_LOCATOR 8 +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1 0xC +#define PCI_DVSEC_CXL_REG_LOCATOR_BIR __GENMASK(2, 0) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID __GENMASK(15, 8) +#define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW __GENMASK(31, 16) =20 #endif /* LINUX_PCI_REGS_H */ --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011059.outbound.protection.outlook.com [40.107.208.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80F052FFF8F; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:21:46.4826 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: febd3ff3-7385-4378-c073-08de5399c6ec X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6988 Content-Type: text/plain; charset="utf-8" CXL and AER drivers need the ability to identify CXL devices. Introduce set_pcie_cxl() with logic checking for CXL.mem or CXL.cache status in the CXL Flex Bus DVSEC status register. The CXL Flex Bus DVSEC presence is used because it is required for all the CXL PCIe devices.[1] Add boolean 'struct pci_dev::is_cxl' with the purpose to cache the CXL CXL.cache and CXl.mem status. Call set_pcie_cxl() for the parent bridge. Once a device is created there is a possibility the parent training or CXL state was updated as well. This will make certain the correct parent CXL state is cached. Add function pcie_is_cxl() to return 'struct pci_dev::is_cxl'. [1] CXL 3.1 Spec, 8.1.1 PCIe Designated Vendor-Specific Extended Capability (DVSEC) ID Assignment, Table 8-2 Signed-off-by: Terry Bowman Reviewed-by: Ira Weiny Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Alejandro Lucero Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams Acked-by: Bjorn Helgaas --- Changes in v13->v14: - Move FLEXBUS_STATUS DVSEC here (Jonathan) - Remove check for EP and USP (Dan) - Update commit message (Bjorn) - Fix writing past 80 columns (Bjorn) - Add pci_is_pcie() parent bridge check at beginning of function (Bjorn) Changes in v12->v13: - Add Ben's "reviewed-by" Changes in v11->v12: - Add review-by for Alejandro - Add comment in set_pcie_cxl() explaining why updating parent status. Changes in v10->v11: - Amend set_pcie_cxl() to check for Upstream Port's and EP's parent downstream port by calling set_pcie_cxl(). (Dan) - Retitle patch: 'Add' -> 'Introduce' - Add check for CXL.mem and CXL.cache (Alejandro, Dan) --- drivers/pci/probe.c | 31 +++++++++++++++++++++++++++++++ include/linux/pci.h | 6 ++++++ include/uapi/linux/pci_regs.h | 6 ++++++ 3 files changed, 43 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 41183aed8f5d..bd7ce41d0c7a 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1735,6 +1735,35 @@ static void set_pcie_thunderbolt(struct pci_dev *dev) dev->is_thunderbolt =3D 1; } =20 +static void set_pcie_cxl(struct pci_dev *dev) +{ + struct pci_dev *bridge; + u16 dvsec, cap; + + if (!pci_is_pcie(dev)) + return; + + /* + * Update parent's CXL state because alternate protocol training + * may have changed + */ + bridge =3D pci_upstream_bridge(dev); + if (bridge) + set_pcie_cxl(bridge); + + dvsec =3D pci_find_dvsec_capability(dev, PCI_VENDOR_ID_CXL, + PCI_DVSEC_CXL_FLEXBUS_PORT); + if (!dvsec) + return; + + pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS, + &cap); + + dev->is_cxl =3D FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE, cap) || + FIELD_GET(PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM, cap); + +} + static void set_pcie_untrusted(struct pci_dev *dev) { struct pci_dev *parent =3D pci_upstream_bridge(dev); @@ -2065,6 +2094,8 @@ int pci_setup_device(struct pci_dev *dev) /* Need to have dev->cfg_size ready */ set_pcie_thunderbolt(dev); =20 + set_pcie_cxl(dev); + set_pcie_untrusted(dev); =20 if (pci_is_pcie(dev)) diff --git a/include/linux/pci.h b/include/linux/pci.h index 864775651c6f..f8e8b3df794d 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -463,6 +463,7 @@ struct pci_dev { unsigned int is_pciehp:1; unsigned int shpc_managed:1; /* SHPC owned by shpchp */ unsigned int is_thunderbolt:1; /* Thunderbolt controller */ + unsigned int is_cxl:1; /* Compute Express Link (CXL) */ /* * Devices marked being untrusted are the ones that can potentially * execute DMA attacks and similar. They are typically connected @@ -791,6 +792,11 @@ static inline bool pci_is_display(struct pci_dev *pdev) return (pdev->class >> 16) =3D=3D PCI_BASE_CLASS_DISPLAY; } =20 +static inline bool pcie_is_cxl(struct pci_dev *pci_dev) +{ + return pci_dev->is_cxl; +} + #define for_each_pci_bridge(dev, bus) \ list_for_each_entry(dev, &bus->devices, bus_list) \ if (!pci_is_bridge(dev)) {} else diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 662582bdccf0..b6622fd60fd9 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1379,6 +1379,12 @@ /* CXL r4.0, 8.1.7: GPF DVSEC for CXL Device */ #define PCI_DVSEC_CXL_DEVICE_GPF 5 =20 +/* CXL r4.0, 8.1.8: Flex Bus DVSEC */ +#define PCI_DVSEC_CXL_FLEXBUS_PORT 7 +#define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS 0xE +#define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_CACHE _BITUL(0) +#define PCI_DVSEC_CXL_FLEXBUS_PORT_STATUS_MEM _BITUL(2) + /* CXL r4.0, 8.1.9: Register Locator DVSEC */ #define PCI_DVSEC_CXL_REG_LOCATOR 8 #define PCI_DVSEC_CXL_REG_LOCATOR_BLOCK1 0xC --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011042.outbound.protection.outlook.com [52.101.52.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DF2833507C; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:21:57.0713 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0ba3281-b6e3-4d64-5bf6-08de5399cd3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6373 Content-Type: text/plain; charset="utf-8" The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() are unnecessary helper functions used only for Endpoints. Remove these functions as they are not common for all CXL devices and do not provide value for EP handling. Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras() to cxl_handle_cor_ras(). Signed-off-by: Terry Bowman Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Tested-by: Joshua Hahn Reviewed-by: Dan Williams --- Changes in v13->v14: - None Changes in v12->v13: - None Changes in v11->v12: - Added Dave Jiang's review by - Moved to front of series Changes in v10->v11: - None --- drivers/cxl/core/pci.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 077b386e0c8d..3ec7407f0c5d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -632,8 +632,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -649,11 +649,6 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state = *cxlds, } } =20 -static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); -} - /* CXL spec rev3.0 8.2.4.16.1 */ static void header_log_copy(void __iomem *ras_base, u32 *log) { @@ -675,8 +670,8 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) +static bool cxl_handle_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -709,11 +704,6 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxl= ds, return true; } =20 -static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) -{ - return __cxl_handle_ras(cxlds, cxlds->regs.ras); -} - #ifdef CONFIG_PCIEAER_CXL =20 static void cxl_dport_map_rch_aer(struct cxl_dport *dport) @@ -792,13 +782,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "C= XL"); static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_cor_ras(cxlds, dport->regs.ras); + return cxl_handle_cor_ras(cxlds, dport->regs.ras); } =20 static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, struct cxl_dport *dport) { - return __cxl_handle_ras(cxlds, dport->regs.ras); + return cxl_handle_ras(cxlds, dport->regs.ras); } =20 /* @@ -895,7 +885,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_endpoint_cor_ras(cxlds); + cxl_handle_cor_ras(cxlds, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -924,7 +914,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_endpoint_ras(cxlds); + ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); } =20 =20 --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011012.outbound.protection.outlook.com [52.101.62.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31E08335064; Wed, 14 Jan 2026 18:22:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 14 Jan 2026 12:22:06 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 05/34] cxl/pci: Remove unnecessary CXL RCH handling helper functions Date: Wed, 14 Jan 2026 12:20:26 -0600 Message-ID: <20260114182055.46029-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D1:EE_|CY5PR12MB9054:EE_ X-MS-Office365-Filtering-Correlation-Id: 298c19cd-b2c5-43a6-7f9c-08de5399d591 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:22:11.0504 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 298c19cd-b2c5-43a6-7f9c-08de5399d591 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB9054 Content-Type: text/plain; charset="utf-8" cxl_handle_rdport_cor_ras() and cxl_handle_rdport_ras() are specific to Restricted CXL Host (RCH) handling. Improve readability and maintainability by replacing these and instead using the common cxl_handle_cor_ras() and cxl_handle_ras() functions. Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Dan Williams --- Changes in v13->v14: - None Changes in v12->v13: - None Changes in v11->v12: - Add reviewed-by for Alejandro & Dave Jiang - Moved to front of series Changes in v10->v11: - New patch --- drivers/cxl/core/pci.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3ec7407f0c5d..51bb0f372e40 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -779,18 +779,6 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -static void cxl_handle_rdport_cor_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_cor_ras(cxlds, dport->regs.ras); -} - -static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, - struct cxl_dport *dport) -{ - return cxl_handle_ras(cxlds, dport->regs.ras); -} - /* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:22:18.9470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf39c29e-49e0-41ec-75b3-08de5399da46 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5892 Content-Type: text/plain; charset="utf-8" The AER driver includes a CXL support function cxl_error_is_native(). This function adds no additional value from pcie_aer_is_native(). Simplify the codebase by removing cxl_error_is_native() and replace occurrences of cxl_error_is_native() with pcie_aer_is_native(). Signed-off-by: Terry Bowman Reviewed-by: Dan Williams Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13->v14: - New commit (Dan) --- drivers/pci/pcie/aer.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index e0bcaa896803..c99ba2a1159c 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1166,13 +1166,6 @@ static bool is_cxl_mem_dev(struct pci_dev *dev) return true; } =20 -static bool cxl_error_is_native(struct pci_dev *dev) -{ - struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); - - return (pcie_ports_native || host->native_aer); -} - static bool is_internal_error(struct aer_err_info *info) { if (info->severity =3D=3D AER_CORRECTABLE) @@ -1186,7 +1179,7 @@ static int cxl_rch_handle_error_iter(struct pci_dev *= dev, void *data) struct aer_err_info *info =3D (struct aer_err_info *)data; const struct pci_error_handlers *err_handler; =20 - if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) + if (!is_cxl_mem_dev(dev) || !pcie_aer_is_native(dev)) return 0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:22:34.9993 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7e7421d-fcaf-4c64-11dc-08de5399e3d8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8375 Content-Type: text/plain; charset="utf-8" From: Dave Jiang Create new config CONFIG_CXL_RAS and put all CXL RAS items behind the config. The config will depend on CPER and PCIE AER to build. Move the related VH RAS code from core/pci.c to core/ras.c. Restricted CXL host (RCH) RAS functions will be moved in a future patch. Cc: Robert Richter Cc: Terry Bowman Reviewed-by: Joshua Hahn Reviewed-by: Jonathan Cameron Signed-off-by: Dave Jiang Reviewed-by: Alison Schofield Co-developed-by: Terry Bowman Reviewed-by: Dan Williams --- Changes in v13->v14: - None Changes in v12->v13: - None Changes in v11->v12: - None Changes in v10->v11: - New patch - Updated by Terry Bowman to use (ACPI_APEI_GHES && PCIEAER_CXL) dependency in Kconfig. Otherwise checks will be reauired for CONFIG_PCIEAER because AER driver functions are called. --- drivers/cxl/Kconfig | 4 + drivers/cxl/core/Makefile | 2 +- drivers/cxl/core/core.h | 31 +++++++ drivers/cxl/core/pci.c | 189 +------------------------------------- drivers/cxl/core/ras.c | 176 +++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 8 -- drivers/cxl/cxlpci.h | 16 ++++ tools/testing/cxl/Kbuild | 2 +- 8 files changed, 233 insertions(+), 195 deletions(-) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..217888992c88 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -233,4 +233,8 @@ config CXL_MCE def_bool y depends on X86_MCE && MEMORY_FAILURE =20 +config CXL_RAS + def_bool y + depends on ACPI_APEI_GHES && PCIEAER && CXL_PCI + endif diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index 5ad8fef210b5..b2930cc54f8b 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -14,9 +14,9 @@ cxl_core-y +=3D pci.o cxl_core-y +=3D hdm.o cxl_core-y +=3D pmu.o cxl_core-y +=3D cdat.o -cxl_core-y +=3D ras.o cxl_core-$(CONFIG_TRACING) +=3D trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D region.o cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o +cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 1fb66132b777..bc818de87ccc 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -144,8 +144,39 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct= access_coordinate *c); int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, struct access_coordinate *c); =20 +#ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); +bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base); +void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e); +#else +static inline int cxl_ras_init(void) +{ + return 0; +} + +static inline void cxl_ras_exit(void) +{ +} + +static inline bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iome= m *ras_base) +{ + return false; +} +static inline void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __= iomem *ras_base) { } +#endif /* CONFIG_CXL_RAS */ + +/* Restricted CXL Host specific RAS functions */ +#ifdef CONFIG_CXL_RAS +void cxl_dport_map_rch_aer(struct cxl_dport *dport); +void cxl_disable_rch_root_ints(struct cxl_dport *dport); +void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); +#else +static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } +static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } +static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } +#endif /* CONFIG_CXL_RAS */ + int cxl_gpf_port_setup(struct cxl_dport *dport); =20 struct cxl_hdm; diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 51bb0f372e40..e132fff80979 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -632,81 +632,8 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -static void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) -{ - void __iomem *addr; - u32 status; - - if (!ras_base) - return; - - addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; - status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); - } -} - -/* CXL spec rev3.0 8.2.4.16.1 */ -static void header_log_copy(void __iomem *ras_base, u32 *log) -{ - void __iomem *addr; - u32 *log_addr; - int i, log_u32_size =3D CXL_HEADERLOG_SIZE / sizeof(u32); - - addr =3D ras_base + CXL_RAS_HEADER_LOG_OFFSET; - log_addr =3D log; - - for (i =3D 0; i < log_u32_size; i++) { - *log_addr =3D readl(addr); - log_addr++; - addr +=3D sizeof(u32); - } -} - -/* - * Log the state of the RAS status registers and prepare them to log the - * next error status. Return 1 if reset needed. - */ -static bool cxl_handle_ras(struct cxl_dev_state *cxlds, - void __iomem *ras_base) -{ - u32 hl[CXL_HEADERLOG_SIZE_U32]; - void __iomem *addr; - u32 status; - u32 fe; - - if (!ras_base) - return false; - - addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; - status =3D readl(addr); - if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; - - /* If multiple errors, log header points to first error from ctrl reg */ - if (hweight32(status) > 1) { - void __iomem *rcc_addr =3D - ras_base + CXL_RAS_CAP_CONTROL_OFFSET; - - fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, - readl(rcc_addr))); - } else { - fe =3D status; - } - - header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); - writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); - - return true; -} - -#ifdef CONFIG_PCIEAER_CXL - -static void cxl_dport_map_rch_aer(struct cxl_dport *dport) +#ifdef CONFIG_CXL_RAS +void cxl_dport_map_rch_aer(struct cxl_dport *dport) { resource_size_t aer_phys; struct device *host; @@ -721,19 +648,7 @@ static void cxl_dport_map_rch_aer(struct cxl_dport *dp= ort) } } =20 -static void cxl_dport_map_ras(struct cxl_dport *dport) -{ - struct cxl_register_map *map =3D &dport->reg_map; - struct device *dev =3D dport->dport_dev; - - if (!map->component_map.ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) - dev_dbg(dev, "Failed to map RAS capability.\n"); -} - -static void cxl_disable_rch_root_ints(struct cxl_dport *dport) +void cxl_disable_rch_root_ints(struct cxl_dport *dport) { void __iomem *aer_base =3D dport->regs.dport_aer; u32 aer_cmd_mask, aer_cmd; @@ -757,28 +672,6 @@ static void cxl_disable_rch_root_ints(struct cxl_dport= *dport) writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } =20 -/** - * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport - * @dport: the cxl_dport that needs to be initialized - * @host: host device for devm operations - */ -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) -{ - dport->reg_map.host =3D host; - cxl_dport_map_ras(dport); - - if (dport->rch) { - struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); - - if (!host_bridge->native_aer) - return; - - cxl_dport_map_rch_aer(dport); - cxl_disable_rch_root_ints(dport); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); - /* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. Clear the @@ -827,7 +720,7 @@ static bool cxl_rch_get_aer_severity(struct aer_capabil= ity_regs *aer_regs, return false; } =20 -static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) +void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); struct aer_capability_regs aer_regs; @@ -852,82 +745,8 @@ static void cxl_handle_rdport_errors(struct cxl_dev_st= ate *cxlds) else cxl_handle_ras(cxlds, dport->regs.ras); } - -#else -static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { } #endif =20 -void cxl_cor_error_detected(struct pci_dev *pdev) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct device *dev =3D &cxlds->cxlmd->dev; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - - cxl_handle_cor_ras(cxlds, cxlds->regs.ras); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); - -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; - - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } - - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); - } - - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; -} -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); - static int cxl_flit_size(struct pci_dev *pdev) { if (cxl_pci_flit_256(pdev)) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 2731ba3a0799..b933030b8e1e 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "trace.h" =20 static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev, @@ -124,3 +125,178 @@ void cxl_ras_exit(void) cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); cancel_work_sync(&cxl_cper_prot_err_work); } + +static void cxl_dport_map_ras(struct cxl_dport *dport) +{ + struct cxl_register_map *map =3D &dport->reg_map; + struct device *dev =3D dport->dport_dev; + + if (!map->component_map.ras.valid) + dev_dbg(dev, "RAS registers not found\n"); + else if (cxl_map_component_regs(map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(dev, "Failed to map RAS capability.\n"); +} + +/** + * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport + * @dport: the cxl_dport that needs to be initialized + * @host: host device for devm operations + */ +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) +{ + dport->reg_map.host =3D host; + cxl_dport_map_ras(dport); + + if (dport->rch) { + struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); + + if (!host_bridge->native_aer) + return; + + cxl_dport_map_rch_aer(dport); + cxl_disable_rch_root_ints(dport); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); + +void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e) +{ + void __iomem *addr; + u32 status; + + if (!ras_base) + return; + + addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; + status =3D readl(addr); + if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + } +} + +/* CXL spec rev3.0 8.2.4.16.1 */ +static void header_log_copy(void __iomem *ras_base, u32 *log) +{ + void __iomem *addr; + u32 *log_addr; + int i, log_u32_size =3D CXL_HEADERLOG_SIZE / sizeof(u32); + + addr =3D ras_base + CXL_RAS_HEADER_LOG_OFFSET; + log_addr =3D log; + + for (i =3D 0; i < log_u32_size; i++) { + *log_addr =3D readl(addr); + log_addr++; + addr +=3D sizeof(u32); + } +} + +/* + * Log the state of the RAS status registers and prepare them to log the + * next error status. Return 1 if reset needed. + */ +bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) +{ + u32 hl[CXL_HEADERLOG_SIZE_U32]; + void __iomem *addr; + u32 status; + u32 fe; + + if (!ras_base) + return false; + + addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; + status =3D readl(addr); + if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) + return false; + + /* If multiple errors, log header points to first error from ctrl reg */ + if (hweight32(status) > 1) { + void __iomem *rcc_addr =3D + ras_base + CXL_RAS_CAP_CONTROL_OFFSET; + + fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, + readl(rcc_addr))); + } else { + fe =3D status; + } + + header_log_copy(ras_base, hl); + trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); + + return true; +} + +void cxl_cor_error_detected(struct pci_dev *pdev) +{ + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct device *dev =3D &cxlds->cxlmd->dev; + + scoped_guard(device, dev) { + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); + +pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; + struct device *dev =3D &cxlmd->dev; + bool ue; + + scoped_guard(device, dev) { + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_DISCONNECT; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + /* + * A frozen channel indicates an impending reset which is fatal to + * CXL.mem operation, and will likely crash the system. On the off + * chance the situation is recoverable dump the status of the RAS + * capability registers and bounce the active state of the memdev. + */ + ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); + } + + + switch (state) { + case pci_channel_io_normal: + if (ue) { + device_release_driver(dev); + return PCI_ERS_RESULT_NEED_RESET; + } + return PCI_ERS_RESULT_CAN_RECOVER; + case pci_channel_io_frozen: + dev_warn(&pdev->dev, + "%s: frozen state error detected, disable CXL.mem\n", + dev_name(dev)); + device_release_driver(dev); + return PCI_ERS_RESULT_NEED_RESET; + case pci_channel_io_perm_failure: + dev_warn(&pdev->dev, + "failure state error detected, request disconnect\n"); + return PCI_ERS_RESULT_DISCONNECT; + } + return PCI_ERS_RESULT_NEED_RESET; +} +EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ba17fa86d249..42a76a7a088f 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -803,14 +803,6 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_po= rt *port, struct device *dport_dev, int port_id, resource_size_t rcrb); =20 -#ifdef CONFIG_PCIEAER_CXL -void cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport); -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); -#else -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, - struct device *host) { } -#endif - struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); struct cxl_switch_decoder *to_cxl_switch_decoder(struct device *dev); diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index cdb7cf3dbcb4..6f9c78886fd9 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -76,7 +76,23 @@ static inline bool cxl_pci_flit_256(struct pci_dev *pdev) =20 struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); + +#ifdef CONFIG_CXL_RAS void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +#else +static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } + +static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + return PCI_ERS_RESULT_NONE; +} + +static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, + struct device *host) { } +#endif + #endif /* __CXL_PCI_H__ */ diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 0e151d0572d1..b7ea66382f3b 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -57,12 +57,12 @@ cxl_core-y +=3D $(CXL_CORE_SRC)/pci.o cxl_core-y +=3D $(CXL_CORE_SRC)/hdm.o cxl_core-y +=3D $(CXL_CORE_SRC)/pmu.o cxl_core-y +=3D $(CXL_CORE_SRC)/cdat.o -cxl_core-y +=3D $(CXL_CORE_SRC)/ras.o cxl_core-$(CONFIG_TRACING) +=3D $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) +=3D $(CXL_CORE_SRC)/region.o cxl_core-$(CONFIG_CXL_MCE) +=3D $(CXL_CORE_SRC)/mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D $(CXL_CORE_SRC)/features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D $(CXL_CORE_SRC)/edac.o +cxl_core-$(CONFIG_CXL_RAS) +=3D $(CXL_CORE_SRC)/ras.o cxl_core-y +=3D config_check.o cxl_core-y +=3D cxl_core_test.o cxl_core-y +=3D cxl_core_exports.o --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010042.outbound.protection.outlook.com [52.101.193.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C338335065; 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Wed, 14 Jan 2026 12:22:45 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 08/34] cxl/pci: Move CXL driver's RCH error handling into core/ras_rch.c Date: Wed, 14 Jan 2026 12:20:29 -0600 Message-ID: <20260114182055.46029-9-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|CH3PR12MB8712:EE_ X-MS-Office365-Filtering-Correlation-Id: e58a989e-f8ae-4020-1d18-08de5399ea93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:22:46.2933 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e58a989e-f8ae-4020-1d18-08de5399ea93 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8712 Content-Type: text/plain; charset="utf-8" Restricted CXL Host (RCH) protocol error handling uses a procedure distinct from the CXL Virtual Hierarchy (VH) handling. This is because of the differences in the RCH and VH topologies. Improve the maintainability and add ability to enable/disable RCH handling. Move and combine the RCH handling code into a single block conditionally compiled with the CONFIG_CXL_RCH_RAS kernel config. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Signed-off-by: Dan Williams Reviewed-by: Dave Jiang --- Changes in v13->v14: - Add sign-off for Dan and Jonathan - Revert inadvertent formatting of cxl_dport_map_rch_aer() (Jonathan) - Remove default value for CXL_RCH_RAS (Dan) - Remove unnecessary pci.h include in core.h & ras_rch.c (Jonathan) - Add linux/types.h include in ras_rch.c (Jonathan) - Change CONFIG_CXL_RCH_RAS -> CONFIG_CXL_RAS (Dan) Changes in v12->v13: - None Changes v11->v12: - Moved CXL_RCH_RAS Kconfig definition here from following commit. Changes v10->v11: - New patch --- drivers/cxl/core/Makefile | 1 + drivers/cxl/core/core.h | 11 +--- drivers/cxl/core/pci.c | 115 ----------------------------------- drivers/cxl/core/ras_rch.c | 121 +++++++++++++++++++++++++++++++++++++ tools/testing/cxl/Kbuild | 1 + 5 files changed, 126 insertions(+), 123 deletions(-) create mode 100644 drivers/cxl/core/ras_rch.c diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile index b2930cc54f8b..b37f38d502d8 100644 --- a/drivers/cxl/core/Makefile +++ b/drivers/cxl/core/Makefile @@ -20,3 +20,4 @@ cxl_core-$(CONFIG_CXL_MCE) +=3D mce.o cxl_core-$(CONFIG_CXL_FEATURES) +=3D features.o cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) +=3D edac.o cxl_core-$(CONFIG_CXL_RAS) +=3D ras.o +cxl_core-$(CONFIG_CXL_RAS) +=3D ras_rch.o diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index bc818de87ccc..724361195057 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -149,6 +149,9 @@ int cxl_ras_init(void); void cxl_ras_exit(void); bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base); void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e); +void cxl_dport_map_rch_aer(struct cxl_dport *dport); +void cxl_disable_rch_root_ints(struct cxl_dport *dport); +void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); #else static inline int cxl_ras_init(void) { @@ -164,14 +167,6 @@ static inline bool cxl_handle_ras(struct cxl_dev_state= *cxlds, void __iomem *ras return false; } static inline void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __= iomem *ras_base) { } -#endif /* CONFIG_CXL_RAS */ - -/* Restricted CXL Host specific RAS functions */ -#ifdef CONFIG_CXL_RAS -void cxl_dport_map_rch_aer(struct cxl_dport *dport); -void cxl_disable_rch_root_ints(struct cxl_dport *dport); -void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); -#else static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index e132fff80979..b838c59d7a3c 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -632,121 +632,6 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL"); =20 -#ifdef CONFIG_CXL_RAS -void cxl_dport_map_rch_aer(struct cxl_dport *dport) -{ - resource_size_t aer_phys; - struct device *host; - u16 aer_cap; - - aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); - if (aer_cap) { - host =3D dport->reg_map.host; - aer_phys =3D aer_cap + dport->rcrb.base; - dport->regs.dport_aer =3D devm_cxl_iomap_block(host, aer_phys, - sizeof(struct aer_capability_regs)); - } -} - -void cxl_disable_rch_root_ints(struct cxl_dport *dport) -{ - void __iomem *aer_base =3D dport->regs.dport_aer; - u32 aer_cmd_mask, aer_cmd; - - if (!aer_base) - return; - - /* - * Disable RCH root port command interrupts. - * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors - * - * This sequence may not be necessary. CXL spec states disabling - * the root cmd register's interrupts is required. But, PCI spec - * shows these are disabled by default on reset. - */ - aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | - PCI_ERR_ROOT_CMD_NONFATAL_EN | - PCI_ERR_ROOT_CMD_FATAL_EN); - aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); - aer_cmd &=3D ~aer_cmd_mask; - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); -} - -/* - * Copy the AER capability registers using 32 bit read accesses. - * This is necessary because RCRB AER capability is MMIO mapped. Clear the - * status after copying. - * - * @aer_base: base address of AER capability block in RCRB - * @aer_regs: destination for copying AER capability - */ -static bool cxl_rch_get_aer_info(void __iomem *aer_base, - struct aer_capability_regs *aer_regs) -{ - int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); - u32 *aer_regs_buf =3D (u32 *)aer_regs; - int n; - - if (!aer_base) - return false; - - /* Use readl() to guarantee 32-bit accesses */ - for (n =3D 0; n < read_cnt; n++) - aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); - - writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); - writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); - - return true; -} - -/* Get AER severity. Return false if there is no error. */ -static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, - int *severity) -{ - if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) - *severity =3D AER_FATAL; - else - *severity =3D AER_NONFATAL; - return true; - } - - if (aer_regs->cor_status & ~aer_regs->cor_mask) { - *severity =3D AER_CORRECTABLE; - return true; - } - - return false; -} - -void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) -{ - struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); - struct aer_capability_regs aer_regs; - struct cxl_dport *dport; - int severity; - - struct cxl_port *port __free(put_cxl_port) =3D - cxl_pci_find_port(pdev, &dport); - if (!port) - return; - - if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) - return; - - if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) - return; - - pci_print_aer(pdev, severity, &aer_regs); - - if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(cxlds, dport->regs.ras); - else - cxl_handle_ras(cxlds, dport->regs.ras); -} -#endif - static int cxl_flit_size(struct pci_dev *pdev) { if (cxl_pci_flit_256(pdev)) diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c new file mode 100644 index 000000000000..ed58afd18ecc --- /dev/null +++ b/drivers/cxl/core/ras_rch.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include "cxl.h" +#include "core.h" +#include "cxlmem.h" + +void cxl_dport_map_rch_aer(struct cxl_dport *dport) +{ + resource_size_t aer_phys; + struct device *host; + u16 aer_cap; + + aer_cap =3D cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base); + if (aer_cap) { + host =3D dport->reg_map.host; + aer_phys =3D aer_cap + dport->rcrb.base; + dport->regs.dport_aer =3D + devm_cxl_iomap_block(host, aer_phys, + sizeof(struct aer_capability_regs)); + } +} + +void cxl_disable_rch_root_ints(struct cxl_dport *dport) +{ + void __iomem *aer_base =3D dport->regs.dport_aer; + u32 aer_cmd_mask, aer_cmd; + + if (!aer_base) + return; + + /* + * Disable RCH root port command interrupts. + * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors + * + * This sequence may not be necessary. CXL spec states disabling + * the root cmd register's interrupts is required. But, PCI spec + * shows these are disabled by default on reset. + */ + aer_cmd_mask =3D (PCI_ERR_ROOT_CMD_COR_EN | + PCI_ERR_ROOT_CMD_NONFATAL_EN | + PCI_ERR_ROOT_CMD_FATAL_EN); + aer_cmd =3D readl(aer_base + PCI_ERR_ROOT_COMMAND); + aer_cmd &=3D ~aer_cmd_mask; + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); +} + +/* + * Copy the AER capability registers using 32 bit read accesses. + * This is necessary because RCRB AER capability is MMIO mapped. Clear the + * status after copying. + * + * @aer_base: base address of AER capability block in RCRB + * @aer_regs: destination for copying AER capability + */ +static bool cxl_rch_get_aer_info(void __iomem *aer_base, + struct aer_capability_regs *aer_regs) +{ + int read_cnt =3D sizeof(struct aer_capability_regs) / sizeof(u32); + u32 *aer_regs_buf =3D (u32 *)aer_regs; + int n; + + if (!aer_base) + return false; + + /* Use readl() to guarantee 32-bit accesses */ + for (n =3D 0; n < read_cnt; n++) + aer_regs_buf[n] =3D readl(aer_base + n * sizeof(u32)); + + writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); + writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); + + return true; +} + +/* Get AER severity. Return false if there is no error. */ +static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, + int *severity) +{ + if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { + if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) + *severity =3D AER_FATAL; + else + *severity =3D AER_NONFATAL; + return true; + } + + if (aer_regs->cor_status & ~aer_regs->cor_mask) { + *severity =3D AER_CORRECTABLE; + return true; + } + + return false; +} + +void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) +{ + struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); + struct aer_capability_regs aer_regs; + struct cxl_dport *dport; + int severity; + + struct cxl_port *port __free(put_cxl_port) =3D + cxl_pci_find_port(pdev, &dport); + if (!port) + return; + + if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) + return; + + if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) + return; + + pci_print_aer(pdev, severity, &aer_regs); + if (severity =3D=3D AER_CORRECTABLE) + cxl_handle_cor_ras(cxlds, dport->regs.ras); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:22:58.3571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf67362b-3d66-49fc-18e3-08de5399f1c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6245 Content-Type: text/plain; charset="utf-8" Internal PCIe errors are not enabled by default during initialization. This creates a problem for CXL drivers, which rely on PCIe Correctable and Uncorrectable Internal Errors to receive CXL protocol error notifications. Export pci_aer_unmask_internal_errors() so CXL and other drivers can enable internal PCIe errors. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan --- Changes in v13->v14: - New commit. Bjorn requested separating out and adding immediatetly before being used. This is called from cxl_rch_enable_rcec() in following patch. --- drivers/pci/pcie/aer.c | 6 +++--- include/linux/aer.h | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index c99ba2a1159c..63658e691aa2 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1120,8 +1120,6 @@ static bool find_source_device(struct pci_dev *parent, return true; } =20 -#ifdef CONFIG_PCIEAER_CXL - /** * pci_aer_unmask_internal_errors - unmask internal errors * @dev: pointer to the pci_dev data structure @@ -1132,7 +1130,7 @@ static bool find_source_device(struct pci_dev *parent, * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer =3D dev->aer_cap; u32 mask; @@ -1145,7 +1143,9 @@ static void pci_aer_unmask_internal_errors(struct pci= _dev *dev) mask &=3D ~PCI_ERR_COR_INTERNAL; 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Wed, 14 Jan 2026 12:23:12 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 10/34] PCI/AER: Update is_internal_error() to be non-static is_aer_internal_error() Date: Wed, 14 Jan 2026 12:20:31 -0600 Message-ID: <20260114182055.46029-11-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|SJ2PR12MB8873:EE_ X-MS-Office365-Filtering-Correlation-Id: 4b0dd86b-37c0-4470-aeef-08de5399fba1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|7416014|82310400026|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:23:14.9098 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4b0dd86b-37c0-4470-aeef-08de5399fba1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8873 Content-Type: text/plain; charset="utf-8" The AER driver includes significant logic for handling CXL protocol errors. The AER driver will be updated in the future to separate the AER and CXL logic. Rename the is_internal_error() function to is_aer_internal_error() as it gives a more precise indication of the purpose. Make is_aer_internal_error() non-static to allow for other PCI drivers to access. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas --- Changes in v13->v14: - New patch --- drivers/pci/pcie/aer.c | 4 ++-- drivers/pci/pcie/portdrv.h | 9 +++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 63658e691aa2..2527e8370186 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1166,7 +1166,7 @@ static bool is_cxl_mem_dev(struct pci_dev *dev) return true; } =20 -static bool is_internal_error(struct aer_err_info *info) +bool is_aer_internal_error(struct aer_err_info *info) { if (info->severity =3D=3D AER_CORRECTABLE) return info->status & PCI_ERR_COR_INTERNAL; @@ -1211,7 +1211,7 @@ static void cxl_rch_handle_error(struct pci_dev *dev,= struct aer_err_info *info) * device driver. */ if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_internal_error(info)) + is_aer_internal_error(info)) pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); } =20 diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index bd29d1cc7b8b..e7a0a2cffea9 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -123,4 +123,13 @@ static inline void pcie_pme_interrupt_enable(struct pc= i_dev *dev, bool en) {} #endif /* !CONFIG_PCIE_PME */ =20 struct device *pcie_port_find_device(struct pci_dev *dev, u32 service); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:23:29.7889 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 221bda68-1e83-453f-7ed4-08de539a0480 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9414 Content-Type: text/plain; charset="utf-8" The Restricted CXL Host (RCH) AER error handling logic currently resides in the AER driver file, aer.c. CXL specific changes conditionally compiled using #ifdefs. Improve the AER driver maintainability by separating the RCH specific logic from the AER driver's core functionality and removing the ifdefs. Introduce drivers/pci/pcie/aer_cxl_rch.c for moving the RCH AER logic into. Condition= ally compile the file using the CONFIG_CXL_RCH_RAS Kconfig. Move the CXL logic into the new file but leave CXL helper function is_internal_error() in aer.c for now as it will be moved in future patch for CXL Virtual Hierarchy handling. To maintain compilation after the move other changes are required. Change cxl_rch_handle_error(), cxl_rch_enable_rcec(), and is_internal_error() to be non-static inorder for accessing from the AER driver. Update the new file with the SPDX and 2023 AMD copyright notations because the RCH bits were initially contributed in 2023 by AMD. See commit: commit 0a867568bb0d ("PCI/AER: Forward RCH downstream port-detected errors = to the CXL.mem dev handler") Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams Acked-by: Bjorn Helgaas --- Changes in v13->v14: - Add review-by and signed-off for Dan - Commit message fixup (Dan) - Update commit message with use-case description (Dan, Lukas) - Make cxl_error_is_native() static (Dan) Changes in v12->v13: - Add forward declararation of 'struct aer_err_info' in pci/pci.h (Terry) - Changed copyright date from 2025 to 2023 (Jonathan) - Add David Jiang's, Jonathan's, and Ben's review-by - Re-add 'struct aer_err_info' (Bot) Changes in v11->v12: - Rename drivers/pci/pcie/cxl_rch.c to drivers/pci/pcie/aer_cxl_rch.c (Luka= s) - Removed forward declararation of 'struct aer_err_info' in pci/pci.h (Terr= y) Changes in v10->v11: - Remove changes in code-split and move to earlier, new patch - Add #include to cxl_ras.c - Move cxl_rch_handle_error() & cxl_rch_enable_rcec() declarations from pci= .h to aer.h, more localized. - Introduce CONFIG_CXL_RCH_RAS, includes Makefile changes, ras.c ifdef changes --- drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 99 +----------------------------- drivers/pci/pcie/aer_cxl_rch.c | 106 +++++++++++++++++++++++++++++++++ drivers/pci/pcie/portdrv.h | 9 ++- 4 files changed, 114 insertions(+), 101 deletions(-) create mode 100644 drivers/pci/pcie/aer_cxl_rch.c diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index 173829aa02e6..b0b43a18c304 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o =20 obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o +obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_rch.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 2527e8370186..b1e6ee7468b9 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1145,27 +1145,7 @@ void pci_aer_unmask_internal_errors(struct pci_dev *= dev) } EXPORT_SYMBOL_GPL(pci_aer_unmask_internal_errors); =20 -#ifdef CONFIG_PCIEAER_CXL -static bool is_cxl_mem_dev(struct pci_dev *dev) -{ - /* - * The capability, status, and control fields in Device 0, - * Function 0 DVSEC control the CXL functionality of the - * entire device (CXL 3.0, 8.1.3). - */ - if (dev->devfn !=3D PCI_DEVFN(0, 0)) - return false; - - /* - * CXL Memory Devices must have the 502h class code set (CXL - * 3.0, 8.1.12.1). - */ - if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) - return false; - - return true; -} - +#ifdef CONFIG_CXL_RAS bool is_aer_internal_error(struct aer_err_info *info) { if (info->severity =3D=3D AER_CORRECTABLE) @@ -1173,83 +1153,6 @@ bool is_aer_internal_error(struct aer_err_info *info) =20 return info->status & PCI_ERR_UNC_INTN; } - -static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) -{ - struct aer_err_info *info =3D (struct aer_err_info *)data; - const struct pci_error_handlers *err_handler; - - if (!is_cxl_mem_dev(dev) || !pcie_aer_is_native(dev)) - return 0; - - /* Protect dev->driver */ - device_lock(&dev->dev); - - err_handler =3D dev->driver ? dev->driver->err_handler : NULL; - if (!err_handler) - goto out; - - if (info->severity =3D=3D AER_CORRECTABLE) { - if (err_handler->cor_error_detected) - err_handler->cor_error_detected(dev); - } else if (err_handler->error_detected) { - if (info->severity =3D=3D AER_NONFATAL) - err_handler->error_detected(dev, pci_channel_io_normal); - else if (info->severity =3D=3D AER_FATAL) - err_handler->error_detected(dev, pci_channel_io_frozen); - } -out: - device_unlock(&dev->dev); - return 0; -} - -static void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info = *info) -{ - /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. - */ - if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && - is_aer_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); -} - -static int handles_cxl_error_iter(struct pci_dev *dev, void *data) -{ - bool *handles_cxl =3D data; - - if (!*handles_cxl) - *handles_cxl =3D is_cxl_mem_dev(dev) && pcie_aer_is_native(dev); - - /* Non-zero terminates iteration */ - return *handles_cxl; -} - -static bool handles_cxl_errors(struct pci_dev *rcec) -{ - bool handles_cxl =3D false; - - if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && - pcie_aer_is_native(rcec)) - pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); - - return handles_cxl; -} - -static void cxl_rch_enable_rcec(struct pci_dev *rcec) -{ - if (!handles_cxl_errors(rcec)) - return; - - pci_aer_unmask_internal_errors(rcec); - pci_info(rcec, "CXL: Internal errors unmasked"); -} - -#else -static inline void cxl_rch_enable_rcec(struct pci_dev *dev) { } -static inline void cxl_rch_handle_error(struct pci_dev *dev, - struct aer_err_info *info) { } #endif =20 /** diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c new file mode 100644 index 000000000000..6b515edb12c1 --- /dev/null +++ b/drivers/pci/pcie/aer_cxl_rch.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2023 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include "../pci.h" +#include "portdrv.h" + +static bool is_cxl_mem_dev(struct pci_dev *dev) +{ + /* + * The capability, status, and control fields in Device 0, + * Function 0 DVSEC control the CXL functionality of the + * entire device (CXL 3.0, 8.1.3). + */ + if (dev->devfn !=3D PCI_DEVFN(0, 0)) + return false; + + /* + * CXL Memory Devices must have the 502h class code set (CXL + * 3.0, 8.1.12.1). + */ + if ((dev->class >> 8) !=3D PCI_CLASS_MEMORY_CXL) + return false; + + return true; +} + +static bool cxl_error_is_native(struct pci_dev *dev) +{ + struct pci_host_bridge *host =3D pci_find_host_bridge(dev->bus); + + return (pcie_ports_native || host->native_aer); +} + +static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) +{ + struct aer_err_info *info =3D (struct aer_err_info *)data; + const struct pci_error_handlers *err_handler; + + if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) + return 0; + + device_lock(&dev->dev); + + err_handler =3D dev->driver ? dev->driver->err_handler : NULL; + if (!err_handler) + goto out; + + if (info->severity =3D=3D AER_CORRECTABLE) { + if (err_handler->cor_error_detected) + err_handler->cor_error_detected(dev); + } else if (err_handler->error_detected) { + if (info->severity =3D=3D AER_NONFATAL) + err_handler->error_detected(dev, pci_channel_io_normal); + else if (info->severity =3D=3D AER_FATAL) + err_handler->error_detected(dev, pci_channel_io_frozen); + } +out: + device_unlock(&dev->dev); + return 0; +} + +void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +{ + /* + * Internal errors of an RCEC indicate an AER error in an + * RCH's downstream port. Check and handle them in the CXL.mem + * device driver. + */ + if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && + is_aer_internal_error(info)) + pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); +} + +static int handles_cxl_error_iter(struct pci_dev *dev, void *data) +{ + bool *handles_cxl =3D data; + + if (!*handles_cxl) + *handles_cxl =3D is_cxl_mem_dev(dev) && cxl_error_is_native(dev); + + /* Non-zero terminates iteration */ + return *handles_cxl; +} + +static bool handles_cxl_errors(struct pci_dev *rcec) +{ + bool handles_cxl =3D false; + + if (pci_pcie_type(rcec) =3D=3D PCI_EXP_TYPE_RC_EC && + pcie_aer_is_native(rcec)) + pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + + return handles_cxl; +} + +void cxl_rch_enable_rcec(struct pci_dev *rcec) +{ + if (!handles_cxl_errors(rcec)) + return; + + pci_aer_unmask_internal_errors(rcec); + pci_info(rcec, "CXL: Internal errors unmasked"); +} diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index e7a0a2cffea9..cc58bf2f2c84 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -126,10 +126,13 @@ struct device *pcie_port_find_device(struct pci_dev *= dev, u32 service); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:23:40.5921 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7dc7a811-dffa-432b-ad47-08de539a0af0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9548 Content-Type: text/plain; charset="utf-8" cxl_rch_handle_error_iter() includes a call to device_lock() using a goto for multiple return paths. Improve readability and maintainability by using the guard() lock variant. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang Reviewed-by: Dan Williams Acked-by: Bjorn Helgaas --- Changes in v13 -> v14: - Add review-by for Jonathan, Dave Jiang, Dan WIlliams, and Bjorn - Remove cleanup.h (Jonathan) - Reverted comment removal (Bjorn) - Move this patch after pci/pcie/aer_cxl_rch.c creation (Bjorn) Changes in v12 -> v13: - New patch --- drivers/pci/pcie/aer_cxl_rch.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c index 6b515edb12c1..e471eefec9c4 100644 --- a/drivers/pci/pcie/aer_cxl_rch.c +++ b/drivers/pci/pcie/aer_cxl_rch.c @@ -42,11 +42,11 @@ static int cxl_rch_handle_error_iter(struct pci_dev *de= v, void *data) if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) return 0; =20 - device_lock(&dev->dev); + guard(device)(&dev->dev); =20 err_handler =3D dev->driver ? dev->driver->err_handler : NULL; if (!err_handler) - goto out; + return 0; =20 if (info->severity =3D=3D AER_CORRECTABLE) { if (err_handler->cor_error_detected) @@ -57,8 +57,6 @@ static int cxl_rch_handle_error_iter(struct pci_dev *dev,= void *data) else if (info->severity =3D=3D AER_FATAL) err_handler->error_detected(dev, pci_channel_io_frozen); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:23:51.7506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4e3a4c8-8ade-4b02-2891-08de539a1197 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9660 Content-Type: text/plain; charset="utf-8" From: Dan Williams One of the primary reasons for the CXL driver to exist is to perform error handling. If both PCIEAER and CXL are enabled then light up CXL error handling as well. The work to remove CONFIG_PCIEAER_CXL started in: commit 4ae6ae66649c ("cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL= conditional blocks from core/pci.c") Finish that off with conditionally compiling all CXL RAS related helpers with CONFIG_CXL_RAS. Signed-off-by: Dan Williams Reviewed-by: Terry Bowman Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron ---- Changes in v13->v14: - New commit --- drivers/cxl/Kconfig | 2 +- drivers/pci/pcie/Kconfig | 9 --------- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 217888992c88..70acddc08c39 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -235,6 +235,6 @@ config CXL_MCE =20 config CXL_RAS def_bool y - depends on ACPI_APEI_GHES && PCIEAER && CXL_PCI + depends on ACPI_APEI_GHES && PCIEAER && CXL_BUS =20 endif diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 17919b99fa66..207c2deae35f 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -49,15 +49,6 @@ config PCIEAER_INJECT gotten from: https://github.com/intel/aer-inject.git =20 -config PCIEAER_CXL - bool "PCI Express CXL RAS support" - default y - depends on PCIEAER && CXL_PCI - help - Enables CXL error handling. - - If unsure, say Y. - # # PCI Express ECRC # --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010042.outbound.protection.outlook.com [52.101.193.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E53432FFF8F; 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Wed, 14 Jan 2026 12:24:01 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 14/34] PCI/AER: Report CXL or PCIe bus type in AER trace logging Date: Wed, 14 Jan 2026 12:20:35 -0600 Message-ID: <20260114182055.46029-15-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|SJ2PR12MB9088:EE_ X-MS-Office365-Filtering-Correlation-Id: ac4b87a8-13b1-4113-ce23-08de539a18ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:24:04.0369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac4b87a8-13b1-4113-ce23-08de539a18ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9088 Content-Type: text/plain; charset="utf-8" The AER service driver and aer_event tracing currently log 'PCIe Bus Type' for all errors. Update the driver and aer_event tracing to log 'CXL Bus Type' for CXL device errors. This requires that AER can identify and distinguish between PCIe errors and CXL errors. Introduce boolean 'is_cxl' to 'struct aer_err_info'. Add assignment in aer_get_device_error_info() and pci_print_aer(). Update the aer_event trace routine to accept a bus type string parameter. Signed-off-by: Terry Bowman Co-developed-by: Dan Williams Signed-off-by: Dan Williams Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13->v14: - Merged with Dan's commit. Changes are moving bus_type the last parameter in function calls (Dan) - Removed all DCOs because of changes (Terry) - Update commit message (Bjorn) - Add Bjorn's ack-by Changes in v12->v13: - Remove duplicated aer_err_info inline comments. Is already in the kernel-doc header (Ben) Changes in v11->v12: - Change aer_err_info::is_cxl to be bool a bitfield. Update structure padding. (Lukas) - Add kernel-doc for 'struct aer_err_info' (Lukas) Changes in v10->v11: - Remove duplicate call to trace_aer_event() (Shiju) - Added Dan William's and Dave Jiang's reviewed-by --- drivers/pci/pci.h | 8 +++++++- drivers/pci/pcie/aer.c | 20 +++++++++++++------- include/ras/ras_event.h | 12 ++++++++---- 3 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 0e67014aa001..41ec38e82c08 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -738,7 +738,8 @@ struct aer_err_info { unsigned int multi_error_valid:1; =20 unsigned int first_error:5; - unsigned int __pad2:2; + unsigned int __pad2:1; + unsigned int is_cxl:1; unsigned int tlp_header_valid:1; =20 unsigned int status; /* COR/UNCOR Error Status */ @@ -749,6 +750,11 @@ struct aer_err_info { int aer_get_device_error_info(struct aer_err_info *info, int i); void aer_print_error(struct aer_err_info *info, int i); =20 +static inline const char *aer_err_bus(struct aer_err_info *info) +{ + return info->is_cxl ? "CXL" : "PCIe"; +} + int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, unsigned int tlp_len, bool flit, struct pcie_tlp_log *log); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index b1e6ee7468b9..d30a217fae46 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -870,6 +870,7 @@ void aer_print_error(struct aer_err_info *info, int i) struct pci_dev *dev; int layer, agent, id; const char *level =3D info->level; + const char *bus_type =3D aer_err_bus(info); =20 if (WARN_ON_ONCE(i >=3D AER_MAX_MULTI_ERR_DEVICES)) return; @@ -879,22 +880,22 @@ void aer_print_error(struct aer_err_info *info, int i) =20 pci_dev_aer_stats_incr(dev, info); trace_aer_event(pci_name(dev), (info->status & ~info->mask), - info->severity, info->tlp_header_valid, &info->tlp); + info->severity, info->tlp_header_valid, &info->tlp, bus_type); =20 if (!info->ratelimit_print[i]) return; =20 if (!info->status) { - pci_err(dev, "PCIe Bus Error: severity=3D%s, type=3DInaccessible, (Unreg= istered Agent ID)\n", - aer_error_severity_string[info->severity]); + pci_err(dev, "%s Bus Error: severity=3D%s, type=3DInaccessible, (Unregis= tered Agent ID)\n", + bus_type, aer_error_severity_string[info->severity]); goto out; } =20 layer =3D AER_GET_LAYER_ERROR(info->severity, info->status); agent =3D AER_GET_AGENT(info->severity, info->status); =20 - aer_printk(level, dev, "PCIe Bus Error: severity=3D%s, type=3D%s, (%s)\n", - aer_error_severity_string[info->severity], + aer_printk(level, dev, "%s Bus Error: severity=3D%s, type=3D%s, (%s)\n", + bus_type, aer_error_severity_string[info->severity], aer_error_layer[layer], aer_agent_string[agent]); =20 aer_printk(level, dev, " device [%04x:%04x] error status/mask=3D%08x/%08= x\n", @@ -928,6 +929,7 @@ EXPORT_SYMBOL_GPL(cper_severity_to_aer); void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer) { + const char *bus_type; int layer, agent, tlp_header_valid =3D 0; u32 status, mask; struct aer_err_info info =3D { @@ -948,10 +950,13 @@ void pci_print_aer(struct pci_dev *dev, int aer_sever= ity, =20 info.status =3D status; info.mask =3D mask; + info.is_cxl =3D pcie_is_cxl(dev); + + bus_type =3D aer_err_bus(&info); =20 pci_dev_aer_stats_incr(dev, &info); - trace_aer_event(pci_name(dev), (status & ~mask), - aer_severity, tlp_header_valid, &aer->header_log); + trace_aer_event(pci_name(dev), (status & ~mask), aer_severity, + tlp_header_valid, &aer->header_log, bus_type); =20 if (!aer_ratelimit(dev, info.severity)) return; @@ -1301,6 +1306,7 @@ int aer_get_device_error_info(struct aer_err_info *in= fo, int i) /* Must reset in this function */ info->status =3D 0; info->tlp_header_valid =3D 0; + info->is_cxl =3D pcie_is_cxl(dev); =20 /* The device might not support AER */ if (!aer) diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index eaecc3c5f772..fdb785fa4613 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -339,9 +339,11 @@ TRACE_EVENT(aer_event, const u32 status, const u8 severity, const u8 tlp_header_valid, - struct pcie_tlp_log *tlp), + struct pcie_tlp_log *tlp, + const char *bus_type), =20 - TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp), + + TP_ARGS(dev_name, status, severity, tlp_header_valid, tlp, bus_type), =20 TP_STRUCT__entry( __string( dev_name, dev_name ) @@ -349,10 +351,12 @@ TRACE_EVENT(aer_event, __field( u8, severity ) __field( u8, tlp_header_valid) __array( u32, tlp_header, PCIE_STD_MAX_TLP_HEADERLOG) + __string( bus_type, bus_type ) ), =20 TP_fast_assign( __assign_str(dev_name); + __assign_str(bus_type); __entry->status =3D status; __entry->severity =3D severity; __entry->tlp_header_valid =3D tlp_header_valid; @@ -364,8 +368,8 @@ TRACE_EVENT(aer_event, } ), =20 - TP_printk("%s PCIe Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", - __get_str(dev_name), + TP_printk("%s %s Bus Error: severity=3D%s, %s, TLP Header=3D%s\n", + __get_str(dev_name), __get_str(bus_type), __entry->severity =3D=3D AER_CORRECTABLE ? "Corrected" : __entry->severity =3D=3D AER_FATAL ? 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:24:18.8525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5efd0c5e-6211-4e48-7ca6-08de539a21be X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6987 Content-Type: text/plain; charset="utf-8" Update the existing 'struct aer_err_info' definition to use kernel-doc formatting. Remove the inline comments to reduce noise and do not introduce functional changes. This will improve readability and maintainability. Signed-off-by: Terry Bowman Reviewed-by: Dan Williams Acked-by: Bjorn Helgaas Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13->v14: - New commit --- drivers/pci/pci.h | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 41ec38e82c08..dbc547db208a 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -724,16 +724,33 @@ static inline bool pci_dev_binding_disallowed(struct = pci_dev *dev) =20 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ =20 +/** + * struct aer_err_info - AER Error Information + * @dev: Devices reporting error + * @ratelimit_print: Flag to log or not log the devices' error. 0=3DNotLog= /1=3DLog + * @error_dev_num: Number of devices reporting an error + * @level: printk level to use in logging + * @id: Value from register PCI_ERR_ROOT_ERR_SRC + * @severity: AER severity, 0-UNCOR Non-fatal, 1-UNCOR fatal, 2-COR + * @root_ratelimit_print: Flag to log or not log the root's error. 0=3DNot= Log/1=3DLog + * @multi_error_valid: If multiple errors are reported + * @first_error: First reported error + * @is_cxl: Bus type error: 0-PCI Bus error, 1-CXL Bus error + * @tlp_header_valid: Indicates if TLP field contains error information + * @status: COR/UNCOR error status + * @mask: COR/UNCOR mask + * @tlp: Transaction packet information + */ struct aer_err_info { struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:24:34.9497 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8ad2de5f-3b2b-49b7-e16c-08de539a2b56 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5969 Content-Type: text/plain; charset="utf-8" From: Dan Williams The convention for devm_ helpers in the CXL driver is that the first argument is the @host for the operation (locked driver::probe() context). Signed-off-by: Dan Williams Reviewed-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13 -> v14: - New patch --- drivers/cxl/core/pmem.c | 13 +++++++------ drivers/cxl/cxl.h | 3 ++- drivers/cxl/mem.c | 2 +- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c index 8853415c106a..e7b1e6fa0ea0 100644 --- a/drivers/cxl/core/pmem.c +++ b/drivers/cxl/core/pmem.c @@ -237,12 +237,13 @@ static void cxlmd_release_nvdimm(void *_cxlmd) =20 /** * devm_cxl_add_nvdimm() - add a bridge between a cxl_memdev and an nvdimm - * @parent_port: parent port for the (to be added) @cxlmd endpoint port - * @cxlmd: cxl_memdev instance that will perform LIBNVDIMM operations + * @host: host device for devm operations + * @port: any port in the CXL topology to find the nvdimm-bridge device + * @cxlmd: parent of the to be created cxl_nvdimm device * * Return: 0 on success negative error code on failure. */ -int devm_cxl_add_nvdimm(struct cxl_port *parent_port, +int devm_cxl_add_nvdimm(struct device *host, struct cxl_port *port, struct cxl_memdev *cxlmd) { struct cxl_nvdimm_bridge *cxl_nvb; @@ -250,7 +251,7 @@ int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct device *dev; int rc; =20 - cxl_nvb =3D cxl_find_nvdimm_bridge(parent_port); + cxl_nvb =3D cxl_find_nvdimm_bridge(port); if (!cxl_nvb) return -ENODEV; =20 @@ -270,10 +271,10 @@ int devm_cxl_add_nvdimm(struct cxl_port *parent_port, if (rc) goto err; =20 - dev_dbg(&cxlmd->dev, "register %s\n", dev_name(dev)); + dev_dbg(host, "register %s\n", dev_name(dev)); =20 /* @cxlmd carries a reference on @cxl_nvb until cxlmd_release_nvdimm */ - return devm_add_action_or_reset(&cxlmd->dev, cxlmd_release_nvdimm, cxlmd); + return devm_add_action_or_reset(host, cxlmd_release_nvdimm, cxlmd); =20 err: put_device(dev); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 42a76a7a088f..6f3741a57932 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -887,7 +887,8 @@ struct cxl_nvdimm_bridge *devm_cxl_add_nvdimm_bridge(st= ruct device *host, struct cxl_port *port); struct cxl_nvdimm *to_cxl_nvdimm(struct device *dev); bool is_cxl_nvdimm(struct device *dev); -int devm_cxl_add_nvdimm(struct cxl_port *parent_port, struct cxl_memdev *c= xlmd); +int devm_cxl_add_nvdimm(struct device *host, struct cxl_port *port, + struct cxl_memdev *cxlmd); struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_port *port); =20 #ifdef CONFIG_CXL_REGION diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 6e6777b7bafb..c2ee7f7f6320 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -153,7 +153,7 @@ static int cxl_mem_probe(struct device *dev) } =20 if (cxl_pmem_size(cxlds) && IS_ENABLED(CONFIG_CXL_PMEM)) { - rc =3D devm_cxl_add_nvdimm(parent_port, cxlmd); + rc =3D devm_cxl_add_nvdimm(dev, parent_port, cxlmd); if (rc) { if (rc =3D=3D -ENODEV) dev_info(dev, "PMEM disabled by platform\n"); --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from CO1PR03CU002.outbound.protection.outlook.com (mail-westus2azon11010045.outbound.protection.outlook.com [52.101.46.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC5898632A; 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Wed, 14 Jan 2026 12:24:44 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 17/34] cxl: Update RAS handler interfaces to also support CXL Ports Date: Wed, 14 Jan 2026 12:20:38 -0600 Message-ID: <20260114182055.46029-18-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CF:EE_|IA1PR12MB8519:EE_ X-MS-Office365-Filtering-Correlation-Id: e6ea3fcf-ccb3-49a9-c8fc-08de539a31ed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|7416014|1800799024|30052699003|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:24:46.0045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6ea3fcf-ccb3-49a9-c8fc-08de539a31ed X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8519 Content-Type: text/plain; charset="utf-8" CXL PCIe Port Protocol Error handling support will be added to the CXL drivers in the future. In preparation, rename the existing interfaces to support handling all CXL PCIe Port Protocol Errors. The driver's RAS support functions currently rely on a 'struct cxl_dev_state' type parameter, which is not available for CXL Port devices. However, since the same CXL RAS capability structure is needed across most CXL components and devices, a common handling approach should be adopted. To accommodate this, update the __cxl_handle_cor_ras() and __cxl_handle_ras() functions to use a `struct device` instead of `struct cxl_dev_state`. No functional changes are introduced. [1] CXL 3.1 Spec, 8.2.4 CXL.cache and CXL.mem Registers Signed-off-by: Terry Bowman Reviewed-by: Alejandro Lucero Reviewed-by: Ira Weiny Reviewed-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams --- Changes in v13->v14: - None --- drivers/cxl/core/core.h | 14 +++++--------- drivers/cxl/core/ras.c | 12 ++++++------ drivers/cxl/core/ras_rch.c | 4 ++-- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 724361195057..422531799af2 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -147,8 +147,8 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port= *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base); -void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e); +bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); +void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); @@ -157,16 +157,12 @@ static inline int cxl_ras_init(void) { return 0; } - -static inline void cxl_ras_exit(void) -{ -} - -static inline bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iome= m *ras_base) +static inline void cxl_ras_exit(void) { } +static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) { return false; } -static inline void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __= iomem *ras_base) { } +static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index b933030b8e1e..72908f3ced77 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -160,7 +160,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt, struct device *host) } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 -void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, void __iomem *ras_bas= e) +void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { void __iomem *addr; u32 status; @@ -172,7 +172,7 @@ void cxl_handle_cor_ras(struct cxl_dev_state *cxlds, vo= id __iomem *ras_base) status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(cxlds->cxlmd, status); + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); } } =20 @@ -197,7 +197,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct cxl_dev_state *cxlds, void __iomem *ras_base) +bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -224,7 +224,7 @@ bool cxl_handle_ras(struct cxl_dev_state *cxlds, void _= _iomem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -246,7 +246,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(cxlds, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -275,7 +275,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(cxlds, cxlds->regs.ras); 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Wed, 14 Jan 2026 12:24:56 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 18/34] cxl/port: Remove "enumerate dports" helpers Date: Wed, 14 Jan 2026 12:20:39 -0600 Message-ID: <20260114182055.46029-19-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|CYYPR12MB8869:EE_ X-MS-Office365-Filtering-Correlation-Id: 70a716f0-9f90-4f63-d4c7-08de539a388b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:24:57.1080 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70a716f0-9f90-4f63-d4c7-08de539a388b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8869 Content-Type: text/plain; charset="utf-8" From: Dan Williams Now that cxl_switch_port_probe() no longer walks potential dports, because they are enumerated dynamically on descendant endpoint arrival, remove the dead code. Signed-off-by: Dan Williams Reviewed-by: Terry Bowman --- Changes in v13 -> v14: - New patch --- drivers/cxl/core/pci.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index b838c59d7a3c..0305a421504e 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -71,6 +71,14 @@ struct cxl_dport *__devm_cxl_add_dport_by_dev(struct cxl= _port *port, } EXPORT_SYMBOL_NS_GPL(__devm_cxl_add_dport_by_dev, "CXL"); =20 +struct cxl_walk_context { + struct pci_bus *bus; + struct cxl_port *port; + int type; + int error; + int count; +}; + static int cxl_dvsec_mem_range_valid(struct cxl_dev_state *cxlds, int id) { struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); @@ -820,14 +828,6 @@ int cxl_gpf_port_setup(struct cxl_dport *dport) return 0; } =20 -struct cxl_walk_context { - struct pci_bus *bus; - struct cxl_port *port; - int type; - int error; - int count; -}; - static int count_dports(struct pci_dev *pdev, void *data) { struct cxl_walk_context *ctx =3D data; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:25:08.5373 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 203b3399-575d-47c3-1c7e-08de539a3f5f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4428 Content-Type: text/plain; charset="utf-8" From: Dan Williams With dport addition moving out of cxl_switch_port_probe() it is no longer the case that a single dport-add failure will cause all dport resources to be automatically unwound. devm still helps all dport resources get cleaned up when the port is detached, but setup now needs to avoid leaking resources if an early exit occurs during setup. Convert from a "devm add" model, to an "auto remove" model that makes the caller responsible for registering devm reclaim after the object is fully instantiated. As a side of effect of this reorganization port->nr_dports is now always consistent with the number of entries in the port->dports xarray, and this can stop playing games with ida_is_empty() which is unreliable as a detector of whether decoders are setup. I.e. consider how CONFIG_DEBUG_KOBJECT_RELEASE might wreak havoc with this approach. Signed-off-by: Dan Williams Reviewed-by: Terry Bowman Reviewed-by: Dave Jiang --- Changes in v13 -> v14: - New patch --- drivers/cxl/acpi.c | 11 +- drivers/cxl/core/pci.c | 10 +- drivers/cxl/core/port.c | 225 ++++++++++++++++----------- drivers/cxl/cxl.h | 23 +-- drivers/cxl/port.c | 8 +- tools/testing/cxl/Kbuild | 3 +- tools/testing/cxl/cxl_core_exports.c | 13 +- tools/testing/cxl/exports.h | 4 +- tools/testing/cxl/test/cxl.c | 6 +- tools/testing/cxl/test/mock.c | 25 ++- tools/testing/cxl/test/mock.h | 4 +- 11 files changed, 188 insertions(+), 144 deletions(-) diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 77ac940e3013..1e1383eb9bd5 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -679,16 +679,19 @@ static int add_host_bridge_dport(struct device *match= , void *arg) if (ctx.cxl_version =3D=3D ACPI_CEDT_CHBS_VERSION_CXL11) { dev_dbg(match, "RCRB found for UID %lld: %pa\n", ctx.uid, &ctx.base); - dport =3D devm_cxl_add_rch_dport(root_port, bridge, ctx.uid, - ctx.base); + dport =3D cxl_add_rch_dport(root_port, bridge, ctx.uid, ctx.base); } else { - dport =3D devm_cxl_add_dport(root_port, bridge, ctx.uid, - CXL_RESOURCE_NONE); + dport =3D cxl_add_dport(root_port, bridge, ctx.uid, + CXL_RESOURCE_NONE); } =20 if (IS_ERR(dport)) return PTR_ERR(dport); =20 + ret =3D cxl_dport_autoremove(dport); + if (ret) + return ret; + ret =3D get_genport_coordinates(match, dport); if (ret) dev_dbg(match, "Failed to get generic port perf coordinates.\n"); diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 0305a421504e..512a3e29a095 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -41,14 +41,14 @@ static int pci_get_port_num(struct pci_dev *pdev) } =20 /** - * __devm_cxl_add_dport_by_dev - allocate a dport by dport device + * __cxl_add_dport_by_dev - allocate a dport by dport device * @port: cxl_port that hosts the dport * @dport_dev: 'struct device' of the dport * * Returns the allocated dport on success or ERR_PTR() of -errno on error */ -struct cxl_dport *__devm_cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev) +struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port, + struct device *dport_dev) { struct cxl_register_map map; struct pci_dev *pdev; @@ -67,9 +67,9 @@ struct cxl_dport *__devm_cxl_add_dport_by_dev(struct cxl_= port *port, return ERR_PTR(rc); =20 device_lock_assert(&port->dev); - return devm_cxl_add_dport(port, dport_dev, port_num, map.resource); + return cxl_add_dport(port, dport_dev, port_num, map.resource); } -EXPORT_SYMBOL_NS_GPL(__devm_cxl_add_dport_by_dev, "CXL"); +EXPORT_SYMBOL_NS_GPL(__cxl_add_dport_by_dev, "CXL"); =20 struct cxl_walk_context { struct pci_bus *bus; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index fef3aa0c6680..a05a1812bb6e 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1051,7 +1051,8 @@ static struct cxl_dport *find_dport(struct cxl_port *= port, int id) return NULL; } =20 -static int add_dport(struct cxl_port *port, struct cxl_dport *dport) +static struct cxl_dport *add_dport(struct cxl_port *port, + struct cxl_dport *dport) { struct cxl_dport *dup; int rc; @@ -1063,16 +1064,33 @@ static int add_dport(struct cxl_port *port, struct = cxl_dport *dport) "unable to add dport%d-%s non-unique port id (%s)\n", dport->port_id, dev_name(dport->dport_dev), dev_name(dup->dport_dev)); - return -EBUSY; + return ERR_PTR(-EBUSY); + } + + /* + * Unlike CXL switch upstream ports where it can train a CXL link + * independent of its downstream ports, a host bridge upstream port may + * not enable CXL registers until at least one downstream port (root + * port) trains CXL. Enumerate registers once when the number of dports + * transitions from zero to one. + */ + if (!port->nr_dports) { + rc =3D cxl_port_setup_regs(port, port->component_reg_phys); + if (rc) + return ERR_PTR(rc); } =20 + /* Arrange for dport_dev to be valid through remove_dport() */ + struct device *dev __free(put_device) =3D get_device(dport->dport_dev); + rc =3D xa_insert(&port->dports, (unsigned long)dport->dport_dev, dport, GFP_KERNEL); if (rc) - return rc; + return ERR_PTR(rc); =20 + retain_and_null_ptr(dev); port->nr_dports++; - return 0; + return dport; } =20 /* @@ -1094,51 +1112,32 @@ static void cond_cxl_root_unlock(struct cxl_port *p= ort) device_unlock(&port->dev); } =20 -static void cxl_dport_remove(void *data) +static void remove_dport(struct cxl_dport *dport) { - struct cxl_dport *dport =3D data; struct cxl_port *port =3D dport->port; =20 + port->nr_dports--; xa_erase(&port->dports, (unsigned long) dport->dport_dev); put_device(dport->dport_dev); } =20 -static void cxl_dport_unlink(void *data) -{ - struct cxl_dport *dport =3D data; - struct cxl_port *port =3D dport->port; - char link_name[CXL_TARGET_STRLEN]; +DEFINE_FREE(remove_dport, struct cxl_dport *, + if (!IS_ERR_OR_NULL(_T)) remove_dport(_T)) =20 - sprintf(link_name, "dport%d", dport->port_id); - sysfs_remove_link(&port->dev.kobj, link_name); -} - -static struct cxl_dport * -__devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, - int port_id, resource_size_t component_reg_phys, - resource_size_t rcrb) +static struct cxl_dport *__cxl_add_dport(struct cxl_port *port, + struct device *dport_dev, int port_id, + resource_size_t component_reg_phys, + resource_size_t rcrb) { char link_name[CXL_TARGET_STRLEN]; - struct cxl_dport *dport; - struct device *host; int rc; =20 - if (is_cxl_root(port)) - host =3D port->uport_dev; - else - host =3D &port->dev; - - if (!host->driver) { - dev_WARN_ONCE(&port->dev, 1, "dport:%s bad devm context\n", - dev_name(dport_dev)); - return ERR_PTR(-ENXIO); - } - if (snprintf(link_name, CXL_TARGET_STRLEN, "dport%d", port_id) >=3D CXL_TARGET_STRLEN) return ERR_PTR(-EINVAL); =20 - dport =3D devm_kzalloc(host, sizeof(*dport), GFP_KERNEL); + struct cxl_dport *dport __free(kfree) =3D + kzalloc(sizeof(*dport), GFP_KERNEL); if (!dport) return ERR_PTR(-ENOMEM); =20 @@ -1176,48 +1175,27 @@ __devm_cxl_add_dport(struct cxl_port *port, struct = device *dport_dev, &component_reg_phys); =20 cond_cxl_root_lock(port); - rc =3D add_dport(port, dport); + struct cxl_dport *dport_add __free(remove_dport) =3D + add_dport(port, dport); cond_cxl_root_unlock(port); - if (rc) - return ERR_PTR(rc); - - /* - * Setup port register if this is the first dport showed up. Having - * a dport also means that there is at least 1 active link. - */ - if (port->nr_dports =3D=3D 1 && - port->component_reg_phys !=3D CXL_RESOURCE_NONE) { - rc =3D cxl_port_setup_regs(port, port->component_reg_phys); - if (rc) { - xa_erase(&port->dports, (unsigned long)dport->dport_dev); - return ERR_PTR(rc); - } - port->component_reg_phys =3D CXL_RESOURCE_NONE; - } + if (IS_ERR(dport_add)) + return dport_add; =20 - get_device(dport_dev); - rc =3D devm_add_action_or_reset(host, cxl_dport_remove, dport); - if (rc) - return ERR_PTR(rc); + if (dev_is_pci(dport_dev)) + dport->link_latency =3D cxl_pci_get_latency(to_pci_dev(dport_dev)); =20 rc =3D sysfs_create_link(&port->dev.kobj, &dport_dev->kobj, link_name); if (rc) return ERR_PTR(rc); =20 - rc =3D devm_add_action_or_reset(host, cxl_dport_unlink, dport); - if (rc) - return ERR_PTR(rc); - - if (dev_is_pci(dport_dev)) - dport->link_latency =3D cxl_pci_get_latency(to_pci_dev(dport_dev)); - cxl_debugfs_create_dport_dir(dport); =20 - return dport; + retain_and_null_ptr(dport_add); + return no_free_ptr(dport); } =20 /** - * devm_cxl_add_dport - append VH downstream port data to a cxl_port + * cxl_add_dport - append VH downstream port data to a cxl_port * @port: the cxl_port that references this dport * @dport_dev: firmware or PCI device representing the dport * @port_id: identifier for this dport in a decoder's target list @@ -1227,14 +1205,13 @@ __devm_cxl_add_dport(struct cxl_port *port, struct = device *dport_dev, * either the port's host (for root ports), or the port itself (for * switch ports) */ -struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, - struct device *dport_dev, int port_id, - resource_size_t component_reg_phys) +struct cxl_dport *cxl_add_dport(struct cxl_port *port, struct device *dpor= t_dev, + int port_id, resource_size_t component_reg_phys) { struct cxl_dport *dport; =20 - dport =3D __devm_cxl_add_dport(port, dport_dev, port_id, - component_reg_phys, CXL_RESOURCE_NONE); + dport =3D __cxl_add_dport(port, dport_dev, port_id, component_reg_phys, + CXL_RESOURCE_NONE); if (IS_ERR(dport)) { dev_dbg(dport_dev, "failed to add dport to %s: %ld\n", dev_name(&port->dev), PTR_ERR(dport)); @@ -1245,10 +1222,10 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_por= t *port, =20 return dport; } -EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_add_dport, "CXL"); =20 /** - * devm_cxl_add_rch_dport - append RCH downstream port data to a cxl_port + * cxl_add_rch_dport - append RCH downstream port data to a cxl_port * @port: the cxl_port that references this dport * @dport_dev: firmware or PCI device representing the dport * @port_id: identifier for this dport in a decoder's target list @@ -1256,9 +1233,9 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport, "CXL"); * * See CXL 3.0 9.11.8 CXL Devices Attached to an RCH */ -struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, - struct device *dport_dev, int port_id, - resource_size_t rcrb) +struct cxl_dport *cxl_add_rch_dport(struct cxl_port *port, + struct device *dport_dev, int port_id, + resource_size_t rcrb) { struct cxl_dport *dport; =20 @@ -1267,8 +1244,8 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_p= ort *port, return ERR_PTR(-EINVAL); } =20 - dport =3D __devm_cxl_add_dport(port, dport_dev, port_id, - CXL_RESOURCE_NONE, rcrb); + dport =3D __cxl_add_dport(port, dport_dev, port_id, CXL_RESOURCE_NONE, + rcrb); if (IS_ERR(dport)) { dev_dbg(dport_dev, "failed to add RCH dport to %s: %ld\n", dev_name(&port->dev), PTR_ERR(dport)); @@ -1279,7 +1256,7 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_p= ort *port, =20 return dport; } -EXPORT_SYMBOL_NS_GPL(devm_cxl_add_rch_dport, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_add_rch_dport, "CXL"); =20 static int add_ep(struct cxl_ep *new) { @@ -1439,13 +1416,42 @@ static void delete_switch_port(struct cxl_port *por= t) devm_release_action(port->dev.parent, unregister_port, port); } =20 +static void unlink_dport(void *data) +{ + struct cxl_dport *dport =3D data; + struct cxl_port *port =3D dport->port; + char link_name[CXL_TARGET_STRLEN]; + + sprintf(link_name, "dport%d", dport->port_id); + sysfs_remove_link(&port->dev.kobj, link_name); + remove_dport(dport); + kfree(dport); +} + +int cxl_dport_autoremove(struct cxl_dport *dport) +{ + struct cxl_port *port =3D dport->port; + struct device *host; + + if (is_cxl_root(port)) + host =3D port->uport_dev; + else + host =3D &port->dev; + + return devm_add_action_or_reset(host, unlink_dport, dport); +} +EXPORT_SYMBOL_NS_GPL(cxl_dport_autoremove, "CXL"); + +/* + * Note: this only services dynamic removal of mid-level ports, root ports= are + * always removed by the platform driver (e.g. cxl_acpi). @host can be + * hard-coded to &port->dev. + */ static void del_dport(struct cxl_dport *dport) { struct cxl_port *port =3D dport->port; =20 - devm_release_action(&port->dev, cxl_dport_unlink, dport); - devm_release_action(&port->dev, cxl_dport_remove, dport); - devm_kfree(&port->dev, dport); + devm_release_action(&port->dev, unlink_dport, dport); } =20 static void del_dports(struct cxl_port *port) @@ -1597,10 +1603,24 @@ static int update_decoder_targets(struct device *de= v, void *data) return 0; } =20 -DEFINE_FREE(del_cxl_dport, struct cxl_dport *, if (!IS_ERR_OR_NULL(_T)) de= l_dport(_T)) +static struct cxl_port *cxl_port_devres_group(struct cxl_port *port) +{ + if (!devres_open_group(&port->dev, port, GFP_KERNEL)) + return ERR_PTR(-ENOMEM); + return port; +} +DEFINE_FREE(cxl_port_group_free, struct cxl_port *, + if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T)) + +static void cxl_port_group_close(struct cxl_port *port) +{ + devres_remove_group(&port->dev, port); +} + static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port, struct device *dport_dev) { + struct cxl_dport *new_dport; struct cxl_dport *dport; int rc; =20 @@ -1615,29 +1635,46 @@ static struct cxl_dport *cxl_port_add_dport(struct = cxl_port *port, return ERR_PTR(-EBUSY); } =20 - struct cxl_dport *new_dport __free(del_cxl_dport) =3D - devm_cxl_add_dport_by_dev(port, dport_dev); - if (IS_ERR(new_dport)) - return new_dport; - - cxl_switch_parse_cdat(new_dport); + /* + * With the first dport arrival it is now safe to start looking at + * component registers. Be careful to not strand resources if dport + * creation ultimately fails. + */ + struct cxl_port *port_group __free(cxl_port_group_free) =3D + cxl_port_devres_group(port); + if (IS_ERR(port_group)) + return ERR_CAST(port_group); =20 - if (ida_is_empty(&port->decoder_ida)) { + if (port->nr_dports =3D=3D 0) { rc =3D devm_cxl_switch_port_decoders_setup(port); if (rc) return ERR_PTR(rc); - dev_dbg(&port->dev, "first dport%d:%s added with decoders\n", - new_dport->port_id, dev_name(dport_dev)); - return no_free_ptr(new_dport); + /* + * Note, when nr_dports returns to zero the port is unregistered + * and triggers cleanup. I.e. no need for open-coded release + * action on dport removal. See cxl_detach_ep() for that logic. + */ } =20 + new_dport =3D cxl_add_dport_by_dev(port, dport_dev); + if (IS_ERR(new_dport)) + return new_dport; + + rc =3D cxl_dport_autoremove(new_dport); + if (rc) + return ERR_PTR(rc); + + cxl_switch_parse_cdat(new_dport); + + cxl_port_group_close(no_free_ptr(port_group)); + + dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n", + port->nr_dports - 1, new_dport->port_id, dev_name(dport_dev)); + /* New dport added, update the decoder targets */ device_for_each_child(&port->dev, new_dport, update_decoder_targets); =20 - dev_dbg(&port->dev, "dport%d:%s added\n", new_dport->port_id, - dev_name(dport_dev)); - - return no_free_ptr(new_dport); + return new_dport; } =20 static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev, diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 6f3741a57932..47ee06c95433 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -796,12 +796,12 @@ struct cxl_port *cxl_mem_find_port(struct cxl_memdev = *cxlmd, struct cxl_dport **dport); bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); =20 -struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, - struct device *dport, int port_id, - resource_size_t component_reg_phys); -struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, - struct device *dport_dev, int port_id, - resource_size_t rcrb); +struct cxl_dport *cxl_add_dport(struct cxl_port *port, struct device *dpor= t, + int port_id, + resource_size_t component_reg_phys); +struct cxl_dport *cxl_add_rch_dport(struct cxl_port *port, + struct device *dport_dev, int port_id, + resource_size_t rcrb); =20 struct cxl_decoder *to_cxl_decoder(struct device *dev); struct cxl_root_decoder *to_cxl_root_decoder(struct device *dev); @@ -824,6 +824,7 @@ static inline int cxl_root_decoder_autoremove(struct de= vice *host, return cxl_decoder_autoremove(host, &cxlrd->cxlsd.cxld); } int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *end= point); +int cxl_dport_autoremove(struct cxl_dport *dport); =20 /** * struct cxl_endpoint_dvsec_info - Cached DVSEC info @@ -937,10 +938,10 @@ void cxl_coordinates_combine(struct access_coordinate= *out, struct access_coordinate *c2); =20 bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); -struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev); -struct cxl_dport *__devm_cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev); +struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port, + struct device *dport_dev); +struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port, + struct device *dport_dev); =20 /* * Unit test builds overrides this to __weak, find the 'strong' version @@ -964,7 +965,7 @@ u16 cxl_gpf_get_dvsec(struct device *dev); */ #ifndef CXL_TEST_ENABLE #define DECLARE_TESTABLE(x) __##x -#define devm_cxl_add_dport_by_dev DECLARE_TESTABLE(devm_cxl_add_dport_by_d= ev) +#define cxl_add_dport_by_dev DECLARE_TESTABLE(cxl_add_dport_by_dev) #define devm_cxl_switch_port_decoders_setup DECLARE_TESTABLE(devm_cxl_swit= ch_port_decoders_setup) #endif =20 diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 51c8f2f84717..167cc0a87484 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -59,8 +59,12 @@ static int discover_region(struct device *dev, void *unu= sed) =20 static int cxl_switch_port_probe(struct cxl_port *port) { - /* Reset nr_dports for rebind of driver */ - port->nr_dports =3D 0; + /* + * Unfortunately, typical driver operations like "find and map + * registers", can not be done at port device attach time and must wait + * for dport arrival. See cxl_port_add_dport() and the comments in + * add_dport() for details. + */ =20 /* Cache the data early to ensure is_visible() works */ read_cdat_data(port); diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 6eceefefb0e0..4d740392aac5 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -5,7 +5,8 @@ ldflags-y +=3D --wrap=3Dacpi_evaluate_integer ldflags-y +=3D --wrap=3Dacpi_pci_find_root ldflags-y +=3D --wrap=3Dnvdimm_bus_register ldflags-y +=3D --wrap=3Dcxl_await_media_ready -ldflags-y +=3D --wrap=3Ddevm_cxl_add_rch_dport +ldflags-y +=3D --wrap=3Dcxl_add_rch_dport +ldflags-y +=3D --wrap=3Dcxl_rcd_component_reg_phys ldflags-y +=3D --wrap=3Dcxl_endpoint_parse_cdat ldflags-y +=3D --wrap=3Dcxl_dport_init_ras_reporting ldflags-y +=3D --wrap=3Ddevm_cxl_endpoint_decoders_setup diff --git a/tools/testing/cxl/cxl_core_exports.c b/tools/testing/cxl/cxl_c= ore_exports.c index 6754de35598d..02d479867a12 100644 --- a/tools/testing/cxl/cxl_core_exports.c +++ b/tools/testing/cxl/cxl_core_exports.c @@ -7,16 +7,15 @@ /* Exporting of cxl_core symbols that are only used by cxl_test */ EXPORT_SYMBOL_NS_GPL(cxl_num_decoders_committed, "CXL"); =20 -cxl_add_dport_by_dev_fn _devm_cxl_add_dport_by_dev =3D - __devm_cxl_add_dport_by_dev; -EXPORT_SYMBOL_NS_GPL(_devm_cxl_add_dport_by_dev, "CXL"); +cxl_add_dport_by_dev_fn _cxl_add_dport_by_dev =3D __cxl_add_dport_by_dev; +EXPORT_SYMBOL_NS_GPL(_cxl_add_dport_by_dev, "CXL"); =20 -struct cxl_dport *devm_cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev) +struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port, + struct device *dport_dev) { - return _devm_cxl_add_dport_by_dev(port, dport_dev); + return _cxl_add_dport_by_dev(port, dport_dev); } -EXPORT_SYMBOL_NS_GPL(devm_cxl_add_dport_by_dev, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_add_dport_by_dev, "CXL"); =20 cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup =3D __devm_cxl_switch_port_decoders_setup; diff --git a/tools/testing/cxl/exports.h b/tools/testing/cxl/exports.h index 7ebee7c0bd67..cbb16073be18 100644 --- a/tools/testing/cxl/exports.h +++ b/tools/testing/cxl/exports.h @@ -4,8 +4,8 @@ #define __MOCK_CXL_EXPORTS_H_ =20 typedef struct cxl_dport *(*cxl_add_dport_by_dev_fn)(struct cxl_port *port, - struct device *dport_dev); -extern cxl_add_dport_by_dev_fn _devm_cxl_add_dport_by_dev; + struct device *dport_dev); +extern cxl_add_dport_by_dev_fn _cxl_add_dport_by_dev; =20 typedef int(*cxl_switch_decoders_setup_fn)(struct cxl_port *port); extern cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup; diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 81e2aef3627a..b7a2b550c0b0 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -1060,8 +1060,8 @@ static struct cxl_dport *mock_cxl_add_dport_by_dev(st= ruct cxl_port *port, if (&pdev->dev !=3D dport_dev) continue; =20 - return devm_cxl_add_dport(port, &pdev->dev, pdev->id, - CXL_RESOURCE_NONE); + return cxl_add_dport(port, &pdev->dev, pdev->id, + CXL_RESOURCE_NONE); } =20 return ERR_PTR(-ENODEV); @@ -1126,9 +1126,9 @@ static struct cxl_mock_ops cxl_mock_ops =3D { .devm_cxl_switch_port_decoders_setup =3D mock_cxl_switch_port_decoders_se= tup, .devm_cxl_endpoint_decoders_setup =3D mock_cxl_endpoint_decoders_setup, .cxl_endpoint_parse_cdat =3D mock_cxl_endpoint_parse_cdat, - .devm_cxl_add_dport_by_dev =3D mock_cxl_add_dport_by_dev, .hmat_get_extended_linear_cache_size =3D mock_hmat_get_extended_linear_cache_size, + .cxl_add_dport_by_dev =3D mock_cxl_add_dport_by_dev, .list =3D LIST_HEAD_INIT(cxl_mock_ops.list), }; =20 diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 44bce80ef3ff..660e8402189c 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -15,14 +15,13 @@ static LIST_HEAD(mock); =20 static struct cxl_dport * -redirect_devm_cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev); +redirect_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_= dev); static int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *p= ort); =20 void register_cxl_mock_ops(struct cxl_mock_ops *ops) { list_add_rcu(&ops->list, &mock); - _devm_cxl_add_dport_by_dev =3D redirect_devm_cxl_add_dport_by_dev; + _cxl_add_dport_by_dev =3D redirect_cxl_add_dport_by_dev; _devm_cxl_switch_port_decoders_setup =3D redirect_devm_cxl_switch_port_decoders_setup; } @@ -34,7 +33,7 @@ void unregister_cxl_mock_ops(struct cxl_mock_ops *ops) { _devm_cxl_switch_port_decoders_setup =3D __devm_cxl_switch_port_decoders_setup; - _devm_cxl_add_dport_by_dev =3D __devm_cxl_add_dport_by_dev; + _cxl_add_dport_by_dev =3D __cxl_add_dport_by_dev; list_del_rcu(&ops->list); synchronize_srcu(&cxl_mock_srcu); } @@ -207,7 +206,7 @@ int __wrap_cxl_await_media_ready(struct cxl_dev_state *= cxlds) } EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, "CXL"); =20 -struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, +struct cxl_dport *__wrap_cxl_add_rch_dport(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb) @@ -217,19 +216,19 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struc= t cxl_port *port, struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); =20 if (ops && ops->is_mock_port(dport_dev)) { - dport =3D devm_cxl_add_dport(port, dport_dev, port_id, - CXL_RESOURCE_NONE); + dport =3D cxl_add_dport(port, dport_dev, port_id, + CXL_RESOURCE_NONE); if (!IS_ERR(dport)) { dport->rcrb.base =3D rcrb; dport->rch =3D true; } } else - dport =3D devm_cxl_add_rch_dport(port, dport_dev, port_id, rcrb); + dport =3D cxl_add_rch_dport(port, dport_dev, port_id, rcrb); put_cxl_mock_ops(index); =20 return dport; } -EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); +EXPORT_SYMBOL_NS_GPL(__wrap_cxl_add_rch_dport, "CXL"); =20 void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) { @@ -257,17 +256,17 @@ void __wrap_cxl_dport_init_ras_reporting(struct cxl_d= port *dport, struct device } EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dport_init_ras_reporting, "CXL"); =20 -struct cxl_dport *redirect_devm_cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev) +struct cxl_dport *redirect_cxl_add_dport_by_dev(struct cxl_port *port, + struct device *dport_dev) { int index; struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); struct cxl_dport *dport; =20 if (ops && ops->is_mock_port(port->uport_dev)) - dport =3D ops->devm_cxl_add_dport_by_dev(port, dport_dev); + dport =3D ops->cxl_add_dport_by_dev(port, dport_dev); else - dport =3D __devm_cxl_add_dport_by_dev(port, dport_dev); + dport =3D __cxl_add_dport_by_dev(port, dport_dev); put_cxl_mock_ops(index); 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Wed, 14 Jan 2026 12:25:18 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 20/34] cxl/port: Move dport operations to a driver event Date: Wed, 14 Jan 2026 12:20:41 -0600 Message-ID: <20260114182055.46029-21-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001E9:EE_|DS2PR12MB9663:EE_ X-MS-Office365-Filtering-Correlation-Id: d679322b-f156-4195-3052-08de539a45ad X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:25:19.1110 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d679322b-f156-4195-3052-08de539a45ad X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS2PR12MB9663 Content-Type: text/plain; charset="utf-8" From: Dan Williams In preparation for adding more register setup to the cxl_port_add_dport() path (for RAS register mapping), move the dport creation event to a driver callback. This achieves 2 things it puts driver operations logically where they belong, in a driver, and it obviates the gymnastics of DECLARE_TESTABLE() which just makes a mess of grepping for CXL symbols. In other words, a driver callback is less of an ongoing maintenance burden than this DECLARE_TESTABLE arrangement that does not scale and diminishes the grep-ability of the codebase. cxl_port_add_dport() moves mostly unmodified from drivers/cxl/core/port.c. The only deliberate change is that it now assumes that the device_lock is held on entry and the driver is attached (just like cxl_port_probe()). Signed-off-by: Dan Williams Reviewed-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13 -> v14: - New patch --- drivers/cxl/core/hdm.c | 6 +-- drivers/cxl/core/pci.c | 8 +-- drivers/cxl/core/port.c | 79 ++++++---------------------- drivers/cxl/cxl.h | 23 ++------ drivers/cxl/port.c | 71 +++++++++++++++++++++++++ tools/testing/cxl/Kbuild | 2 + tools/testing/cxl/cxl_core_exports.c | 21 -------- tools/testing/cxl/exports.h | 13 ----- tools/testing/cxl/test/mock.c | 23 +++----- 9 files changed, 107 insertions(+), 139 deletions(-) delete mode 100644 tools/testing/cxl/exports.h diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index 1c5d2022c87a..365b02b7a241 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -1219,12 +1219,12 @@ static int devm_cxl_enumerate_decoders(struct cxl_h= dm *cxlhdm, } =20 /** - * __devm_cxl_switch_port_decoders_setup - allocate and setup switch decod= ers + * devm_cxl_switch_port_decoders_setup - allocate and setup switch decoders * @port: CXL port context * * Return 0 or -errno on error */ -int __devm_cxl_switch_port_decoders_setup(struct cxl_port *port) +int devm_cxl_switch_port_decoders_setup(struct cxl_port *port) { struct cxl_hdm *cxlhdm; =20 @@ -1248,7 +1248,7 @@ int __devm_cxl_switch_port_decoders_setup(struct cxl_= port *port) dev_err(&port->dev, "HDM decoder capability not found\n"); return -ENXIO; } -EXPORT_SYMBOL_NS_GPL(__devm_cxl_switch_port_decoders_setup, "CXL"); +EXPORT_SYMBOL_NS_GPL(devm_cxl_switch_port_decoders_setup, "CXL"); =20 /** * devm_cxl_endpoint_decoders_setup - allocate and setup endpoint decoders diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 512a3e29a095..8633bfdef38d 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -41,14 +41,14 @@ static int pci_get_port_num(struct pci_dev *pdev) } =20 /** - * __cxl_add_dport_by_dev - allocate a dport by dport device + * cxl_add_dport_by_dev - allocate a dport by dport device * @port: cxl_port that hosts the dport * @dport_dev: 'struct device' of the dport * * Returns the allocated dport on success or ERR_PTR() of -errno on error */ -struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev) +struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port, + struct device *dport_dev) { struct cxl_register_map map; struct pci_dev *pdev; @@ -69,7 +69,7 @@ struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port = *port, device_lock_assert(&port->dev); return cxl_add_dport(port, dport_dev, port_num, map.resource); } -EXPORT_SYMBOL_NS_GPL(__cxl_add_dport_by_dev, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_add_dport_by_dev, "CXL"); =20 struct cxl_walk_context { struct pci_bus *bus; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index a05a1812bb6e..2184c20af011 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1603,78 +1603,31 @@ static int update_decoder_targets(struct device *de= v, void *data) return 0; } =20 -static struct cxl_port *cxl_port_devres_group(struct cxl_port *port) +void cxl_port_update_decoder_targets(struct cxl_port *port, + struct cxl_dport *dport) { - if (!devres_open_group(&port->dev, port, GFP_KERNEL)) - return ERR_PTR(-ENOMEM); - return port; + device_for_each_child(&port->dev, dport, update_decoder_targets); } +EXPORT_SYMBOL_NS_GPL(cxl_port_update_decoder_targets, "CXL"); + DEFINE_FREE(cxl_port_group_free, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T)) =20 -static void cxl_port_group_close(struct cxl_port *port) -{ - devres_remove_group(&port->dev, port); -} - -static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port, - struct device *dport_dev) +static struct cxl_dport *probe_dport(struct cxl_port *port, + struct device *dport_dev) { - struct cxl_dport *new_dport; - struct cxl_dport *dport; - int rc; + struct cxl_driver *drv; =20 device_lock_assert(&port->dev); if (!port->dev.driver) return ERR_PTR(-ENXIO); =20 - dport =3D cxl_find_dport_by_dev(port, dport_dev); - if (dport) { - dev_dbg(&port->dev, "dport%d:%s already exists\n", - dport->port_id, dev_name(dport_dev)); - return ERR_PTR(-EBUSY); - } - - /* - * With the first dport arrival it is now safe to start looking at - * component registers. Be careful to not strand resources if dport - * creation ultimately fails. - */ - struct cxl_port *port_group __free(cxl_port_group_free) =3D - cxl_port_devres_group(port); - if (IS_ERR(port_group)) - return ERR_CAST(port_group); - - if (port->nr_dports =3D=3D 0) { - rc =3D devm_cxl_switch_port_decoders_setup(port); - if (rc) - return ERR_PTR(rc); - /* - * Note, when nr_dports returns to zero the port is unregistered - * and triggers cleanup. I.e. no need for open-coded release - * action on dport removal. See cxl_detach_ep() for that logic. - */ - } - - new_dport =3D cxl_add_dport_by_dev(port, dport_dev); - if (IS_ERR(new_dport)) - return new_dport; - - rc =3D cxl_dport_autoremove(new_dport); - if (rc) - return ERR_PTR(rc); - - cxl_switch_parse_cdat(new_dport); - - cxl_port_group_close(no_free_ptr(port_group)); - - dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n", - port->nr_dports - 1, new_dport->port_id, dev_name(dport_dev)); - - /* New dport added, update the decoder targets */ - device_for_each_child(&port->dev, new_dport, update_decoder_targets); + drv =3D container_of(port->dev.driver, struct cxl_driver, drv); + if (!drv->add_dport) + return ERR_PTR(-ENXIO); =20 - return new_dport; + /* see cxl_port_add_dport() */ + return drv->add_dport(port, dport_dev); } =20 static struct cxl_dport *devm_cxl_create_port(struct device *ep_dev, @@ -1721,7 +1674,7 @@ static struct cxl_dport *devm_cxl_create_port(struct = device *ep_dev, } =20 guard(device)(&port->dev); - return cxl_port_add_dport(port, dport_dev); + return probe_dport(port, dport_dev); } =20 static int add_port_attach_ep(struct cxl_memdev *cxlmd, @@ -1753,7 +1706,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlm= d, scoped_guard(device, &parent_port->dev) { parent_dport =3D cxl_find_dport_by_dev(parent_port, dparent); if (!parent_dport) { - parent_dport =3D cxl_port_add_dport(parent_port, dparent); + parent_dport =3D probe_dport(parent_port, dparent); if (IS_ERR(parent_dport)) return PTR_ERR(parent_dport); } @@ -1789,7 +1742,7 @@ static struct cxl_dport *find_or_add_dport(struct cxl= _port *port, device_lock_assert(&port->dev); dport =3D cxl_find_dport_by_dev(port, dport_dev); if (!dport) { - dport =3D cxl_port_add_dport(port, dport_dev); + dport =3D probe_dport(port, dport_dev); if (IS_ERR(dport)) return dport; =20 diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 47ee06c95433..46491046f101 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -841,8 +841,9 @@ struct cxl_endpoint_dvsec_info { }; =20 int devm_cxl_switch_port_decoders_setup(struct cxl_port *port); -int __devm_cxl_switch_port_decoders_setup(struct cxl_port *port); int devm_cxl_endpoint_decoders_setup(struct cxl_port *port); +void cxl_port_update_decoder_targets(struct cxl_port *port, + struct cxl_dport *dport); =20 struct cxl_dev_state; int cxl_dvsec_rr_decode(struct cxl_dev_state *cxlds, @@ -856,6 +857,8 @@ struct cxl_driver { const char *name; int (*probe)(struct device *dev); void (*remove)(struct device *dev); + struct cxl_dport *(*add_dport)(struct cxl_port *port, + struct device *dport_dev); struct device_driver drv; int id; }; @@ -940,8 +943,6 @@ void cxl_coordinates_combine(struct access_coordinate *= out, bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port); struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_dev); -struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev); =20 /* * Unit test builds overrides this to __weak, find the 'strong' version @@ -953,20 +954,4 @@ struct cxl_dport *__cxl_add_dport_by_dev(struct cxl_po= rt *port, =20 u16 cxl_gpf_get_dvsec(struct device *dev); =20 -/* - * Declaration for functions that are mocked by cxl_test that are called by - * cxl_core. The respective functions are defined as __foo() and called by - * cxl_core as foo(). The macros below ensures that those functions would - * exist as foo(). See tools/testing/cxl/cxl_core_exports.c and - * tools/testing/cxl/exports.h for setting up the mock functions. The dance - * is done to avoid a circular dependency where cxl_core calls a function = that - * ends up being a mock function and goes to * cxl_test where it calls a - * cxl_core function. - */ -#ifndef CXL_TEST_ENABLE -#define DECLARE_TESTABLE(x) __##x -#define cxl_add_dport_by_dev DECLARE_TESTABLE(cxl_add_dport_by_dev) -#define devm_cxl_switch_port_decoders_setup DECLARE_TESTABLE(devm_cxl_swit= ch_port_decoders_setup) -#endif - #endif /* __CXL_H__ */ diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 167cc0a87484..2770bc8520d3 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -155,9 +155,80 @@ static const struct attribute_group *cxl_port_attribut= e_groups[] =3D { NULL, }; =20 +static struct cxl_port *cxl_port_devres_group(struct cxl_port *port) +{ + if (!devres_open_group(&port->dev, port, GFP_KERNEL)) + return ERR_PTR(-ENOMEM); + return port; +} +DEFINE_FREE(cxl_port_group_free, struct cxl_port *, + if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T)) + +static void cxl_port_group_close(struct cxl_port *port) +{ + devres_remove_group(&port->dev, port); +} + +static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port, + struct device *dport_dev) +{ + struct cxl_dport *new_dport; + struct cxl_dport *dport; + int rc; + + dport =3D cxl_find_dport_by_dev(port, dport_dev); + if (dport) { + dev_dbg(&port->dev, "dport%d:%s already exists\n", + dport->port_id, dev_name(dport_dev)); + return ERR_PTR(-EBUSY); + } + + /* + * With the first dport arrival it is now safe to start looking at + * component registers. Be careful to not strand resources if dport + * creation ultimately fails. + */ + struct cxl_port *port_group __free(cxl_port_group_free) =3D + cxl_port_devres_group(port); + if (IS_ERR(port_group)) + return ERR_CAST(port_group); + + if (port->nr_dports =3D=3D 0) { + rc =3D devm_cxl_switch_port_decoders_setup(port); + if (rc) + return ERR_PTR(rc); + /* + * Note, when nr_dports returns to zero the port is unregistered + * and triggers cleanup. I.e. no need for open-coded release + * action on dport removal. See cxl_detach_ep() for that logic. + */ + } + + new_dport =3D cxl_add_dport_by_dev(port, dport_dev); + if (IS_ERR(new_dport)) + return new_dport; + + rc =3D cxl_dport_autoremove(new_dport); + if (rc) + return ERR_PTR(rc); + + cxl_switch_parse_cdat(new_dport); + + cxl_port_group_close(no_free_ptr(port_group)); + + dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n", + port->nr_dports - 1, new_dport->port_id, dev_name(dport_dev)); + + /* New dport added, update the decoder targets */ + cxl_port_update_decoder_targets(port, new_dport); + + return new_dport; +} + static struct cxl_driver cxl_port_driver =3D { .name =3D "cxl_port", .probe =3D cxl_port_probe, + .add_dport =3D cxl_port_add_dport, .id =3D CXL_DEVICE_PORT, .drv =3D { .dev_groups =3D cxl_port_attribute_groups, diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 4d740392aac5..25516728535e 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -11,6 +11,8 @@ ldflags-y +=3D --wrap=3Dcxl_endpoint_parse_cdat ldflags-y +=3D --wrap=3Dcxl_dport_init_ras_reporting ldflags-y +=3D --wrap=3Ddevm_cxl_endpoint_decoders_setup ldflags-y +=3D --wrap=3Dhmat_get_extended_linear_cache_size +ldflags-y +=3D --wrap=3Dcxl_add_dport_by_dev +ldflags-y +=3D --wrap=3Ddevm_cxl_switch_port_decoders_setup =20 DRIVERS :=3D ../../../drivers CXL_SRC :=3D $(DRIVERS)/cxl diff --git a/tools/testing/cxl/cxl_core_exports.c b/tools/testing/cxl/cxl_c= ore_exports.c index 02d479867a12..f088792a8925 100644 --- a/tools/testing/cxl/cxl_core_exports.c +++ b/tools/testing/cxl/cxl_core_exports.c @@ -2,27 +2,6 @@ /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ =20 #include "cxl.h" -#include "exports.h" =20 /* Exporting of cxl_core symbols that are only used by cxl_test */ EXPORT_SYMBOL_NS_GPL(cxl_num_decoders_committed, "CXL"); - -cxl_add_dport_by_dev_fn _cxl_add_dport_by_dev =3D __cxl_add_dport_by_dev; -EXPORT_SYMBOL_NS_GPL(_cxl_add_dport_by_dev, "CXL"); - -struct cxl_dport *cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev) -{ - return _cxl_add_dport_by_dev(port, dport_dev); -} -EXPORT_SYMBOL_NS_GPL(cxl_add_dport_by_dev, "CXL"); - -cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup =3D - __devm_cxl_switch_port_decoders_setup; -EXPORT_SYMBOL_NS_GPL(_devm_cxl_switch_port_decoders_setup, "CXL"); - -int devm_cxl_switch_port_decoders_setup(struct cxl_port *port) -{ - return _devm_cxl_switch_port_decoders_setup(port); -} -EXPORT_SYMBOL_NS_GPL(devm_cxl_switch_port_decoders_setup, "CXL"); diff --git a/tools/testing/cxl/exports.h b/tools/testing/cxl/exports.h deleted file mode 100644 index cbb16073be18..000000000000 --- a/tools/testing/cxl/exports.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2025 Intel Corporation */ -#ifndef __MOCK_CXL_EXPORTS_H_ -#define __MOCK_CXL_EXPORTS_H_ - -typedef struct cxl_dport *(*cxl_add_dport_by_dev_fn)(struct cxl_port *port, - struct device *dport_dev); -extern cxl_add_dport_by_dev_fn _cxl_add_dport_by_dev; - -typedef int(*cxl_switch_decoders_setup_fn)(struct cxl_port *port); -extern cxl_switch_decoders_setup_fn _devm_cxl_switch_port_decoders_setup; - -#endif diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 660e8402189c..10140a4c5fac 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -10,20 +10,12 @@ #include #include #include "mock.h" -#include "../exports.h" =20 static LIST_HEAD(mock); =20 -static struct cxl_dport * -redirect_cxl_add_dport_by_dev(struct cxl_port *port, struct device *dport_= dev); -static int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *p= ort); - void register_cxl_mock_ops(struct cxl_mock_ops *ops) { list_add_rcu(&ops->list, &mock); - _cxl_add_dport_by_dev =3D redirect_cxl_add_dport_by_dev; - _devm_cxl_switch_port_decoders_setup =3D - redirect_devm_cxl_switch_port_decoders_setup; } EXPORT_SYMBOL_GPL(register_cxl_mock_ops); =20 @@ -31,9 +23,6 @@ DEFINE_STATIC_SRCU(cxl_mock_srcu); =20 void unregister_cxl_mock_ops(struct cxl_mock_ops *ops) { - _devm_cxl_switch_port_decoders_setup =3D - __devm_cxl_switch_port_decoders_setup; - _cxl_add_dport_by_dev =3D __cxl_add_dport_by_dev; list_del_rcu(&ops->list); synchronize_srcu(&cxl_mock_srcu); } @@ -162,7 +151,7 @@ __wrap_nvdimm_bus_register(struct device *dev, } EXPORT_SYMBOL_GPL(__wrap_nvdimm_bus_register); =20 -int redirect_devm_cxl_switch_port_decoders_setup(struct cxl_port *port) +int __wrap_devm_cxl_switch_port_decoders_setup(struct cxl_port *port) { int rc, index; struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); @@ -170,11 +159,12 @@ int redirect_devm_cxl_switch_port_decoders_setup(stru= ct cxl_port *port) if (ops && ops->is_mock_port(port->uport_dev)) rc =3D ops->devm_cxl_switch_port_decoders_setup(port); else - rc =3D __devm_cxl_switch_port_decoders_setup(port); + rc =3D devm_cxl_switch_port_decoders_setup(port); put_cxl_mock_ops(index); =20 return rc; } +EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_switch_port_decoders_setup, "CXL"); =20 int __wrap_devm_cxl_endpoint_decoders_setup(struct cxl_port *port) { @@ -256,8 +246,8 @@ void __wrap_cxl_dport_init_ras_reporting(struct cxl_dpo= rt *dport, struct device } EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dport_init_ras_reporting, "CXL"); =20 -struct cxl_dport *redirect_cxl_add_dport_by_dev(struct cxl_port *port, - struct device *dport_dev) +struct cxl_dport *__wrap_cxl_add_dport_by_dev(struct cxl_port *port, + struct device *dport_dev) { int index; struct cxl_mock_ops *ops =3D get_cxl_mock_ops(&index); @@ -266,11 +256,12 @@ struct cxl_dport *redirect_cxl_add_dport_by_dev(struc= t cxl_port *port, if (ops && ops->is_mock_port(port->uport_dev)) dport =3D ops->cxl_add_dport_by_dev(port, dport_dev); else - dport =3D __cxl_add_dport_by_dev(port, dport_dev); + dport =3D cxl_add_dport_by_dev(port, dport_dev); put_cxl_mock_ops(index); =20 return dport; } +EXPORT_SYMBOL_NS_GPL(__wrap_cxl_add_dport_by_dev, "CXL"); =20 MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("cxl_test: emulation module"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:25:36.0166 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cf0b37b-a271-456d-f3e9-08de539a4fc3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7222 Content-Type: text/plain; charset="utf-8" From: Dan Williams Towards the end goal of making all CXL RAS capability handling uniform across upstream host bridges, upstream switch ports, and upstream endpoint ports, move dport RAS setup to cxl_endpoint_port_probe(). Rename the RAS setup helper to devm_cxl_dport_ras_setup() for symmetry with devm_cxl_switch_port_decoders_setup(). Signed-off-by: Dan Williams Reviewed-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13 -> v14: - New patch --- drivers/cxl/core/ras.c | 12 ++++++------ drivers/cxl/cxlpci.h | 8 ++++---- drivers/cxl/mem.c | 2 -- drivers/cxl/port.c | 12 ++++++++++++ tools/testing/cxl/Kbuild | 2 +- tools/testing/cxl/test/mock.c | 6 +++--- 6 files changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 72908f3ced77..d71fcac31cf2 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -139,17 +139,17 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) } =20 /** - * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport + * devm_cxl_dport_ras_setup - Setup CXL RAS report on this dport * @dport: the cxl_dport that needs to be initialized - * @host: host device for devm operations */ -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host) +void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { - dport->reg_map.host =3D host; + dport->reg_map.host =3D &dport->port->dev; cxl_dport_map_ras(dport); =20 if (dport->rch) { - struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(dport->dport_= dev); + struct pci_host_bridge *host_bridge =3D + to_pci_host_bridge(dport->dport_dev); =20 if (!host_bridge->native_aer) return; @@ -158,7 +158,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dpo= rt, struct device *host) cxl_disable_rch_root_ints(dport); } } -EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); +EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_ras_setup, "CXL"); =20 void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 6f9c78886fd9..e41bb93d583a 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -81,7 +81,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *= host); +void devm_cxl_dport_ras_setup(struct cxl_dport *dport); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } =20 @@ -90,9 +90,9 @@ static inline pci_ers_result_t cxl_error_detected(struct = pci_dev *pdev, { return PCI_ERS_RESULT_NONE; } - -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, - struct device *host) { } +static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) +{ +} #endif =20 #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index c2ee7f7f6320..e25c33f8c6cf 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -166,8 +166,6 @@ static int cxl_mem_probe(struct device *dev) else endpoint_parent =3D &parent_port->dev; =20 - cxl_dport_init_ras_reporting(dport, dev); - scoped_guard(device, endpoint_parent) { if (!endpoint_parent->driver) { dev_err(dev, "CXL port topology %s not enabled\n", diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 2770bc8520d3..8f8fc98c1428 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -75,6 +75,7 @@ static int cxl_switch_port_probe(struct cxl_port *port) static int cxl_endpoint_port_probe(struct cxl_port *port) { struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_dport *dport =3D port->parent_dport; int rc; =20 /* Cache the data early to ensure is_visible() works */ @@ -90,6 +91,17 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) if (rc) return rc; =20 + /* + * With VH (CXL Virtual Host) topology the cxl_port::add_dport() method + * handles RAS setup for downstream ports. With RCH (CXL Restricted CXL + * Host) topologies the downstream port is enumerated early by platform + * firmware, but the RCRB (root complex register block) is not mapped + * until after the cxl_pci driver attaches to the RCIeP (root complex + * integrated endpoint). + */ + if (dport->rch) + devm_cxl_dport_ras_setup(dport); + /* * Now that all endpoint decoders are successfully enumerated, try to * assemble regions from committed decoders diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 25516728535e..7250bedf0448 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -8,7 +8,7 @@ ldflags-y +=3D --wrap=3Dcxl_await_media_ready ldflags-y +=3D --wrap=3Dcxl_add_rch_dport ldflags-y +=3D --wrap=3Dcxl_rcd_component_reg_phys ldflags-y +=3D --wrap=3Dcxl_endpoint_parse_cdat -ldflags-y +=3D --wrap=3Dcxl_dport_init_ras_reporting +ldflags-y +=3D --wrap=3Ddevm_cxl_dport_ras_setup ldflags-y +=3D --wrap=3Ddevm_cxl_endpoint_decoders_setup ldflags-y +=3D --wrap=3Dhmat_get_extended_linear_cache_size ldflags-y +=3D --wrap=3Dcxl_add_dport_by_dev diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 10140a4c5fac..8883357ee50d 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -234,17 +234,17 @@ void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *= port) } EXPORT_SYMBOL_NS_GPL(__wrap_cxl_endpoint_parse_cdat, "CXL"); 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Wed, 14 Jan 2026 12:25:45 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 22/34] cxl: Update CXL Endpoint tracing Date: Wed, 14 Jan 2026 12:20:43 -0600 Message-ID: <20260114182055.46029-23-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F5:EE_|CH3PR12MB8993:EE_ X-MS-Office365-Filtering-Correlation-Id: 91515e35-f4d7-4102-1f53-08de539a562b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:25:46.7591 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91515e35-f4d7-4102-1f53-08de539a562b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8993 Content-Type: text/plain; charset="utf-8" CXL protocol error handling will be expanded to soon include CXL Port support along with existing Endpoint support. 2 updates are needed first: - Update calling interfaces to use 'struct device*' - Log serial number Add serial number parameter to the trace logging. This is used for EPs and 0 is provided for CXL port devices without a serial number. Leave the correctable and uncorrectable trace routines' TP_STRUCT__entry() unchanged with respect to member data types and order. Below is output of correctable and uncorrectable protocol error logging. CXL Root Port and CXL Endpoint examples are included below. Root Port: cxl_aer_correctable_error: device=3D0000:0c:00.0 host=3Dpci0000:0c serial: = 0 status=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: device=3D0000:0c:00.0 host=3Dpci0000:0c serial= : 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enabl= e Parity Error' Endpoint: cxl_aer_correctable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial=3D0 sta= tus=3D'CRC Threshold Hit' cxl_aer_uncorrectable_error: memdev=3Dmem3 host=3D0000:0f:00.0 serial: 0 st= atus: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Pari= ty Error' Signed-off-by: Terry Bowman Reviewed-by: Shiju Jose Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- Changes in v13->v14: - Update commit headline (Bjorn) Changes in v12->v13: - Added Dave Jiang's review-by Changes in v11 -> v12: - Correct parameters to call trace_cxl_aer_correctable_error() - Add reviewed-by for Jonathan and Shiju Changes in v10->v11: - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI and unchanged TP_printk() logging. --- drivers/cxl/core/core.h | 4 ++-- drivers/cxl/core/ras.c | 35 ++++++++++++++++++++--------------- drivers/cxl/core/ras_rch.c | 4 ++-- drivers/cxl/core/trace.h | 25 +++++++++++++------------ 4 files changed, 37 insertions(+), 31 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 422531799af2..306762a15dc0 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -147,8 +147,8 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port= *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base= ); +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index d71fcac31cf2..84abcf90fa99 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_= dev *pdev, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_port_aer_correctable_error(&pdev->dev, status); + trace_cxl_aer_correctable_error(&pdev->dev, status, 0); } =20 static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev, @@ -28,8 +28,8 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pc= i_dev *pdev, else fe =3D status; =20 - trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe, + ras_cap.header_log, 0); } =20 static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd, @@ -37,7 +37,7 @@ static void cxl_cper_trace_corr_prot_err(struct cxl_memde= v *cxlmd, { u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; =20 - trace_cxl_aer_correctable_error(cxlmd, status); + trace_cxl_aer_correctable_error(&cxlmd->dev, status, cxlmd->cxlds->serial= ); } =20 static void @@ -45,6 +45,7 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, struct cxl_ras_capability_regs ras_cap) { u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; u32 fe; =20 if (hweight32(status) > 1) @@ -53,8 +54,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, else fe =3D status; =20 - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, - ras_cap.header_log); + trace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe, + ras_cap.header_log, + cxlds->serial); } =20 static int match_memdev_by_parent(struct device *dev, const void *uport) @@ -160,7 +162,7 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport) } EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_ras_setup, "CXL"); =20 -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; u32 status; @@ -170,10 +172,11 @@ void cxl_handle_cor_ras(struct device *dev, void __io= mem *ras_base) =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); - } + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) + return; + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); + + trace_cxl_aer_correctable_error(dev, status, serial); } =20 /* CXL spec rev3.0 8.2.4.16.1 */ @@ -197,7 +200,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; @@ -224,7 +227,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *r= as_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -246,7 +249,8 @@ void cxl_cor_error_detected(struct pci_dev *pdev) if (cxlds->rcd) cxl_handle_rdport_errors(cxlds); =20 - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, + cxlds->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -275,7 +279,8 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->regs.ras); + ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, + cxlds->regs.ras); } =20 =20 diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 0a8b3b9b6388..3e33374e07f2 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -115,7 +115,7 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxl= ds) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras); else - cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, dport->regs.ras); } diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index a972e4ef1936..c569d92b6000 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -77,11 +77,12 @@ TRACE_EVENT(cxl_port_aer_uncorrectable_error, ); =20 TRACE_EVENT(cxl_aer_uncorrectable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), - TP_ARGS(cxlmd, status, fe, hl), + TP_PROTO(const struct device *cxlmd, u32 status, u32 fe, u32 *hl, + u64 serial), + TP_ARGS(cxlmd, status, fe, hl, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, dev_name(cxlmd)) + __string(host, dev_name(cxlmd->parent)) __field(u64, serial) __field(u32, status) __field(u32, first_error) @@ -90,7 +91,7 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, TP_fast_assign( __assign_str(memdev); __assign_str(host); - __entry->serial =3D cxlmd->cxlds->serial; + __entry->serial =3D serial; __entry->status =3D status; __entry->first_error =3D fe; /* @@ -138,24 +139,24 @@ TRACE_EVENT(cxl_port_aer_correctable_error, __entry->status =3D status; ), TP_printk("device=3D%s host=3D%s status=3D'%s'", - __get_str(device), __get_str(host), - show_ce_errs(__entry->status) + __get_str(device), __get_str(host), + show_ce_errs(__entry->status) ) ); =20 TRACE_EVENT(cxl_aer_correctable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), - TP_ARGS(cxlmd, status), + TP_PROTO(const struct device *cxlmd, u32 status, u64 serial), + TP_ARGS(cxlmd, status, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, dev_name(cxlmd)) + __string(host, dev_name(cxlmd->parent)) __field(u64, serial) __field(u32, status) ), TP_fast_assign( __assign_str(memdev); __assign_str(host); - __entry->serial =3D cxlmd->cxlds->serial; + __entry->serial =3D serial; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:25:57.8547 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb042200-02aa-481d-325e-08de539a5cc8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6234 Content-Type: text/plain; charset="utf-8" In preparation for CXL VH (Virtual Host) topology protocol error handling, add RAS capability registered mapping for all ports in a CXL VH topology. This includes the RAS capabilities of Switch Upstream Ports, Switch Downstream Ports, Host Bridge Ports ("upstream"), and Root Ports ("downstream") Update cxl_port_add_dport() to map the upstream RAS capability on first 'dport' attach, and downstream RAS capability on each 'dport' attach. Arrange for dport mappings to be released at del_dport() time. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang [djbw: reword changelog, fix devm handling] Co-developed-by: Dan Williams Signed-off-by: Dan Williams --- Changes in v13->v14: - Correct message spelling (Terry) --- drivers/cxl/core/port.c | 2 +- drivers/cxl/core/ras.c | 11 +++++++++++ drivers/cxl/cxl.h | 2 ++ drivers/cxl/cxlpci.h | 4 ++++ drivers/cxl/port.c | 37 +++++++++++++++++++++++++++++++++++ tools/testing/cxl/Kbuild | 1 + tools/testing/cxl/test/mock.c | 12 ++++++++++++ 7 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2184c20af011..2c4e28e7975c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1451,7 +1451,7 @@ static void del_dport(struct cxl_dport *dport) { struct cxl_port *port =3D dport->port; =20 - devm_release_action(&port->dev, unlink_dport, dport); + devres_release_group(&port->dev, dport); } =20 static void del_dports(struct cxl_port *port) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 84abcf90fa99..76ac567724e3 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -162,6 +162,17 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport) } EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_ras_setup, "CXL"); =20 +void devm_cxl_port_ras_setup(struct cxl_port *port) +{ + struct cxl_register_map *map =3D &port->reg_map; + + map->host =3D &port->dev; + if (cxl_map_component_regs(map, &port->regs, + BIT(CXL_CM_CAP_CAP_ID_RAS))) + dev_dbg(&port->dev, "Failed to map RAS capability\n"); +} +EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 46491046f101..805923693707 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -607,6 +607,7 @@ struct cxl_dax_region { * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @reg_map: component and ras register mapping parameters + * @regs: mapped component registers * @nr_dports: number of entries in @dports * @hdm_end: track last allocated HDM decoder instance for allocation orde= ring * @commit_end: cursor to track highest committed decoder for commit order= ing @@ -628,6 +629,7 @@ struct cxl_port { struct cxl_dport *parent_dport; struct ida decoder_ida; struct cxl_register_map reg_map; + struct cxl_component_regs regs; int nr_dports; int hdm_end; int commit_end; diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index e41bb93d583a..ef4496b4e55e 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -82,6 +82,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); +void devm_cxl_port_ras_setup(struct cxl_port *port); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } =20 @@ -93,6 +94,9 @@ static inline pci_ers_result_t cxl_error_detected(struct = pci_dev *pdev, static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { } +static inline void devm_cxl_port_ras_setup(struct cxl_port *port) +{ +} #endif =20 #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 8f8fc98c1428..0d6e010e21ca 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -176,11 +176,29 @@ static struct cxl_port *cxl_port_devres_group(struct = cxl_port *port) DEFINE_FREE(cxl_port_group_free, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->dev, _T)) =20 +static struct cxl_dport *cxl_dport_devres_group(struct cxl_dport *dport) +{ + if (!devres_open_group(&dport->port->dev, dport, GFP_KERNEL)) + return ERR_PTR(-ENOMEM); + return dport; +} +DEFINE_FREE(cxl_dport_group_free, struct cxl_dport *, + if (!IS_ERR_OR_NULL(_T)) devres_release_group(&(_T)->port->dev, _T)) + static void cxl_port_group_close(struct cxl_port *port) { devres_remove_group(&port->dev, port); } =20 +/* + * Unlike the port group, that just facilitates unwind of setup failures, = the + * dport group needs to stay live for del_dport() to reference. + */ +static void cxl_dport_group_close(struct cxl_dport *dport) +{ + devres_close_group(&dport->port->dev, dport); +} + static struct cxl_dport *cxl_port_add_dport(struct cxl_port *port, struct device *dport_dev) { @@ -209,6 +227,13 @@ static struct cxl_dport *cxl_port_add_dport(struct cxl= _port *port, rc =3D devm_cxl_switch_port_decoders_setup(port); if (rc) return ERR_PTR(rc); + + /* + * RAS setup is optional, either driver operation can continue + * on failure, or the device does not implement RAS registers. + */ + devm_cxl_port_ras_setup(port); + /* * Note, when nr_dports returns to zero the port is unregistered * and triggers cleanup. I.e. no need for open-coded release @@ -220,12 +245,24 @@ static struct cxl_dport *cxl_port_add_dport(struct cx= l_port *port, if (IS_ERR(new_dport)) return new_dport; =20 + /* + * Establish a group for all dport resources that need to be released + * when the dport is deleted. + */ + struct cxl_dport *dport_group __free(cxl_dport_group_free) =3D + cxl_dport_devres_group(new_dport); + if (IS_ERR(dport_group)) + return ERR_CAST(dport_group); + rc =3D cxl_dport_autoremove(new_dport); if (rc) return ERR_PTR(rc); =20 + devm_cxl_dport_ras_setup(new_dport); + cxl_switch_parse_cdat(new_dport); =20 + cxl_dport_group_close(no_free_ptr(dport_group)); cxl_port_group_close(no_free_ptr(port_group)); =20 dev_dbg(&port->dev, "dport[%d] id:%d dport_dev: %s added\n", diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 7250bedf0448..6c516019600e 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -13,6 +13,7 @@ ldflags-y +=3D --wrap=3Ddevm_cxl_endpoint_decoders_setup ldflags-y +=3D --wrap=3Dhmat_get_extended_linear_cache_size ldflags-y +=3D --wrap=3Dcxl_add_dport_by_dev ldflags-y +=3D --wrap=3Ddevm_cxl_switch_port_decoders_setup +ldflags-y +=3D --wrap=3Ddevm_cxl_port_ras_setup =20 DRIVERS :=3D ../../../drivers CXL_SRC :=3D $(DRIVERS)/cxl diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 8883357ee50d..a0b87bbb2f75 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -246,6 +246,18 @@ void __wrap_devm_cxl_dport_ras_setup(struct cxl_dport = *dport) } EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_dport_ras_setup, "CXL"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:26:13.9478 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f81f4038-576e-4343-e8b9-08de539a665f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7783 Content-Type: text/plain; charset="utf-8" From: Dan Williams In preparation for generic protocol error handling across CXL endpoints, whether they be memory expander class devices or accelerators, drop the endpoint component management from cxl_dev_state. Organize all CXL port component management through the common cxl_port driver. Note that the end game is that drivers/cxl/core/ras.c loses all dependencies on a 'struct cxl_dev_state' parameter and operates only on port resources. The removal of component register mapping from cxl_pci is an incremental step towards that. Signed-off-by: Dan Williams Reviewed-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13 -> v14: - New patch - Update log message for cxl_ras_unmask() failure (Dan) --- drivers/cxl/core/ras.c | 6 ++-- drivers/cxl/cxlmem.h | 4 +-- drivers/cxl/pci.c | 63 +----------------------------------------- drivers/cxl/port.c | 54 ++++++++++++++++++++++++++++++++++++ 4 files changed, 60 insertions(+), 67 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 76ac567724e3..b37108f60c56 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -247,6 +247,7 @@ bool cxl_handle_ras(struct device *dev, u64 serial, voi= d __iomem *ras_base) void cxl_cor_error_detected(struct pci_dev *pdev) { struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; struct device *dev =3D &cxlds->cxlmd->dev; =20 scoped_guard(device, dev) { @@ -261,7 +262,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev) cxl_handle_rdport_errors(cxlds); =20 cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, - cxlds->regs.ras); + cxlmd->endpoint->regs.ras); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -291,10 +292,9 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pd= ev, * capability registers and bounce the active state of the memdev. */ ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, - cxlds->regs.ras); + cxlmd->endpoint->regs.ras); } =20 - switch (state) { case pci_channel_io_normal: if (ue) { diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 434031a0c1f7..ab7201ef3ea6 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -415,7 +415,7 @@ struct cxl_dpa_partition { * @dev: The device associated with this CXL state * @cxlmd: The device representing the CXL.mem capabilities of @dev * @reg_map: component and ras register mapping parameters - * @regs: Parsed register blocks + * @regs: Class device "Device" registers * @cxl_dvsec: Offset to the PCIe device DVSEC * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an = RCH) * @media_ready: Indicate whether the device media is usable @@ -431,7 +431,7 @@ struct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; struct cxl_register_map reg_map; - struct cxl_regs regs; + struct cxl_device_regs regs; int cxl_dvsec; bool rcd; bool media_ready; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index b7f694bda913..acb0eb2a13c3 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -535,52 +535,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, en= um cxl_regloc_type type, return cxl_setup_regs(map); } =20 -static int cxl_pci_ras_unmask(struct pci_dev *pdev) -{ - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - void __iomem *addr; - u32 orig_val, val, mask; - u16 cap; - int rc; - - if (!cxlds->regs.ras) { - dev_dbg(&pdev->dev, "No RAS registers.\n"); - return 0; - } - - /* BIOS has PCIe AER error control */ - if (!pcie_aer_is_native(pdev)) - return 0; - - rc =3D pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); - if (rc) - return rc; - - if (cap & PCI_EXP_DEVCTL_URRE) { - addr =3D cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; - orig_val =3D readl(addr); - - mask =3D CXL_RAS_UNCORRECTABLE_MASK_MASK | - CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; - val =3D orig_val & ~mask; - writel(val, addr); - dev_dbg(&pdev->dev, - "Uncorrectable RAS Errors Mask: %#x -> %#x\n", - orig_val, val); - } - - if (cap & PCI_EXP_DEVCTL_CERE) { - addr =3D cxlds->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; - orig_val =3D readl(addr); - val =3D orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; - writel(val, addr); - dev_dbg(&pdev->dev, "Correctable RAS Errors Mask: %#x -> %#x\n", - orig_val, val); - } - - return 0; -} - static void free_event_buf(void *buf) { kvfree(buf); @@ -912,13 +866,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) unsigned int i; bool irq_avail; =20 - /* - * Double check the anonymous union trickery in struct cxl_regs - * FIXME switch to struct_group() - */ - BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) !=3D - offsetof(struct cxl_regs, device_regs.memdev)); - rc =3D pcim_enable_device(pdev); if (rc) return rc; @@ -942,7 +889,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) if (rc) return rc; =20 - rc =3D cxl_map_device_regs(&map, &cxlds->regs.device_regs); + rc =3D cxl_map_device_regs(&map, &cxlds->regs); if (rc) return rc; =20 @@ -957,11 +904,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) else if (!cxlds->reg_map.component_map.ras.valid) dev_dbg(&pdev->dev, "RAS registers not found\n"); =20 - rc =3D cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS)); - if (rc) - dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); - rc =3D cxl_pci_type3_init_mailbox(cxlds); if (rc) return rc; @@ -1052,9 +994,6 @@ static int cxl_pci_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) if (rc) return rc; =20 - if (cxl_pci_ras_unmask(pdev)) - dev_dbg(&pdev->dev, "No RAS reporting unmasked\n"); - pci_save_state(pdev); =20 return rc; diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 0d6e010e21ca..d76b4b532064 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ +#include #include #include #include @@ -72,6 +73,55 @@ static int cxl_switch_port_probe(struct cxl_port *port) return 0; } =20 +static int cxl_ras_unmask(struct cxl_port *port) +{ + struct pci_dev *pdev; + void __iomem *addr; + u32 orig_val, val, mask; + u16 cap; + int rc; + + if (!dev_is_pci(port->uport_dev)) + return 0; + pdev =3D to_pci_dev(port->uport_dev); + + if (!port->regs.ras) { + pci_dbg(pdev, "No RAS registers.\n"); + return 0; + } + + /* BIOS has PCIe AER error control */ + if (!pcie_aer_is_native(pdev)) + return 0; + + rc =3D pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); + if (rc) + return rc; + + if (cap & PCI_EXP_DEVCTL_URRE) { + addr =3D port->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; + orig_val =3D readl(addr); + + mask =3D CXL_RAS_UNCORRECTABLE_MASK_MASK | + CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; + val =3D orig_val & ~mask; + writel(val, addr); + pci_dbg(pdev, "Uncorrectable RAS Errors Mask: %#x -> %#x\n", + orig_val, val); + } + + if (cap & PCI_EXP_DEVCTL_CERE) { + addr =3D port->regs.ras + CXL_RAS_CORRECTABLE_MASK_OFFSET; + orig_val =3D readl(addr); + val =3D orig_val & ~CXL_RAS_CORRECTABLE_MASK_MASK; + writel(val, addr); + pci_dbg(pdev, "Correctable RAS Errors Mask: %#x -> %#x\n", + orig_val, val); + } + + return 0; +} + static int cxl_endpoint_port_probe(struct cxl_port *port) { struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); @@ -102,6 +152,10 @@ static int cxl_endpoint_port_probe(struct cxl_port *po= rt) if (dport->rch) devm_cxl_dport_ras_setup(dport); =20 + devm_cxl_port_ras_setup(port); + if (cxl_ras_unmask(port)) + dev_dbg(&port->dev, "failed to unmask RAS interrupts\n"); + /* * Now that all endpoint decoders are successfully enumerated, try to * assemble regions from committed decoders --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012056.outbound.protection.outlook.com [52.101.48.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4522C335064; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:26:30.0260 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 956a0c6c-9ede-40f1-e9b6-08de539a6ff5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5768 Content-Type: text/plain; charset="utf-8" Port HDM registers must be mapped before calling devm_cxl_switch_port_decoders_setup(). Invoke a call to this function in cxl_port_add_dport(). Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang --- drivers/cxl/core/port.c | 3 ++- drivers/cxl/cxlpci.h | 3 +++ drivers/cxl/port.c | 5 +++++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 2c4e28e7975c..3f730511f11d 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -778,7 +778,7 @@ static int cxl_setup_comp_regs(struct device *host, str= uct cxl_register_map *map return cxl_setup_regs(map); } =20 -static int cxl_port_setup_regs(struct cxl_port *port, +int cxl_port_setup_regs(struct cxl_port *port, resource_size_t component_reg_phys) { if (dev_is_platform(port->uport_dev)) @@ -786,6 +786,7 @@ static int cxl_port_setup_regs(struct cxl_port *port, return cxl_setup_comp_regs(&port->dev, &port->reg_map, component_reg_phys); } +EXPORT_SYMBOL_NS_GPL(cxl_port_setup_regs, "CXL"); =20 static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dpo= rt, resource_size_t component_reg_phys) diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index ef4496b4e55e..532506595d0f 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -99,4 +99,7 @@ static inline void devm_cxl_port_ras_setup(struct cxl_por= t *port) } #endif =20 +int cxl_port_setup_regs(struct cxl_port *port, + resource_size_t component_reg_phys); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:26:41.1026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 740c7cfe-e084-4e95-5d47-08de539a768f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH8PR12MB9741 Content-Type: text/plain; charset="utf-8" The CXL protocol error handlers use scoped_guard() to guarantee access to the underlying CXL memory device. Improve readability and reduce complexity by changing the current scoped_guard() to be guard(). Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang > --- Changes in v13->v14: - Add reviewed-by for Jonathan and Dave Jiang Changes in v12->v13: - New patch --- drivers/cxl/core/ras.c | 58 +++++++++++++++++++++--------------------- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index b37108f60c56..bf82880e19b4 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -250,20 +250,20 @@ void cxl_cor_error_detected(struct pci_dev *pdev) struct cxl_memdev *cxlmd =3D cxlds->cxlmd; struct device *dev =3D &cxlds->cxlmd->dev; =20 - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } + guard(device)(dev); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + cxl_handle_cor_ras(&cxlmd->dev, cxlds->serial, + cxlmd->endpoint->regs.ras); } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 @@ -275,26 +275,26 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *p= dev, struct device *dev =3D &cxlmd->dev; bool ue; =20 - scoped_guard(device, dev) { - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } + guard(device)(dev); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_DISCONNECT; } =20 + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + /* + * A frozen channel indicates an impending reset which is fatal to + * CXL.mem operation, and will likely crash the system. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:26:52.1782 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a6090c21-1cc6-41af-68e5-08de539a7d29 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9542 Content-Type: text/plain; charset="utf-8" The CXL driver's error handling for uncorrectable errors (UCE) will be updated in the future. A required change is for the error handlers to to force a system panic when a UCE is detected. Introduce PCI_ERS_RESULT_PANIC as a 'enum pci_ers_result' type. This will be used by CXL UCE fatal and non-fatal recovery in future patches. Update PCIe recovery documentation with details of PCI_ERS_RESULT_PANIC. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Ben Cheatham Reviewed-by: Dan Williams Reviewed-by: Kuppuswamy Sathyanarayanan --- Changes in v13 -> v14: - Add review-by for Dan - Update Title prefix (Bjorn) - Removed merge_result. Only logging error for device reporting the error (Dan) Changes in v12->v13: - Add Dave Jiang's, Jonathan's, Ben's review-by - Typo fix (Ben) Changes v11 -> v12: - Documentation requested (Lukas) --- Documentation/PCI/pci-error-recovery.rst | 2 ++ include/linux/pci.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/Documentation/PCI/pci-error-recovery.rst b/Documentation/PCI/p= ci-error-recovery.rst index 43bc4e3665b4..82ee2c8c0450 100644 --- a/Documentation/PCI/pci-error-recovery.rst +++ b/Documentation/PCI/pci-error-recovery.rst @@ -102,6 +102,8 @@ Possible return values are:: PCI_ERS_RESULT_NEED_RESET, /* Device driver wants slot to be reset. */ PCI_ERS_RESULT_DISCONNECT, /* Device has completely failed, is unrecove= rable */ PCI_ERS_RESULT_RECOVERED, /* Device driver is fully recovered and oper= ational */ + PCI_ERS_RESULT_NO_AER_DRIVER, /* No AER capabilities registered for the = driver */ + PCI_ERS_RESULT_PANIC, /* System is unstable, panic. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:27:03.0088 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe4887e6-c7a8-46c6-4eb3-08de539a8395 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9174 Content-Type: text/plain; charset="utf-8" CXL virtual hierarchy (VH) RAS handling for CXL Port devices will be added soon. This requires a notification mechanism for the AER driver to share the AER interrupt with the CXL driver. The notification will be used as an indication for the CXL drivers to handle and log the CXL RAS errors. Note, 'CXL protocol error' terminology will refer to CXL VH and not CXL RCH errors unless specifically noted going forward. Introduce a new file in the AER driver to handle the CXL protocol errors named pci/pcie/aer_cxl_vh.c. Add a kfifo work queue to be used by the AER and CXL drivers. The AER driver will be the sole kfifo producer adding work and the cxl_core will be the sole kfifo consumer removing work. Add the boilerplate kfifo support. Encapsulate the kfifo, RW semaphore, and work pointer in a single structure. Add CXL work queue handler registration functions in the AER driver. Export the functions allowing CXL driver to access. Implement registration functions for the CXL driver to assign or clear the work handler function. Synchronize accesses using the RW semaphore. Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work data. This will contain a reference to the PCI error source device and the error severity. This will be used when the work is dequeued by the cxl_core drive= r. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- Changes in v13 -> v14: - Replaced workqueue_types.h include with 'struct work_struct' predeclaration (Bjorn) - Update error message (Bjorn) - Reordered 'struct cxl_proto_err_work_data' (Bjorn) - Remove export of cxl_error_is_native() here (Bjorn) Changes in v12->v13: - Added Dave Jiang's review-by - Update error message (Ben) Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 15 ++----- drivers/pci/pcie/aer_cxl_vh.c | 78 +++++++++++++++++++++++++++++++++++ drivers/pci/pcie/portdrv.h | 4 ++ include/linux/aer.h | 22 ++++++++++ 5 files changed, 109 insertions(+), 11 deletions(-) create mode 100644 drivers/pci/pcie/aer_cxl_vh.c diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index b0b43a18c304..62d3d3c69a5d 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_rch.o +obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_vh.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index d30a217fae46..c2030d32a19c 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1150,16 +1150,6 @@ void pci_aer_unmask_internal_errors(struct pci_dev *= dev) } EXPORT_SYMBOL_GPL(pci_aer_unmask_internal_errors); =20 -#ifdef CONFIG_CXL_RAS -bool is_aer_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} -#endif - /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device @@ -1196,7 +1186,10 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { cxl_rch_handle_error(dev, info); - pci_aer_handle_error(dev, info); + if (is_cxl_error(dev, info)) + cxl_forward_error(dev, info); + else + pci_aer_handle_error(dev, info); pci_dev_put(dev); } =20 diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c new file mode 100644 index 000000000000..2189d3c6cef1 --- /dev/null +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include +#include "../pci.h" +#include "portdrv.h" + +#define CXL_ERROR_SOURCES_MAX 128 + +struct cxl_proto_err_kfifo { + struct work_struct *work; + struct rw_semaphore rw_sema; + DECLARE_KFIFO(fifo, struct cxl_proto_err_work_data, + CXL_ERROR_SOURCES_MAX); +}; + +static struct cxl_proto_err_kfifo cxl_proto_err_kfifo =3D { + .rw_sema =3D __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rw_sema) +}; + +bool is_aer_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; + + return info->status & PCI_ERR_UNC_INTN; +} + +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + if (!info || !info->is_cxl) + return false; + + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + return false; + + return is_aer_internal_error(info); +} + +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + struct cxl_proto_err_work_data wd =3D (struct cxl_proto_err_work_data) { + .severity =3D info->severity, + .pdev =3D pdev + }; + + guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema); + if (!cxl_proto_err_kfifo.work || !kfifo_put(&cxl_proto_err_kfifo.fifo, wd= )) { + dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo error"); + return; + } + + schedule_work(cxl_proto_err_kfifo.work); +} + +void cxl_register_proto_err_work(struct work_struct *work) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D work; +} +EXPORT_SYMBOL_NS_GPL(cxl_register_proto_err_work, "CXL"); + +void cxl_unregister_proto_err_work(void) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema); + cxl_proto_err_kfifo.work =3D NULL; +} +EXPORT_SYMBOL_NS_GPL(cxl_unregister_proto_err_work, "CXL"); + +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd) +{ + guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema); + return kfifo_get(&cxl_proto_err_kfifo.fifo, wd); +} +EXPORT_SYMBOL_NS_GPL(cxl_proto_err_kfifo_get, "CXL"); diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index cc58bf2f2c84..66a6b8099c96 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -130,9 +130,13 @@ struct aer_err_info; bool is_aer_internal_error(struct aer_err_info *info); void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); void cxl_rch_enable_rcec(struct pci_dev *rcec); +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info); #else static inline bool is_aer_internal_error(struct aer_err_info *info) { retu= rn false; } static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_er= r_info *info) { } static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { } +static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } +static inline void cxl_forward_error(struct pci_dev *pdev, struct aer_err_= info *info) { } #endif /* CONFIG_CXL_RAS */ #endif /* _PORTDRV_H_ */ diff --git a/include/linux/aer.h b/include/linux/aer.h index df0f5c382286..f351e41dd979 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -53,6 +53,16 @@ struct aer_capability_regs { u16 uncor_err_source; }; =20 +/** + * struct cxl_proto_err_work_data - Error information used in CXL error ha= ndling + * @pdev: PCI device detecting the error + * @severity: AER severity + */ +struct cxl_proto_err_work_data { + struct pci_dev *pdev; + int severity; +}; + #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); @@ -66,6 +76,18 @@ static inline int pcie_aer_is_native(struct pci_dev *dev= ) { return 0; } static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } #endif =20 +struct work_struct; + +#ifdef CONFIG_CXL_RAS +int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *wd); +void cxl_register_proto_err_work(struct work_struct *work); +void cxl_unregister_proto_err_work(void); +#else +static inline int cxl_proto_err_kfifo_get(struct cxl_proto_err_work_data *= wd) { return 0; } +static inline void cxl_register_proto_err_work(struct work_struct *work) {= } +static inline void cxl_unregister_proto_err_work(void) { } +#endif + void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:27:19.1823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a31a7950-73ed-444d-bd59-08de539a8d41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6732 Content-Type: text/plain; charset="utf-8" From: Dan Williams In support of generic CXL protocol error handling across various 'struct cxl_port' types, update find_cxl_port_by_uport() to retrieve endpoint CXL port companions from endpoint PCIe device instances. The end result is that upstream switch ports and endpoint ports can share error handling and eventually delete the misplaced cxl_error_handlers from the cxl_pci class driver. Signed-off-by: Dan Williams Reviewed-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v13->v14: - New patch --- drivers/cxl/core/port.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 3f730511f11d..a535e57360e0 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1561,10 +1561,20 @@ static int match_port_by_uport(struct device *dev, = const void *data) return 0; =20 port =3D to_cxl_port(dev); + /* Endpoint ports are hosted by memdevs */ + if (is_cxl_memdev(port->uport_dev)) + return uport_dev =3D=3D port->uport_dev->parent; return uport_dev =3D=3D port->uport_dev; } =20 -/* +/** + * find_cxl_port_by_uport - Find a CXL port device companion + * @uport_dev: Device that acts as a switch or endpoint in the CXL hierarc= hy + * + * In the case of endpoint ports recall that port->uport_dev points to a '= struct + * cxl_memdev' device. So, the @uport_dev argument is the parent device of= the + * 'struct cxl_memdev' in that case. + * * Function takes a device reference on the port device. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:27:35.3654 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17f7ebe9-7f46-4477-f22b-08de539a96e7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFB2BF91BC0 Content-Type: text/plain; charset="utf-8" The AER driver now forwards CXL protocol errors to the CXL driver via a kfifo. The CXL driver must consume these work items and initiate protocol error handling while ensuring the device's RAS mappings remain valid throughout processing. Implement cxl_proto_err_work_fn() to dequeue work items forwarded by the AER service driver. Lock the parent CXL Port device to ensure the CXL device's RAS registers are accessible during handling. Add pdev reference-p= ut to match reference-get in AER driver. This will ensure pdev access after kfifo dequeue. These changes apply to CXL Ports and CXL Endpoints. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas --- Changes in v13->v14: - Update commit title's prefix (Bjorn) - Add pdev ref get in AER driver before enqueue and add pdev ref put in CXL driver after dequeue and handling (Dan) - Removed handling to simplify patch context (Terry) Changes in v12->v13: - Add cxlmd lock using guard() (Terry) - Remove exporting of unused function, pci_aer_clear_fatal_status() (Dave J= iang) - Change pr_err() calls to ratelimited. (Terry) - Update commit message. (Terry) - Remove namespace qualifier from pcie_clear_device_status() export (Dave Jiang) - Move locks into cxl_proto_err_work_fn() (Dave) - Update log messages in cxl_forward_error() (Ben) Changes in v11->v12: - Add guard for CE case in cxl_handle_proto_error() (Dave) Changes in v10->v11: - Reword patch commit message to remove RCiEP details (Jonathan) - Add #include (Terry) - is_cxl_rcd() - Fix short comment message wrap (Jonathan) - is_cxl_rcd() - Combine return calls into 1 (Jonathan) - cxl_handle_proto_error() - Move comment earlier (Jonathan) - Use FIELD_GET() in discovering class code (Jonathan) - Remove BDF from cxl_proto_err_work_data. Use 'struct pci_dev *' (Dan) --- drivers/cxl/core/core.h | 3 ++ drivers/cxl/core/port.c | 6 +-- drivers/cxl/core/ras.c | 98 +++++++++++++++++++++++++++++++---- drivers/pci/pcie/aer_cxl_vh.c | 1 + 4 files changed, 94 insertions(+), 14 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 306762a15dc0..39324e1b8940 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -169,6 +169,9 @@ static inline void cxl_handle_rdport_errors(struct cxl_= dev_state *cxlds) { } #endif /* CONFIG_CXL_RAS */ =20 int cxl_gpf_port_setup(struct cxl_dport *dport); +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport); +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev); =20 struct cxl_hdm; int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhd= m, diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index a535e57360e0..0bec10be5d56 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1335,8 +1335,8 @@ static struct cxl_port *__find_cxl_port(struct cxl_fi= nd_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, @@ -1578,7 +1578,7 @@ static int match_port_by_uport(struct device *dev, co= nst void *data) * Function takes a device reference on the port device. Caller should do a * put_device() when done. */ -static struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) { struct device *dev; =20 diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index bf82880e19b4..0c640b84ad70 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -117,17 +117,6 @@ static void cxl_cper_prot_err_work_fn(struct work_stru= ct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 -int cxl_ras_init(void) -{ - return cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); -} - -void cxl_ras_exit(void) -{ - cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); - cancel_work_sync(&cxl_cper_prot_err_work); -} - static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -173,6 +162,44 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 +/* + * Return 'struct cxl_port *' parent CXL Port of dev + * + * Reference count increments returned port on success + * + * @pdev: Find the parent CXL Port of this device + */ +static struct cxl_port *get_cxl_port(struct pci_dev *pdev) +{ + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport; + struct cxl_port *port =3D find_cxl_port(&pdev->dev, &dport); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port; + } + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_ENDPOINT: + { + struct cxl_port *port =3D find_cxl_port_by_uport(&pdev->dev); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port; + } + } + pci_warn_once(pdev, "Error: Unsupported device type (%#x)", pci_pcie_type= (pdev)); + return NULL; +} + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; @@ -316,3 +343,52 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pd= ev, return PCI_ERS_RESULT_NEED_RESET; } EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); + +static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) +{ +} + +static void cxl_proto_err_work_fn(struct work_struct *work) +{ + struct cxl_proto_err_work_data wd; + + while (cxl_proto_err_kfifo_get(&wd)) { + struct pci_dev *pdev __free(pci_dev_put) =3D wd.pdev; + + if (!pdev) { + pr_err_ratelimited("NULL PCI device passed in AER-CXL KFIFO\n"); + continue; + } + + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + if (!port) { + pr_err_ratelimited("Failed to find parent Port device in CXL topology.\= n"); + continue; + } + guard(device)(&port->dev); + + cxl_handle_proto_error(&wd); + } +} + +static struct work_struct cxl_proto_err_work; +static DECLARE_WORK(cxl_proto_err_work, cxl_proto_err_work_fn); + +int cxl_ras_init(void) +{ + if (cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work)) + pr_err("Failed to initialize CXL RAS CPER\n"); + + cxl_register_proto_err_work(&cxl_proto_err_work); + + return 0; +} + +void cxl_ras_exit(void) +{ + cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); + cancel_work_sync(&cxl_cper_prot_err_work); + + cxl_unregister_proto_err_work(); + cancel_work_sync(&cxl_proto_err_work); +} diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c index 2189d3c6cef1..0f616f5fafcf 100644 --- a/drivers/pci/pcie/aer_cxl_vh.c +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -48,6 +48,7 @@ void cxl_forward_error(struct pci_dev *pdev, struct aer_e= rr_info *info) }; =20 guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema); + pci_dev_get(pdev); if (!cxl_proto_err_kfifo.work || !kfifo_put(&cxl_proto_err_kfifo.fifo, wd= )) { dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo error"); return; --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from PH8PR06CU001.outbound.protection.outlook.com (mail-westus3azon11012001.outbound.protection.outlook.com [40.107.209.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E82CA33509E; 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Wed, 14 Jan 2026 12:27:45 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 31/34] PCI: Introduce CXL Port protocol error handlers Date: Wed, 14 Jan 2026 12:20:52 -0600 Message-ID: <20260114182055.46029-32-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F2:EE_|SJ1PR12MB6267:EE_ X-MS-Office365-Filtering-Correlation-Id: 2686ead2-b9a9-4ed7-5bd5-08de539a9d5d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|7416014|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:27:46.2068 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2686ead2-b9a9-4ed7-5bd5-08de539a9d5d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6267 Content-Type: text/plain; charset="utf-8" Add CXL protocol error handlers for CXL Port devices (Root Ports, Downstream Ports, and Upstream Ports). Implement cxl_port_cor_error_detecte= d() and cxl_port_error_detected() to handle correctable and uncorrectable errors respectively. Introduce cxl_get_ras_base() to retrieve the cached RAS register base address for a given CXL port. This function supports CXL Root Ports, Downstream Ports, Upstream Ports, and Endpoints by returning their previously mapped RAS register addresses. Update the AER driver's is_cxl_error() to recognize CXL Port devices in addition to CXL Endpoints, as both now have CXL-specific error handlers. Future patch(es) will include port error handling changes to support Endpoint protocol errors. Signed-off-by: Terry Bowman Acked-by: Bjorn Helgaas --- Changes in v13->v14: - Add Dave Jiang's review-by - Update commit message & headline (Bjorn) - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to one line (Jonathan) - Remove cxl_walk_port() (Dan) - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is sufficient (Dan) - Remove device_lock_if() - Combined CE and UCE here (Terry) Changes in v12->v13: - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue patch (Terry) - Remove EP case in cxl_get_ras_base(), not used. (Terry) - Remove check for dport->dport_dev (Dave) - Remove whitespace (Terry) Changes in v11->v12: - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and pci_to_cxl_dev() - Change cxl_error_detected() -> cxl_cor_error_detected() - Remove NULL variable assignments - Replace bus_find_device() with find_cxl_port_by_uport() for upstream port searches. Changes in v10->v11: - None --- drivers/cxl/core/ras.c | 101 +++++++++++++++++++++++++++++++++- drivers/pci/pci.c | 1 + drivers/pci/pci.h | 2 - drivers/pci/pcie/aer.c | 1 + drivers/pci/pcie/aer_cxl_vh.c | 5 +- include/linux/aer.h | 2 + include/linux/pci.h | 2 + 7 files changed, 109 insertions(+), 5 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 0c640b84ad70..96ce85cc0a46 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -200,6 +200,67 @@ static struct cxl_port *get_cxl_port(struct pci_dev *p= dev) return NULL; } =20 +static void __iomem *cxl_get_ras_base(struct device *dev) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + { + struct cxl_dport *dport; + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port(&pdev->dev,= &dport); + + if (!dport) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return dport->regs.ras; + } + case PCI_EXP_TYPE_UPSTREAM: + { + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&p= dev->dev); + + if (!port) { + pci_err(pdev, "Failed to find the CXL device"); + return NULL; + } + return port->regs.ras; + } + } + dev_warn_once(dev, "Error: Unsupported device type (%#x)", pci_pcie_type(= pdev)); + return NULL; +} + +static pci_ers_result_t cxl_port_error_detected(struct device *dev); + +static void cxl_do_recovery(struct pci_dev *pdev) +{ + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + pci_ers_result_t status; + + if (!port) { + pci_err(pdev, "Failed to find the CXL device\n"); + return; + } + + status =3D cxl_port_error_detected(&pdev->dev); + if (status =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); + + /* + * If we have native control of AER, clear error status in the device + * that detected the error. If the platform retained control of AER, + * it is responsible for clearing this status. In that case, the + * signaling device may not even be visible to the OS. + */ + if (pcie_aer_is_native(pdev)) { + pcie_clear_device_status(pdev); + pci_aer_clear_nonfatal_status(pdev); + pci_aer_clear_fatal_status(pdev); + } +} + void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base) { void __iomem *addr; @@ -214,7 +275,10 @@ void cxl_handle_cor_ras(struct device *dev, u64 serial= , void __iomem *ras_base) return; writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); =20 - trace_cxl_aer_correctable_error(dev, status, serial); + if (is_cxl_memdev(dev)) + trace_cxl_aer_correctable_error(dev, status, serial); + else + trace_cxl_port_aer_correctable_error(dev, status); } =20 /* CXL spec rev3.0 8.2.4.16.1 */ @@ -265,12 +329,27 @@ bool cxl_handle_ras(struct device *dev, u64 serial, v= oid __iomem *ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); + + if (is_cxl_memdev(dev)) + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial); + else + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; } =20 +static void cxl_port_cor_error_detected(struct device *dev) +{ + cxl_handle_cor_ras(dev, 0, cxl_get_ras_base(dev)); +} + +static pci_ers_result_t cxl_port_error_detected(struct device *dev) +{ + return cxl_handle_ras(dev, 0, cxl_get_ras_base(dev)); +} + void cxl_cor_error_detected(struct pci_dev *pdev) { struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); @@ -346,6 +425,24 @@ EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); =20 static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) { + struct pci_dev *pdev =3D err_info->pdev; + + if (err_info->severity =3D=3D AER_CORRECTABLE) { + + if (!pcie_aer_is_native(pdev)) + return; + + if (pdev->aer_cap) + pci_clear_and_set_config_dword(pdev, + pdev->aer_cap + PCI_ERR_COR_STATUS, + 0, PCI_ERR_COR_INTERNAL); + + cxl_port_cor_error_detected(&pdev->dev); + + pcie_clear_device_status(pdev); + } else { + cxl_do_recovery(pdev); + } } =20 static void cxl_proto_err_work_fn(struct work_struct *work) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13dbb405dc31..b7bfefdaf990 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2248,6 +2248,7 @@ void pcie_clear_device_status(struct pci_dev *dev) pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); } +EXPORT_SYMBOL_GPL(pcie_clear_device_status); #endif =20 /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index dbc547db208a..8bb703524f52 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -229,7 +229,6 @@ void pci_refresh_power_state(struct pci_dev *dev); int pci_power_up(struct pci_dev *dev); void pci_disable_enabled_device(struct pci_dev *dev); int pci_finish_runtime_suspend(struct pci_dev *dev); -void pcie_clear_device_status(struct pci_dev *dev); void pcie_clear_root_pme_status(struct pci_dev *dev); bool pci_check_pme_status(struct pci_dev *dev); void pci_pme_wakeup_bus(struct pci_bus *bus); @@ -1196,7 +1195,6 @@ void pci_restore_aer_state(struct pci_dev *dev); static inline void pci_no_aer(void) { } static inline void pci_aer_init(struct pci_dev *d) { } static inline void pci_aer_exit(struct pci_dev *d) { } -static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINV= AL; } static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -= EINVAL; } static inline void pci_save_aer_state(struct pci_dev *dev) { } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index c2030d32a19c..dd7c49651612 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -298,6 +298,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) if (status) pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); } +EXPORT_SYMBOL_GPL(pci_aer_clear_fatal_status); =20 /** * pci_aer_raw_clear_status - Clear AER error registers. diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c index 0f616f5fafcf..aa69e504302f 100644 --- a/drivers/pci/pcie/aer_cxl_vh.c +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -34,7 +34,10 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_i= nfo *info) if (!info || !info->is_cxl) return false; =20 - if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + if ((pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ROOT_PORT) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_UPSTREAM) && + (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_DOWNSTREAM)) return false; =20 return is_aer_internal_error(info); diff --git a/include/linux/aer.h b/include/linux/aer.h index f351e41dd979..c1aef7859d0a 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -65,6 +65,7 @@ struct cxl_proto_err_work_data { =20 #if defined(CONFIG_PCIEAER) int pci_aer_clear_nonfatal_status(struct pci_dev *dev); +void pci_aer_clear_fatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); void pci_aer_unmask_internal_errors(struct pci_dev *dev); #else @@ -72,6 +73,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pc= i_dev *dev) { return -EINVAL; } +static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; 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Wed, 14 Jan 2026 12:27:56 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 32/34] cxl: Update Endpoint uncorrectable protocol error handling Date: Wed, 14 Jan 2026 12:20:53 -0600 Message-ID: <20260114182055.46029-33-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F1:EE_|BL1PR12MB5922:EE_ X-MS-Office365-Filtering-Correlation-Id: bea2b466-fd31-4ded-710a-08de539aa421 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|7416014|1800799024|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:27:57.5573 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bea2b466-fd31-4ded-710a-08de539aa421 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5922 Content-Type: text/plain; charset="utf-8" The CXL drivers must support handling Endpoint CXL and PCI uncorrectable (UCE) protocol errors. Update the drivers to support both. Introduce cxl_pci_error_detected() to handle PCI correctable errors, replacing cxl_error_detected(). Implement this new function to call the existing CXL Port uncorrectable handler, cxl_port_error_detected(). Update cxl_port_error_detected() for Endpoint handling. Take the CXL memory device lock, check for a valid driver, and handle restricted CXL device (RCH) if needed. This is the same sequence initially in cxl_error_detected(). But, the UCE handler's logic for the returned result errors is simplified because recovery will not be tried and instead UCE's will result in the CXL driver invoking system panic. Signed-off-by: Terry Bowman --- Changes in v13->v14: - Update commit headline (Bjorn) - Rename pci_error_detected()/pci_cor_error_detected() -> cxl_pci_error_detected/cxl_pci_cor_error_detected() (Jonathan) - Remove now-invalid comment in cxl_error_detected() (Jonathan) - Split into separate patches for UCE and CE (Terry) Changes in v12->v13: - Update commit messaqge (Terry) - Updated all the implementation and commit message. (Terry) - Refactored cxl_cor_error_detected()/cxl_error_detected() to remove pdev (Dave Jiang) Changes in v11->v12: - None Changes in v10->v11: - cxl_error_detected() - Change handlers' scoped_guard() to guard() (Jonath= an) - cxl_error_detected() - Remove extra line (Shiju) - Changes moved to core/ras.c (Terry) - cxl_error_detected(), remove 'ue' and return with function call. (Jonatha= n) - Remove extra space in documentation for PCI_ERS_RESULT_PANIC definition - Move #include "pci.h from cxl.h to core.h (Terry) - Remove unnecessary includes of cxl.h and core.h in mem.c (Terry) --- drivers/cxl/core/core.h | 9 ++-- drivers/cxl/core/ras.c | 92 +++++++++++++++++++---------------------- drivers/cxl/cxlpci.h | 15 ++++--- drivers/cxl/pci.c | 6 +-- 4 files changed, 60 insertions(+), 62 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 39324e1b8940..96c6cf478427 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -4,6 +4,7 @@ #ifndef __CXL_CORE_H__ #define __CXL_CORE_H__ =20 +#include #include #include =20 @@ -147,7 +148,7 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port= *port, #ifdef CONFIG_CXL_RAS int cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base= ); +pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, void __iom= em *ras_base); void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_= base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); @@ -158,11 +159,11 @@ static inline int cxl_ras_init(void) return 0; } static inline void cxl_ras_exit(void) { } -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) +static inline pci_ers_result_t cxl_handle_ras(struct device *dev, u64 seri= al, void __iomem *ras_base) { - return false; + return PCI_ERS_RESULT_NONE; } -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } +static inline void cxl_handle_cor_ras(struct device *dev, u64 serial, void= __iomem *ras_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 96ce85cc0a46..dc6e02d64821 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -218,6 +218,7 @@ static void __iomem *cxl_get_ras_base(struct device *de= v) return dport->regs.ras; } case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_ENDPOINT: { struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&p= dev->dev); =20 @@ -302,20 +303,22 @@ static void header_log_copy(void __iomem *ras_base, u= 32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) +pci_ers_result_t cxl_handle_ras(struct device *dev, u64 serial, void __iom= em *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; u32 status; u32 fe; =20 - if (!ras_base) - return false; + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); + return PCI_ERS_RESULT_NONE; + } =20 addr =3D ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status =3D readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) - return false; + return PCI_ERS_RESULT_NONE; =20 /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { @@ -337,7 +340,7 @@ bool cxl_handle_ras(struct device *dev, u64 serial, voi= d __iomem *ras_base) =20 writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 - return true; + return PCI_ERS_RESULT_PANIC; } =20 static void cxl_port_cor_error_detected(struct device *dev) @@ -347,7 +350,30 @@ static void cxl_port_cor_error_detected(struct device = *dev) =20 static pci_ers_result_t cxl_port_error_detected(struct device *dev) { - return cxl_handle_ras(dev, 0, cxl_get_ras_base(dev)); + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + u64 serial =3D 0; + + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + + guard(device)(&cxlmd->dev); + + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return PCI_ERS_RESULT_NONE; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + serial =3D cxlds->serial; + } + + return cxl_handle_ras(dev, serial, cxl_get_ras_base(dev)); } =20 void cxl_cor_error_detected(struct pci_dev *pdev) @@ -373,55 +399,21 @@ void cxl_cor_error_detected(struct pci_dev *pdev) } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + pci_ers_result_t rc; =20 - guard(device)(dev); + guard(device)(&port->dev); =20 - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return PCI_ERS_RESULT_DISCONNECT; - } + rc =3D cxl_port_error_detected(&pdev->dev); + if (rc =3D=3D PCI_ERS_RESULT_PANIC) + panic("CXL cachemem error."); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. - */ - ue =3D cxl_handle_ras(&cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); - - switch (state) { - case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } - return PCI_ERS_RESULT_CAN_RECOVER; - case pci_channel_io_frozen: - dev_warn(&pdev->dev, - "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - case pci_channel_io_perm_failure: - dev_warn(&pdev->dev, - "failure state error detected, request disconnect\n"); - return PCI_ERS_RESULT_DISCONNECT; - } - return PCI_ERS_RESULT_NEED_RESET; + return rc; } -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_pci_error_detected, "CXL"); =20 static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_inf= o) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 532506595d0f..f218b343e179 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -79,15 +79,20 @@ void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS void cxl_cor_error_detected(struct pci_dev *pdev); -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t error); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); void devm_cxl_port_ras_setup(struct cxl_port *port); +void __cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device= *host); +void __cxl_uport_init_ras_reporting(struct cxl_port *port, + struct device *host); +int __cxl_await_media_ready(struct cxl_dev_state *cxlds); +resource_size_t __cxl_rcd_component_reg_phys(struct device *dev, + struct cxl_dport *dport); #else static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } - -static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) { return PCI_ERS_RESULT_NONE; } diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index acb0eb2a13c3..ff741adc7c7f 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1051,8 +1051,8 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 -static const struct pci_error_handlers cxl_error_handlers =3D { - .error_detected =3D cxl_error_detected, +static const struct pci_error_handlers pci_error_handlers =3D { + .error_detected =3D cxl_pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, .cor_error_detected =3D cxl_cor_error_detected, @@ -1063,7 +1063,7 @@ static struct pci_driver cxl_pci_driver =3D { .name =3D KBUILD_MODNAME, .id_table =3D cxl_mem_pci_tbl, .probe =3D cxl_pci_probe, - .err_handler =3D &cxl_error_handlers, + .err_handler =3D &pci_error_handlers, .dev_groups =3D cxl_rcd_groups, .driver =3D { .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012019.outbound.protection.outlook.com [52.101.48.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 881E13358BB; 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Wed, 14 Jan 2026 12:28:12 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 33/34] cxl: Update Endpoint correctable protocol error handling Date: Wed, 14 Jan 2026 12:20:54 -0600 Message-ID: <20260114182055.46029-34-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|PH7PR12MB7233:EE_ X-MS-Office365-Filtering-Correlation-Id: 7ef17c50-4e6c-4773-f7d7-08de539aadb2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|1800799024|82310400026|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:28:13.6105 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ef17c50-4e6c-4773-f7d7-08de539aadb2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7233 Content-Type: text/plain; charset="utf-8" The CXL drivers must support handling Endpoint CXL and PCI correctable (CE) protocol errors. Update the driver to support both. Introduce cxl_pci_cor_error_detected() to handle PCI correctable errors, replacing cxl_cor_error_detected(). Implement this new function to call the existing CXL correctable handler, cxl_port_cor_error_detected(). Update cxl_port_cor_error_detected() for correct Endpoint handling. Take the CXL memory device lock, check for a valid driver, and handle Restricted CXL Device (RCD) if needed. Signed-off-by: Terry Bowman --- Changes in v13->v14: - New commit - Change cxl_cor_error_detected() parameter to &pdev->dev device from memdev device. (Terry) - Updated commit message (Terry) --- drivers/cxl/core/ras.c | 52 ++++++++++++++++++++++++++---------------- drivers/cxl/cxlpci.h | 6 +++-- drivers/cxl/pci.c | 2 +- 3 files changed, 37 insertions(+), 23 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index dc6e02d64821..427009a8a78a 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -267,8 +267,10 @@ void cxl_handle_cor_ras(struct device *dev, u64 serial= , void __iomem *ras_base) void __iomem *addr; u32 status; =20 - if (!ras_base) + if (!ras_base) { + dev_warn_once(dev, "CXL RAS register block is not mapped"); return; + } =20 addr =3D ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status =3D readl(addr); @@ -345,7 +347,30 @@ pci_ers_result_t cxl_handle_ras(struct device *dev, u6= 4 serial, void __iomem *ra =20 static void cxl_port_cor_error_detected(struct device *dev) { - cxl_handle_cor_ras(dev, 0, cxl_get_ras_base(dev)); + struct pci_dev *pdev =3D to_pci_dev(dev); + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); + u64 serial =3D 0; + + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + struct cxl_dev_state *cxlds =3D cxlmd->cxlds; + + guard(device)(&cxlmd->dev); + + if (!dev->driver) { + dev_warn(&pdev->dev, + "%s: memdev disabled, abort error handling\n", + dev_name(dev)); + return; + } + + if (cxlds->rcd) + cxl_handle_rdport_errors(cxlds); + + serial =3D cxlds->serial; + } + + cxl_handle_cor_ras(dev, serial, cxl_get_ras_base(dev)); } =20 static pci_ers_result_t cxl_port_error_detected(struct device *dev) @@ -376,28 +401,15 @@ static pci_ers_result_t cxl_port_error_detected(struc= t device *dev) return cxl_handle_ras(dev, serial, cxl_get_ras_base(dev)); } =20 -void cxl_cor_error_detected(struct pci_dev *pdev) +void cxl_pci_cor_error_detected(struct pci_dev *pdev) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlds->cxlmd->dev; - - guard(device)(dev); - - if (!dev->driver) { - dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); - return; - } + struct cxl_port *port __free(put_cxl_port) =3D get_cxl_port(pdev); =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); + guard(device)(&port->dev); =20 - cxl_handle_cor_ras(&cxlmd->dev, cxlds->serial, - cxlmd->endpoint->regs.ras); + cxl_port_cor_error_detected(&pdev->dev); } -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_pci_cor_error_detected, "CXL"); =20 pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error) diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index f218b343e179..3d70f9b4a193 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -78,7 +78,7 @@ struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS -void cxl_cor_error_detected(struct pci_dev *pdev); +void cxl_pci_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t error); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); @@ -90,7 +90,9 @@ int __cxl_await_media_ready(struct cxl_dev_state *cxlds); resource_size_t __cxl_rcd_component_reg_phys(struct device *dev, struct cxl_dport *dport); #else -static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } +static inline void cxl_pci_cor_error_detected(struct pci_dev *pdev) +{ +} static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ff741adc7c7f..328b4ea8dbc5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1055,7 +1055,7 @@ static const struct pci_error_handlers pci_error_hand= lers =3D { .error_detected =3D cxl_pci_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, - .cor_error_detected =3D cxl_cor_error_detected, + .cor_error_detected =3D cxl_pci_cor_error_detected, .reset_done =3D cxl_reset_done, }; =20 --=20 2.34.1 From nobody Sun Feb 8 13:09:16 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012002.outbound.protection.outlook.com [52.101.43.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 997B83358A3; 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Wed, 14 Jan 2026 12:28:28 -0600 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , CC: , , Subject: [PATCH v14 34/34] cxl: Enable CXL protocol errors during CXL Port probe Date: Wed, 14 Jan 2026 12:20:55 -0600 Message-ID: <20260114182055.46029-35-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114182055.46029-1-terry.bowman@amd.com> References: <20260114182055.46029-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F7:EE_|CH3PR12MB7643:EE_ X-MS-Office365-Filtering-Correlation-Id: ac6a6468-87ea-4ae5-a551-08de539ab761 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 18:28:29.7137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac6a6468-87ea-4ae5-a551-08de539ab761 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F7.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7643 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_err= ors(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham --- Changes in v13->v14: - Update commit title's prefix (Bjorn) Changes in v12->v13: - Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Te= rry) - Add Dave Jiang's and Ben's review-by Changes in v11->v12: - None Changes in v10->v11: - Added check for valid PCI devices in is_cxl_error() (Terry) - Removed check for RCiEP in cxl_handle_proto_err() and cxl_report_error_detected() (Terry) --- drivers/cxl/core/port.c | 2 ++ drivers/cxl/core/ras.c | 22 ++++++++++++++++++++++ drivers/cxl/cxlpci.h | 4 ++++ 3 files changed, 28 insertions(+) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 0bec10be5d56..588801c5d406 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1828,6 +1828,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) =20 rc =3D cxl_add_ep(dport, &cxlmd->dev); =20 + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev); + /* * If the endpoint already exists in the port's list, * that's ok, it was added on a previous pass. diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 427009a8a78a..e299eb50fbe4 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -117,6 +117,24 @@ static void cxl_cper_prot_err_work_fn(struct work_stru= ct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 +void cxl_unmask_proto_interrupts(struct device *dev) +{ + if (!dev || !dev_is_pci(dev)) + return; + + struct pci_dev *pdev __free(pci_dev_put) =3D pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} +EXPORT_SYMBOL_NS_GPL(cxl_unmask_proto_interrupts, "CXL"); + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -127,6 +145,8 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) else if (cxl_map_component_regs(map, &dport->regs.component, BIT(CXL_CM_CAP_CAP_ID_RAS))) dev_dbg(dev, "Failed to map RAS capability.\n"); + + cxl_unmask_proto_interrupts(dev); } =20 /** @@ -159,6 +179,8 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) if (cxl_map_component_regs(map, &port->regs, BIT(CXL_CM_CAP_CAP_ID_RAS))) dev_dbg(&port->dev, "Failed to map RAS capability\n"); + + cxl_unmask_proto_interrupts(port->uport_dev); } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 3d70f9b4a193..0c915c0bdfac 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -89,6 +89,7 @@ void __cxl_uport_init_ras_reporting(struct cxl_port *port, int __cxl_await_media_ready(struct cxl_dev_state *cxlds); resource_size_t __cxl_rcd_component_reg_phys(struct device *dev, struct cxl_dport *dport); +void cxl_unmask_proto_interrupts(struct device *dev); #else static inline void cxl_pci_cor_error_detected(struct pci_dev *pdev) { @@ -104,6 +105,9 @@ static inline void devm_cxl_dport_ras_setup(struct cxl_= dport *dport) static inline void devm_cxl_port_ras_setup(struct cxl_port *port) { } +static inline void cxl_unmask_proto_interrupts(struct device *dev) +{ +} #endif =20 int cxl_port_setup_regs(struct cxl_port *port, --=20 2.34.1