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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 17:36:18.5944 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a099397b-739b-431c-c733-08de53936d0b X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR10MB6738 Content-Type: text/plain; charset="utf-8" The TI K3 J721S2, J784S4 and J742S2 SoCs have a HSM (High Security Module) M4F core in the Wakeup Voltage Domain which could be used to run secure services like Authentication. Add Device Tree Node definitions for the HSM core in the respective SoC wakeup dtsi files. The HSM node is reserved to be loaded and booted by the early-stage bootloader. The firmware-name property is defined at the SoC level since the HSM is not a general-purpose remote core and boards are unlikely to use separate firmware. If needed in exceptional cases, board-specific device trees can override this property. Signed-off-by: Beleswar Padhi Reviewed-by: Bryan Brattlof --- v3: Changelog: [Nishanth]: 1. Use generic node name 'remoteproc' 2. Use label 'hsm' instead of 'hsm_m4fss' 3. Add a comment for separate SRAMs 4. Update firmware-name property to match existing naming conventions 5. Change status to 'reserved' and add a commment 6. Re-order bootph-pre-ram property before vendor properties 7. Update commit msg adding rationale for firmware-name in SoC.dtsi Link to v2: https://lore.kernel.org/all/20260106104755.948086-3-b-padhi@ti.com/ v2: Changelog: 1. None Link to v1: https://lore.kernel.org/all/20251231165102.950644-3-b-padhi@ti.com/ .../arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 17 +++++++++++++++++ .../arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi | 4 ++++ .../ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi | 17 +++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index fd01437726ab4..32ee8031cfcb6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -766,4 +766,21 @@ mcu_watchdog1: watchdog@40610000 { /* reserved for MCU_R5F0_1 */ status =3D "reserved"; }; + + hsm: remoteproc@43c00000 { + compatible =3D "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg =3D <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names =3D "sram0_0", "sram0_1", "sram1"; + resets =3D <&k3_reset 304 1>; + firmware-name =3D "j721s2-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci =3D <&sms>; + ti,sci-dev-id =3D <304>; + ti,sci-proc-ids =3D <0x80 0xff>; + /* reserved for early-stage bootloader */ + status =3D "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi index 61db2348d6a47..2f40afcfa67c4 100644 --- a/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j742s2-mcu-wakeup.dtsi @@ -15,3 +15,7 @@ &mcu_r5fss0_core0 { &mcu_r5fss0_core1 { firmware-name =3D "j742s2-mcu-r5f0_1-fw"; }; + +&hsm { + firmware-name =3D "j742s2-hsm-m4f-fw"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi= b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi index cc22bfb5f5996..df37902c963ff 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-mcu-wakeup-common.dtsi @@ -762,4 +762,21 @@ mcu_watchdog1: watchdog@40610000 { /* reserved for MCU_R5F0_1 */ status =3D "reserved"; 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Wed, 14 Jan 2026 11:36:04 -0600 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DFLE215.ent.ti.com (10.64.6.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 14 Jan 2026 11:36:04 -0600 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60EHZpkO040370; Wed, 14 Jan 2026 11:36:01 -0600 From: Beleswar Padhi To: , , , , , CC: , , , , , , Subject: [PATCH v3 2/2] arm64: dts: ti: k3-am62p-j722s-common-main: Add HSM M4F node Date: Wed, 14 Jan 2026 23:05:51 +0530 Message-ID: <20260114173551.2545088-3-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114173551.2545088-1-b-padhi@ti.com> References: <20260114173551.2545088-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E3:EE_|BN0PR10MB5205:EE_ X-MS-Office365-Filtering-Correlation-Id: 98fac0e3-aefe-4a16-db42-08de539370f2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|34020700016|376014|1800799024; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2026 17:36:25.2245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98fac0e3-aefe-4a16-db42-08de539370f2 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR10MB5205 Content-Type: text/plain; charset="utf-8" The TI K3 AM62P and J722S SoCs have a HSM (High Security Module) M4F core in the MAIN Voltage Domain which could be used to run secure services like Authentication. Add Device Tree Node definitions for the HSM core in the respective SoC common main dtsi file. The HSM node is reserved to be loaded and booted by the early-stage bootloader. The firmware-name property is defined at the SoC level since the HSM is not a general-purpose remote core and boards are unlikely to use separate firmware. If needed in exceptional cases, board-specific device trees can override this property. The corresponding reg ranges of HSM node has also been added to its parent node's (cbass_main bus) ranges property. Signed-off-by: Beleswar Padhi Reviewed-by: Bryan Brattlof Reviewed-by: Udit Kumar --- v3: Changelog: [Nishanth]: 1. Use generic node name 'remoteproc' 2. Use label 'hsm' instead of 'hsm_m4fss' 3. Add a comment for separate SRAMs 4. Update firmware-name property to match existing naming conventions 5. Change status to 'reserved' and add a commment 6. Re-order bootph-pre-ram property before vendor properties 7. Update commit msg adding rationale for firmware-name in SoC.dtsi Link to v2: https://lore.kernel.org/all/20260106104755.948086-4-b-padhi@ti.com/ v2: Changelog: 1. None Link to v1: https://lore.kernel.org/all/20251231165102.950644-4-b-padhi@ti.com/ .../boot/dts/ti/k3-am62p-j722s-common-main.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 + arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-j722s.dtsi | 1 + 4 files changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/= arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi index 3cf7c2b3ce2dd..0e1af2a69ca2e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi @@ -1117,4 +1117,21 @@ vpu: video-codec@30210000 { clocks =3D <&k3_clks 204 2>; power-domains =3D <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; + + hsm: remoteproc@43c00000 { + compatible =3D "ti,hsm-m4fss"; + /* contiguous regions but instantiated separately in HW */ + reg =3D <0x00 0x43c00000 0x00 0x20000>, + <0x00 0x43c20000 0x00 0x10000>, + <0x00 0x43c30000 0x00 0x10000>; + reg-names =3D "sram0_0", "sram0_1", "sram1"; + resets =3D <&k3_reset 225 1>; + firmware-name =3D "am62p-hsm-m4f-fw"; + bootph-pre-ram; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <225>; + ti,sci-proc-ids =3D <0x80 0xff>; + /* reserved for early-stage bootloader */ + status =3D "reserved"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/= k3-am62p.dtsi index e2c01328eb298..9d6266d6ddb82 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -96,6 +96,7 @@ cbass_main: bus@f0000 { <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core w= indow */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data = */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges = */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy confi= g */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 873415ec4fa37..9ee5d0c8ffd1e 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -429,6 +429,11 @@ &wkup_r5fss0_core0 { firmware-name =3D "j722s-wkup-r5f0_0-fw"; }; =20 +/* MAIN domain overrides */ +&hsm { + firmware-name =3D "j722s-hsm-m4f-fw"; +}; + &main_conf { serdes_ln_ctrl: mux-controller@4080 { compatible =3D "reg-mux"; diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/= k3-j722s.dtsi index c8b634c346779..059c65ece183f 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi @@ -173,6 +173,7 @@ cbass_main: bus@f0000 { <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core w= indow */ <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data = */ + <0x00 0x43c00000 0x00 0x43c00000 0x00 0x00040000>, /* HSM SRAM ranges = */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy confi= g */ <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */ --=20 2.34.1