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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee55d4279sm33909775e9.8.2026.01.14.07.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 07:14:20 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , devicetree , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stafford Horne , Linus Walleij , Bartosz Golaszewski , linux-gpio@vger.kernel.org Subject: [PATCH v5 1/6] dt-bindings: gpio-mmio: Correct opencores GPIO Date: Wed, 14 Jan 2026 15:13:10 +0000 Message-ID: <20260114151328.3827992-2-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260114151328.3827992-1-shorne@gmail.com> References: <20260114151328.3827992-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In commit f48b5e8bc2e1 ("dt-bindings: gpio-mmio: Add compatible string for opencores,gpio") we marked opencores,gpio to be allowed with brcm,bcm6345-gpio. This was wrong, opencores,gpio is not hardware equivalent to brcm,bcm6345-gpio. It has a different register map and is 8-bit vs braodcom which is 32-bit. Change opencores,gpio to be a separate compatible string for MMIO GPIO. Fixes: f48b5e8bc2e1 ("dt-bindings: gpio-mmio: Add compatible string for ope= ncores,gpio") Signed-off-by: Stafford Horne Reviewed-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- Since v4: - New patch. - Rebased old patch and rewrote commit message. .../devicetree/bindings/gpio/gpio-mmio.yaml | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Docume= ntation/devicetree/bindings/gpio/gpio-mmio.yaml index 7ee40b9bc562..a8823ca65e78 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -18,16 +18,12 @@ description: =20 properties: compatible: - oneOf: - - enum: - - brcm,bcm6345-gpio - - ni,169445-nand-gpio - - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO c= ontroller - - intel,ixp4xx-expansion-bus-mmio-gpio - - items: - - enum: - - opencores,gpio - - const: brcm,bcm6345-gpio + enum: + - brcm,bcm6345-gpio + - ni,169445-nand-gpio + - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO contr= oller + - intel,ixp4xx-expansion-bus-mmio-gpio + - opencores,gpio =20 big-endian: true =20 --=20 2.51.0 From nobody Sat Feb 7 17:56:03 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90D1B319610 for ; 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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee5914232sm40373305e9.14.2026.01.14.07.14.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 07:14:22 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , devicetree , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stafford Horne , Linus Walleij , Geert Uytterhoeven , Bartosz Golaszewski , linux-gpio@vger.kernel.org Subject: [PATCH v5 2/6] gpio: mmio: Add compatible for opencores GPIO Date: Wed, 14 Jan 2026 15:13:11 +0000 Message-ID: <20260114151328.3827992-3-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260114151328.3827992-1-shorne@gmail.com> References: <20260114151328.3827992-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On FPGA Development boards with GPIOs the OpenRISC architecture uses the opencores gpio verilog rtl. This is compatible with the gpio-mmio. Add the compatible string to allow probing this driver from the devicetree. Link: https://opencores.org/projects/gpio Signed-off-by: Stafford Horne Reviewed-by: Linus Walleij Reviewed-by: Geert Uytterhoeven --- Since v4: - No changes. Since v3: - Order this patch after the binding patch. - Add Reviewed-by's. Since v2: - New patch drivers/gpio/gpio-mmio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c index 5daf962b0323..edbcaad57d00 100644 --- a/drivers/gpio/gpio-mmio.c +++ b/drivers/gpio/gpio-mmio.c @@ -724,6 +724,7 @@ static const struct of_device_id gpio_mmio_of_match[] = =3D { { .compatible =3D "wd,mbl-gpio" }, { .compatible =3D "ni,169445-nand-gpio" }, { .compatible =3D "intel,ixp4xx-expansion-bus-mmio-gpio" }, + { .compatible =3D "opencores,gpio" }, { } }; MODULE_DEVICE_TABLE(of, gpio_mmio_of_match); --=20 2.51.0 From nobody Sat Feb 7 17:56:03 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8502A31A807 for ; Wed, 14 Jan 2026 15:14:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768403672; cv=none; b=ar9ceCrSoHZKPD+TaaFNtAVrKf3/n21rOi4w+7sW5h1GdgCc8HjWBcFXzA6F8io/tVIVmN9j3sWpxHOGClFJjdifPXYYAioRxJprv53VZLYPtXJQ+3U/06VFYM/zqzVHu2U4nhX1ZxYPrZ/leVzOR5Mu09XIdEP+b7zHCn1vzEA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768403672; c=relaxed/simple; bh=X+1J5PrXk/eYAdcNrlogIy51e8BwUbac79/oxhidec0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=irLsbIhN3YPGfaYBWtWSPXiKFBBJzV/Dni9uG/uQc1sZ5beVVwC/wCcbuFNfm6QJxuojKKOIdW5jZe+QvJ9MNRjQdBf2/qamX3kQlxJnAzKzATEf+4v4YJMH4mnqXjnR863d8CJ+DozVZOoDlOvaOLSkYBWaZuGUu2A8I/imqk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=RSPCCXSO; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="RSPCCXSO" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-47edd9024b1so11361975e9.3 for ; Wed, 14 Jan 2026 07:14:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768403668; x=1769008468; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1s6pH8NPA0ipZmaojy8syPtuylZJ77gPmpuGh7ODFgg=; b=RSPCCXSOAUDaZqmkmBRNvLm2rHJ7n1oVXsDgZkM4zV0xeWrGfxmUy+G9+H+l38qgKe mKMv1iSz+sbrZ6AouZztWLXOaboNVM/jYpX1N84bniKs8dE4SZ0VPeNAUAqpQr/uq6sE RjqgWv3auJQMxlUAVRDn/zv0+sEdku8PkpvWoWKvpiyMW5nLr4R7VBnQvts6aakr1a3M f5PEB4IllfQEqwWKKv0zPk0V+7PCd5Up6RcGUH1F0bt3Iv363qZJT64j58F9P7TsdtqH 5HxvGFqsJP7tTj9EBQ2zwLSXy84LXHtP9oT5Y2OeLGrCy1K4/Nfej3QN4hmMC2Pq4nzb xeFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768403668; x=1769008468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=1s6pH8NPA0ipZmaojy8syPtuylZJ77gPmpuGh7ODFgg=; b=I+pJdE9daNAyVIlDYMkTRR03swL3BoOtRX4tnonyb74KBou/iEu1DXTIX2yqsI1Z3P tVhp/engBaxGm+MRfgs7+RTUnpZshyR2qjimRgnxjYDGjq70b1zlrLXah9L52LyoGiWu /IV++b57f0nDxPkPMBp5XOLHcQQ503riIgADxW1PXY6XBSTEMe+v1PqF8JBNGRlwpDAU eT1kG6kkaYEBbcX9shvWCJ1JRLgqO2qCICMeutG4xkJL6TqtirGGcf3kYLjtoo4HkT5G 7UZ75Pl3l5d0t+twpcisJS59IurS1UxWatKPoXgCaSBLzwlm0TXYlS1MrmUb10SbIXVu 7Jxg== X-Gm-Message-State: AOJu0YyX9nU2apDP4PAc+XTlOmH6xhF+dWV/Iu1tR6/+fIwakKlhGyP8 GxkKkOHL+dVOnQfoQaZy6jexp4xs9d/ct897CEfHvqH3MYifkcgI8q8ksn7YkQ== X-Gm-Gg: AY/fxX4KqCO+FNPQDtive68o66sP8JebmEs1SlMgUQN969dGUX6nQqcYVu+YwuwJJPv EK1xuMYz3HAeCx57olU818T3CzQx1f+RpHWqBylGFVaqmN++SkWuByC5+qvspoIrXGP4ktBGsX3 CXAwPWVwBZLRVTRdKxHexZrI8xxGjY/PX4PyS2a7PoCnZPrQG77uN3I1N4eKduB3i2i1yUHppcT HaKAsKr8bx48xvNTz33fIB6YKu/1R41jaQYpSKmBdybMWEifLNRzlyyeLn260xiZF/Z3eZ4TCXm RNoFv7F9U30cIbwW6T8MVvOP3QIalcWIQ51eTCzU82zgQ55Hyr50MSrGRuUdGtf/4YZdY93Tjow WgUALMydS+iNcPf6jaZMqH907QdNM4+NfEyTxvGzt7tKxBv7xR50xAei6TTJwiq6pkHufPD0z+t jiifPLcFp7PnwrnMwnCNRG/t/n08qZeM2DHpXqh84x6NIbZOAmqt4rAsG4nnTNRXDz X-Received: by 2002:a05:600c:a318:b0:47e:e952:86c9 with SMTP id 5b1f17b1804b1-47ee952876fmr8858615e9.0.1768403668144; Wed, 14 Jan 2026 07:14:28 -0800 (PST) Received: from localhost (brnt-04-b2-v4wan-170138-cust2432.vm7.cable.virginm.net. [94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd0dacc5sm50466226f8f.5.2026.01.14.07.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 07:14:27 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , devicetree , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH v5 3/6] openrisc: dts: Add de0 nano config and devicetree Date: Wed, 14 Jan 2026 15:13:12 +0000 Message-ID: <20260114151328.3827992-4-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260114151328.3827992-1-shorne@gmail.com> References: <20260114151328.3827992-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The de0 nano from Terasic is an FPGA board that we use in the OpenRISC community to test OpenRISC configurations. Add a base configuration for the board that runs an OpenRISC CPU at 50Mhz with 32MB ram, UART for console and some GPIOs for LEDs and switches. There is an older version of this floating around that defines all of the hardware on the board including SPI's, flash devices, sram, ADCs etc. Eventually it would be good to get the full version upstream but for now I think a minimal board is good to start with. Link: https://openrisc.io/tutorials/de0_nano/ Link: https://github.com/olofk/de0_nano Signed-off-by: Stafford Horne --- Since v3: - No changes. Since v2: - Move leds block up to the top. - Remove unneeded "status" from gpio0. - Removed earlycon from de0-nano.dts. arch/openrisc/boot/dts/de0-nano-common.dtsi | 42 +++++++++++ arch/openrisc/boot/dts/de0-nano.dts | 54 ++++++++++++++ arch/openrisc/configs/de0_nano_defconfig | 79 +++++++++++++++++++++ 3 files changed, 175 insertions(+) create mode 100644 arch/openrisc/boot/dts/de0-nano-common.dtsi create mode 100644 arch/openrisc/boot/dts/de0-nano.dts create mode 100644 arch/openrisc/configs/de0_nano_defconfig diff --git a/arch/openrisc/boot/dts/de0-nano-common.dtsi b/arch/openrisc/bo= ot/dts/de0-nano-common.dtsi new file mode 100644 index 000000000000..02e329e28e33 --- /dev/null +++ b/arch/openrisc/boot/dts/de0-nano-common.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +/ { + leds0: leds { + compatible =3D "gpio-leds"; + + led-heartbeat { + gpios =3D <&gpio0 0 GPIO_ACTIVE_HIGH>; + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + linux,default-trigger =3D "heartbeat"; + label =3D "heartbeat"; + }; + }; + + memory@0 { + device_type =3D "memory"; + reg =3D <0x00000000 0x02000000>; + }; + + /* 8 Green LEDs */ + gpio0: gpio@91000000 { + compatible =3D "opencores,gpio"; + reg =3D <0x91000000 0x1>, <0x91000001 0x1>; + reg-names =3D "dat", "dirout"; + gpio-controller; + #gpio-cells =3D <2>; + }; + + /* 4 DIP Switches */ + gpio1: gpio@92000000 { + compatible =3D "opencores,gpio"; + reg =3D <0x92000000 0x1>, <0x92000001 0x1>; + reg-names =3D "dat", "dirout"; + gpio-controller; + #gpio-cells =3D <2>; + status =3D "disabled"; + }; +}; diff --git a/arch/openrisc/boot/dts/de0-nano.dts b/arch/openrisc/boot/dts/d= e0-nano.dts new file mode 100644 index 000000000000..b5b854e7e8b4 --- /dev/null +++ b/arch/openrisc/boot/dts/de0-nano.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "de0-nano-common.dtsi" + +/ { + model =3D "Terasic DE0 Nano"; + compatible =3D "opencores,or1ksim"; + #address-cells =3D <1>; + #size-cells =3D <1>; + interrupt-parent =3D <&pic>; + + aliases { + uart0 =3D &serial0; + }; + + chosen { + stdout-path =3D "uart0:115200"; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu@0 { + compatible =3D "opencores,or1200-rtlsvn481"; + reg =3D <0>; + clock-frequency =3D <50000000>; + }; + }; + + /* + * OR1K PIC is built into CPU and accessed via special purpose + * registers. It is not addressable and, hence, has no 'reg' + * property. + */ + pic: pic { + compatible =3D "opencores,or1k-pic"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + + serial0: serial@90000000 { + compatible =3D "opencores,uart16550-rtlsvn105", "ns16550a"; + reg =3D <0x90000000 0x100>; + interrupts =3D <2>; + clock-frequency =3D <50000000>; + }; +}; + +&gpio1 { + status =3D "okay"; +}; diff --git a/arch/openrisc/configs/de0_nano_defconfig b/arch/openrisc/confi= gs/de0_nano_defconfig new file mode 100644 index 000000000000..bc63905f9cd8 --- /dev/null +++ b/arch/openrisc/configs/de0_nano_defconfig @@ -0,0 +1,79 @@ +CONFIG_SYSVIPC=3Dy +CONFIG_NO_HZ=3Dy +CONFIG_LOG_BUF_SHIFT=3D14 +CONFIG_BLK_DEV_INITRD=3Dy +# CONFIG_RD_GZIP is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +CONFIG_EXPERT=3Dy +# CONFIG_EPOLL is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_BUILTIN_DTB_NAME=3D"de0-nano" +# CONFIG_FPU is not set +CONFIG_HZ_100=3Dy +# CONFIG_BLOCK is not set +CONFIG_SLUB_TINY=3Dy +# CONFIG_COMPAT_BRK is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_NET=3Dy +CONFIG_UNIX=3Dy +CONFIG_UNIX_DIAG=3Dy +CONFIG_INET=3Dy +CONFIG_IP_MULTICAST=3Dy +CONFIG_INET_UDP_DIAG=3Dy +CONFIG_INET_RAW_DIAG=3Dy +CONFIG_INET_DIAG_DESTROY=3Dy +# CONFIG_IPV6 is not set +CONFIG_DEVTMPFS=3Dy +CONFIG_DEVTMPFS_MOUNT=3Dy +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=3Dy +CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_OF_PLATFORM=3Dy +# CONFIG_HW_RANDOM is not set +CONFIG_PPS=3Dy +CONFIG_GPIO_SYSFS=3Dy +# CONFIG_GPIO_SYSFS_LEGACY is not set +CONFIG_GPIO_GENERIC_PLATFORM=3Dy +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_NEW_LEDS=3Dy +CONFIG_LEDS_CLASS=3Dy +CONFIG_LEDS_GPIO=3Dy +CONFIG_LEDS_TRIGGERS=3Dy +CONFIG_LEDS_TRIGGER_TIMER=3Dy +CONFIG_LEDS_TRIGGER_ONESHOT=3Dy +CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy +CONFIG_LEDS_TRIGGER_CPU=3Dy +CONFIG_LEDS_TRIGGER_ACTIVITY=3Dy +CONFIG_LEDS_TRIGGER_GPIO=3Dy +CONFIG_LEDS_TRIGGER_DEFAULT_ON=3Dy +CONFIG_LEDS_TRIGGER_TRANSIENT=3Dy +CONFIG_LEDS_TRIGGER_PANIC=3Dy +CONFIG_LEDS_TRIGGER_NETDEV=3Dy +CONFIG_LEDS_TRIGGER_PATTERN=3Dy +CONFIG_LEDS_TRIGGER_TTY=3Dy +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=3Dy +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_ARM64 is not set +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_RISCV is not set +CONFIG_PRINTK_TIME=3Dy +# CONFIG_DEBUG_MISC is not set +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set --=20 2.51.0 From nobody Sat Feb 7 17:56:03 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3266031AF2C for ; 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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee7d58f09sm21659865e9.12.2026.01.14.07.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 07:14:31 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , devicetree , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stafford Horne , Thomas Gleixner , Jonas Bonn , Stefan Kristiansson Subject: [PATCH v5 4/6] openrisc: Fix IPIs on simple multicore systems Date: Wed, 14 Jan 2026 15:13:13 +0000 Message-ID: <20260114151328.3827992-5-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260114151328.3827992-1-shorne@gmail.com> References: <20260114151328.3827992-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit c05671846451 ("openrisc: sleep instead of spin on secondary wait") fixed OpenRISC SMP Linux for QEMU. However, stability was never achieved on FPGA development boards. This is because the above patch has a step to unmask IPIs on non-boot cpu's but on hardware without power management, IPIs remain masked. This meant that IPI's were never actually working on the simple SMP systems we run on development boards. The systems booted but stability was very suspect. Add the ability to unmask IPI's on the non-boot cores. This is done by making the OMPIC IRQs proper percpu IRQs. We can then use the enabled_percpu_irq() to unmask IRQ on the non-boot cpus. Update the or1k PIC driver to use a flow handler that can switch between percpu and the configured level or edge flow handlers at runtime. This mechanism is inspired by that done in the J-Core AIC driver. Signed-off-by: Stafford Horne Acked-by: Thomas Gleixner --- Since v4: - Added acked-by. arch/openrisc/include/asm/smp.h | 3 ++- arch/openrisc/kernel/smp.c | 22 +++++++++++++++++++++- drivers/irqchip/irq-ompic.c | 15 +++++++++++---- drivers/irqchip/irq-or1k-pic.c | 27 ++++++++++++++++++++++++++- 4 files changed, 60 insertions(+), 7 deletions(-) diff --git a/arch/openrisc/include/asm/smp.h b/arch/openrisc/include/asm/sm= p.h index e21d2f12b5b6..007296f160ef 100644 --- a/arch/openrisc/include/asm/smp.h +++ b/arch/openrisc/include/asm/smp.h @@ -20,7 +20,8 @@ extern void smp_init_cpus(void); extern void arch_send_call_function_single_ipi(int cpu); extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); =20 -extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned i= nt)); +extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned i= nt), + unsigned int irq); extern void handle_IPI(unsigned int ipi_msg); =20 #endif /* __ASM_OPENRISC_SMP_H */ diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c index 86da4bc5ee0b..040ca201b692 100644 --- a/arch/openrisc/kernel/smp.c +++ b/arch/openrisc/kernel/smp.c @@ -13,6 +13,7 @@ =20 #include #include +#include #include #include #include @@ -25,6 +26,7 @@ =20 asmlinkage __init void secondary_start_kernel(void); =20 +static unsigned int ipi_irq __ro_after_init; static void (*smp_cross_call)(const struct cpumask *, unsigned int); =20 unsigned long secondary_release =3D -1; @@ -39,6 +41,14 @@ enum ipi_msg_type { =20 static DEFINE_SPINLOCK(boot_lock); =20 +static void or1k_ipi_enable(void) +{ + if (WARN_ON_ONCE(!ipi_irq)) + return; + + enable_percpu_irq(ipi_irq, 0); +} + static void boot_secondary(unsigned int cpu, struct task_struct *idle) { /* @@ -136,6 +146,7 @@ asmlinkage __init void secondary_start_kernel(void) complete(&cpu_running); =20 synchronise_count_slave(cpu); + or1k_ipi_enable(); set_cpu_online(cpu, true); =20 local_irq_enable(); @@ -195,9 +206,18 @@ void smp_send_stop(void) smp_call_function(stop_this_cpu, NULL, 0); } =20 -void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned= int)) +void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned= int), + unsigned int irq) { + if (WARN_ON(ipi_irq)) + return; + smp_cross_call =3D fn; + + ipi_irq =3D irq; + + /* Enabled IPIs for boot CPU immediately */ + or1k_ipi_enable(); } =20 void arch_send_call_function_single_ipi(int cpu) diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c index e66ef4373b1e..f0e0b435bb1d 100644 --- a/drivers/irqchip/irq-ompic.c +++ b/drivers/irqchip/irq-ompic.c @@ -84,6 +84,8 @@ DEFINE_PER_CPU(unsigned long, ops); =20 static void __iomem *ompic_base; =20 +static DEFINE_PER_CPU_READ_MOSTLY(int, ipi_dummy_dev); + static inline u32 ompic_readreg(void __iomem *base, loff_t offset) { return ioread32be(base + offset); @@ -183,12 +185,17 @@ static int __init ompic_of_init(struct device_node *n= ode, goto out_unmap; } =20 - ret =3D request_irq(irq, ompic_ipi_handler, IRQF_PERCPU, - "ompic_ipi", NULL); - if (ret) + irq_set_percpu_devid(irq); + ret =3D request_percpu_irq(irq, ompic_ipi_handler, "ompic_ipi", + &ipi_dummy_dev); + + if (ret) { + pr_err("ompic: failed to request irq %d, error: %d", + irq, ret); goto out_irq_disp; + } =20 - set_smp_cross_call(ompic_raise_softirq); + set_smp_cross_call(ompic_raise_softirq, irq); =20 return 0; =20 diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c index 48126067c54b..73dc99c71d40 100644 --- a/drivers/irqchip/irq-or1k-pic.c +++ b/drivers/irqchip/irq-or1k-pic.c @@ -118,11 +118,36 @@ static void or1k_pic_handle_irq(struct pt_regs *regs) generic_handle_domain_irq(root_domain, irq); } =20 +/* + * The OR1K PIC is a cpu-local interrupt controller and does not distingui= sh or + * use distinct irq number ranges for per-cpu event interrupts (IPI). Since + * information to determine whether a particular irq number should be trea= ted as + * per-cpu is not available at mapping time, we use a wrapper handler func= tion + * which chooses the right handler at runtime based on whether IRQF_PERCPU= was + * used when requesting the irq. Borrowed from J-Core AIC. + */ +static void or1k_irq_flow_handler(struct irq_desc *desc) +{ +#ifdef CONFIG_SMP + struct irq_data *data =3D irq_desc_get_irq_data(desc); + struct or1k_pic_dev *pic =3D data->domain->host_data; + + if (irqd_is_per_cpu(data)) + handle_percpu_devid_irq(desc); + else + pic->handle(desc); +#endif +} + static int or1k_map(struct irq_domain *d, unsigned int irq, irq_hw_number_= t hw) { struct or1k_pic_dev *pic =3D d->host_data; =20 - irq_set_chip_and_handler(irq, &pic->chip, pic->handle); + if (IS_ENABLED(CONFIG_SMP)) + irq_set_chip_and_handler(irq, &pic->chip, or1k_irq_flow_handler); + else + irq_set_chip_and_handler(irq, &pic->chip, pic->handle); + irq_set_status_flags(irq, pic->flags); =20 return 0; --=20 2.51.0 From nobody Sat Feb 7 17:56:03 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C528031A07B for ; Wed, 14 Jan 2026 15:14:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768403679; cv=none; b=b//+uuJEzir10ldWS/cLo7z7kCxRL7WDFJp95xBSpWTsLylKTOi2G+pgCvBK/5UUcBxLdOk6D6Gn4Mb26zLu7muf6AlYUUQ2pDwcmGx1lV/Q33ZDZO9HORcpaQ2wPYmxQlg4EGQV7AfrfH7Ma29dXapDzCDYnvEMs7CgqwfEtpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768403679; c=relaxed/simple; bh=s41epkAbLG9smlbYYXWvYNaWVozGaFQ8TXpu/2hzAWw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uwBCMb8V0XkoYO3dqyFs2odBMydJleWlXZXX05IvS8jN825fTIRmFiKrxvPmFmvwyYj75ESL60caUROCphPH6GHy3Nc4HyVZvN4IhDBdDNJOoAwPSmvXOB0vzYMQklhifGvJLPYde+m1lSDRSmoWe9U5ZU6ptwj3ZSRBcSJaPVA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=jN4V0PmJ; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="jN4V0PmJ" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-47ee9817a35so972075e9.1 for ; Wed, 14 Jan 2026 07:14:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768403675; x=1769008475; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3u+3JeZcHRgFBFE83J1Rhnm4t9otRBPxkyt04fpaFbg=; b=jN4V0PmJfqQOdvtqfPnuxJkA6A7Zd7k3gWcEPAKty+pTAimGiQ479dV4XQSN79eonG ld0M7tzo8vR3Yp71p8b130brZRzrhtYtoiE1x2ETzTCwurOVt/hQY9ARgvhqLBkP/+Uq nDtZ5HKnHq7H6X2cOBJRWPWuP2RSMiO1Zw2TFcS6psauyxUp4e0AfPIHm1nogaaNX9gZ BaSNxlBDUPstGIOebH5ml917sh/6SZnn0wH9RRdYCQSV8f0tSkXzqqyFq+Th5hUX2kJJ iDOsEu1SI+Uk/UwaKDIfVzgo1j0slHF/CZUebNKg8jwQw5hGp82glEcVihy9ECHuSIdU 9JWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768403675; x=1769008475; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=3u+3JeZcHRgFBFE83J1Rhnm4t9otRBPxkyt04fpaFbg=; b=aVVY8Gfs7dokR/QN0wJH7I8j15J9ppHCJLTQ1IaElJ9wfx+0JhzFr8vsiaasJrbWLM vl4zGciKyxtpvtUBEmUiL/9suec0wH0im/RpVyoGrMqne//82nBUQiEQYXTuh11dFFZL ZQWV8TQ1pGzSP3JKsu5YYZJD4yjXMmmTs666Q7WSF/iT5CcikHbMN15PZZz0EU8xsEPx IWjCi+MnIm6s2wuRyWr/nmNgB3lom8h/jeLBm/sm/FftypJiYamBjQDJSOzX22teAqWH 5Mz4z7gCFD1s3aBtmQGPN9Q5IgKCMbu78VEhd0rXd6yPCWoydO8WddmI5XbYQJk6Yya7 gaVg== X-Gm-Message-State: AOJu0Ywb+lDrjG8ScZgAipgphnyv2qfTCEoLNSsfpM7pbQvyBf1W+hgk 8g1qR5o8BdQcdP/ZApthKKvt/WTrYw2Ez/l+X6kzuo5PTX+7dVlMfxnkq+4iJQ== X-Gm-Gg: AY/fxX7zK4NAMk67ndbFkFZTXDOP65Kat1Gq9j/XdY6ziRlmrfLJnPA+lozGr/sIsTX HujWGEC7GHhewTYoVkigcxmppTZHKWrv+9OX5hYZHjqLa5x5AGh/qWzWNzXXPbiOmrvFpzMsIjF 1581E1mSB53izXF77tJYfdTwVhJlO1lKFa5r2c7M/1O68sWwAo6w2sjsbv2Sd21+DwNL3iv+ZV2 RThmj60Ctqxt++/cTW3mMQGaZPFraw9uORLEwWQjoRGOJ8XIbJm/qkhTAnPpz/BXUisrq3F5B5x EnL6kcyZ3qUEiM3MVzVIEXIe7YQtG8514WgiKBxcFRkbkgnjoDt56z/TZQ1LT7JBbdLrZHxdTi3 mOF26YUNGVxmcQPpvE+RzYrh4rXqszxwhm2HBcyutwC/p/7Nx8fO44taYiJhtsOEtcfjIAbQBWd jl6tTw2in8EhWsMYjeE9lK/6pnuAGxmuWZj+DeCusUuHLNWkB2+CwwbZ2pC1/uEZjJ X-Received: by 2002:a05:600c:c16e:b0:47e:e076:c7a5 with SMTP id 5b1f17b1804b1-47ee32fd6b9mr31039625e9.11.1768403675446; Wed, 14 Jan 2026 07:14:35 -0800 (PST) Received: from localhost (brnt-04-b2-v4wan-170138-cust2432.vm7.cable.virginm.net. [94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee55c547dsm32361355e9.4.2026.01.14.07.14.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 07:14:34 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , devicetree , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stafford Horne , Jonas Bonn , Stefan Kristiansson , Masahiro Yamada Subject: [PATCH v5 5/6] openrisc: dts: Split simple smp dts to dts and dtsi Date: Wed, 14 Jan 2026 15:13:14 +0000 Message-ID: <20260114151328.3827992-6-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260114151328.3827992-1-shorne@gmail.com> References: <20260114151328.3827992-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Split out the common memory, CPU and PIC definitions of the simple SMP system to a DTSI file which we will later use for our De0 Nano multicore board device tree. We also take this opportunity to swich underscores to dashes as that seems to be the more common convention for DTS files. Signed-off-by: Stafford Horne --- Since v3: - No changes. Since v2: - Sort blocks alphabetically. arch/openrisc/boot/dts/simple-smp.dts | 25 +++++++++++++++++++ .../dts/{simple_smp.dts =3D> simple-smp.dtsi} | 11 ++++---- arch/openrisc/configs/simple_smp_defconfig | 2 +- 3 files changed, 31 insertions(+), 7 deletions(-) create mode 100644 arch/openrisc/boot/dts/simple-smp.dts rename arch/openrisc/boot/dts/{simple_smp.dts =3D> simple-smp.dtsi} (90%) diff --git a/arch/openrisc/boot/dts/simple-smp.dts b/arch/openrisc/boot/dts= /simple-smp.dts new file mode 100644 index 000000000000..01cf219e6aac --- /dev/null +++ b/arch/openrisc/boot/dts/simple-smp.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +/dts-v1/; + +#include "simple-smp.dtsi" + +/ { + model =3D "Simple SMP Board"; +}; + +&cpu0 { + clock-frequency =3D <20000000>; +}; + +&cpu1 { + clock-frequency =3D <20000000>; +}; + +&enet0 { + status =3D "okay"; +}; + +&serial0 { + clock-frequency =3D <20000000>; +}; diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts= /simple-smp.dtsi similarity index 90% rename from arch/openrisc/boot/dts/simple_smp.dts rename to arch/openrisc/boot/dts/simple-smp.dtsi index 71af0e117bfe..42d6eda33b71 100644 --- a/arch/openrisc/boot/dts/simple_smp.dts +++ b/arch/openrisc/boot/dts/simple-smp.dtsi @@ -1,4 +1,3 @@ -/dts-v1/; / { compatible =3D "opencores,or1ksim"; #address-cells =3D <1>; @@ -22,15 +21,15 @@ memory@0 { cpus { #address-cells =3D <1>; #size-cells =3D <0>; - cpu@0 { + + cpu0: cpu@0 { compatible =3D "opencores,or1200-rtlsvn481"; reg =3D <0>; - clock-frequency =3D <20000000>; }; - cpu@1 { + + cpu1: cpu@1 { compatible =3D "opencores,or1200-rtlsvn481"; reg =3D <1>; - clock-frequency =3D <20000000>; }; }; =20 @@ -57,7 +56,6 @@ serial0: serial@90000000 { compatible =3D "opencores,uart16550-rtlsvn105", "ns16550a"; reg =3D <0x90000000 0x100>; interrupts =3D <2>; - clock-frequency =3D <20000000>; }; =20 enet0: ethoc@92000000 { @@ -65,5 +63,6 @@ enet0: ethoc@92000000 { reg =3D <0x92000000 0x800>; interrupts =3D <4>; big-endian; + status =3D "disabled"; }; }; diff --git a/arch/openrisc/configs/simple_smp_defconfig b/arch/openrisc/con= figs/simple_smp_defconfig index 6008e824d31c..db77c795225e 100644 --- a/arch/openrisc/configs/simple_smp_defconfig +++ b/arch/openrisc/configs/simple_smp_defconfig @@ -20,7 +20,7 @@ CONFIG_SLUB=3Dy CONFIG_SLUB_TINY=3Dy CONFIG_MODULES=3Dy # CONFIG_BLOCK is not set -CONFIG_BUILTIN_DTB_NAME=3D"simple_smp" +CONFIG_BUILTIN_DTB_NAME=3D"simple-smp" CONFIG_SMP=3Dy CONFIG_HZ_100=3Dy CONFIG_OPENRISC_HAVE_SHADOW_GPRS=3Dy --=20 2.51.0 From nobody Sat Feb 7 17:56:03 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D3061EF09B for ; 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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57b0749sm36864255e9.7.2026.01.14.07.14.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 07:14:40 -0800 (PST) From: Stafford Horne To: LKML Cc: Linux OpenRISC , devicetree , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stafford Horne , Jonas Bonn , Stefan Kristiansson Subject: [PATCH v5 6/6] openrisc: dts: Add de0 nano multicore config and devicetree Date: Wed, 14 Jan 2026 15:13:15 +0000 Message-ID: <20260114151328.3827992-7-shorne@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260114151328.3827992-1-shorne@gmail.com> References: <20260114151328.3827992-1-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a multicore configuration for the Terasic de0 nano FPGA development board. This SoC runs 2 OpenRISC CPUs at 50Mhz with 32MB ram, UART for console and GPIOs for LEDs. This FPGA SoC is based on the simple-smp reference board and brings in devices from the de0 nano common DTSI file. A default config is added that brings together the device tree and driver setup. Link: https://github.com/stffrdhrn/de0_nano-multicore Signed-off-by: Stafford Horne --- arch/openrisc/boot/dts/de0-nano-multicore.dts | 25 +++++ .../configs/de0_nano_multicore_defconfig | 92 +++++++++++++++++++ 2 files changed, 117 insertions(+) create mode 100644 arch/openrisc/boot/dts/de0-nano-multicore.dts create mode 100644 arch/openrisc/configs/de0_nano_multicore_defconfig diff --git a/arch/openrisc/boot/dts/de0-nano-multicore.dts b/arch/openrisc/= boot/dts/de0-nano-multicore.dts new file mode 100644 index 000000000000..b6cf286afaa4 --- /dev/null +++ b/arch/openrisc/boot/dts/de0-nano-multicore.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include + +/dts-v1/; + +#include "simple-smp.dtsi" +#include "de0-nano-common.dtsi" + +/ { + model =3D "Terasic DE0 Nano - Multicore"; +}; + +&cpu0 { + clock-frequency =3D <50000000>; +}; + +&cpu1 { + clock-frequency =3D <50000000>; +}; + +&serial0 { + clock-frequency =3D <50000000>; +}; diff --git a/arch/openrisc/configs/de0_nano_multicore_defconfig b/arch/open= risc/configs/de0_nano_multicore_defconfig new file mode 100644 index 000000000000..d33b1226e09c --- /dev/null +++ b/arch/openrisc/configs/de0_nano_multicore_defconfig @@ -0,0 +1,92 @@ +CONFIG_LOCALVERSION=3D"-de0nano-smp" +CONFIG_SYSVIPC=3Dy +CONFIG_POSIX_MQUEUE=3Dy +CONFIG_NO_HZ=3Dy +CONFIG_LOG_BUF_SHIFT=3D14 +CONFIG_BLK_DEV_INITRD=3Dy +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_EXPERT=3Dy +# CONFIG_EPOLL is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_AIO is not set +CONFIG_KALLSYMS_ALL=3Dy +CONFIG_DCACHE_WRITETHROUGH=3Dy +CONFIG_BUILTIN_DTB_NAME=3D"de0-nano-multicore" +CONFIG_OPENRISC_HAVE_INST_CMOV=3Dy +CONFIG_SMP=3Dy +CONFIG_HZ_100=3Dy +CONFIG_JUMP_LABEL=3Dy +# CONFIG_BLOCK is not set +CONFIG_SLUB_TINY=3Dy +# CONFIG_COMPAT_BRK is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_NET=3Dy +CONFIG_PACKET=3Dy +CONFIG_UNIX=3Dy +CONFIG_UNIX_DIAG=3Dy +CONFIG_INET=3Dy +CONFIG_IP_MULTICAST=3Dy +CONFIG_TCP_CONG_ADVANCED=3Dy +# CONFIG_TCP_CONG_BIC is not set +# CONFIG_TCP_CONG_CUBIC is not set +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_IPV6 is not set +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=3Dy +CONFIG_DEVTMPFS_MOUNT=3Dy +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +# CONFIG_FW_LOADER is not set +CONFIG_NETDEVICES=3Dy +CONFIG_ETHOC=3Dy +CONFIG_MICREL_PHY=3Dy +# CONFIG_WLAN is not set +# CONFIG_INPUT is not set +# CONFIG_SERIO is not set +# CONFIG_VT is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=3Dy +CONFIG_SERIAL_8250_CONSOLE=3Dy +CONFIG_SERIAL_OF_PLATFORM=3Dy +# CONFIG_HW_RANDOM is not set +CONFIG_GPIO_SYSFS=3Dy +# CONFIG_GPIO_CDEV_V1 is not set +CONFIG_GPIO_GENERIC_PLATFORM=3Dy +# CONFIG_HWMON is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_NEW_LEDS=3Dy +CONFIG_LEDS_CLASS=3Dy +CONFIG_LEDS_GPIO=3Dy +CONFIG_LEDS_TRIGGERS=3Dy +CONFIG_LEDS_TRIGGER_TIMER=3Dy +CONFIG_LEDS_TRIGGER_ONESHOT=3Dy +CONFIG_LEDS_TRIGGER_HEARTBEAT=3Dy +CONFIG_LEDS_TRIGGER_CPU=3Dy +CONFIG_LEDS_TRIGGER_ACTIVITY=3Dy +CONFIG_LEDS_TRIGGER_GPIO=3Dy +CONFIG_LEDS_TRIGGER_DEFAULT_ON=3Dy +CONFIG_LEDS_TRIGGER_TRANSIENT=3Dy +CONFIG_LEDS_TRIGGER_PANIC=3Dy +CONFIG_LEDS_TRIGGER_NETDEV=3Dy +CONFIG_LEDS_TRIGGER_PATTERN=3Dy +CONFIG_LEDS_TRIGGER_TTY=3Dy +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=3Dy +CONFIG_NFS_FS=3Dy +CONFIG_XZ_DEC=3Dy +CONFIG_PRINTK_TIME=3Dy +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=3Dy +CONFIG_GDB_SCRIPTS=3Dy +CONFIG_VMLINUX_MAP=3Dy +CONFIG_HARDLOCKUP_DETECTOR=3Dy +CONFIG_WQ_WATCHDOG=3Dy +CONFIG_WQ_CPU_INTENSIVE_REPORT=3Dy +CONFIG_STACKTRACE=3Dy +CONFIG_RCU_CPU_STALL_CPUTIME=3Dy +# CONFIG_RCU_TRACE is not set --=20 2.51.0