From nobody Sat Feb 7 06:13:55 2026 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 097BF305066 for ; Wed, 14 Jan 2026 14:52:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768402381; cv=none; b=VvKAYjC9CJ2mdJ+MSgJLl7oXygEcS8kJ450DFQr0nm6bzgRMlpoX+Us+w44Gx6tWuCQPTos2ExMNXXf41G4jVsBYDNtdxrRBIlgHVeFSmFEkGzD2YkoTkAphAkE6Wmc0M5F8QSIsAvZkznPXV7vgsndUllmI69/KcHjK9IWRqv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768402381; c=relaxed/simple; bh=6EcsH4NJZuMHhhsCJiB1QN03+YEdExhWKAvJd5QzkRw=; h=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Content-Type; b=GbnjsESf4C7W7WNwojbxDSoemzyvyPuzpOwcLPSERsComtW+xkhjzeDLhNMDIsYwahkA6gikU5OUZY/xdKV4zBTfqehEDvxj9Vt6B7Cpfd0RJvOjIwxzvl823dRQhSLgI08U8IKEuOe+STNE/ODA1HGz5G0cV0js8wxCfVlrnDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--lucaswei.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=ljd1EdfI; arc=none smtp.client-ip=209.85.210.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--lucaswei.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="ljd1EdfI" Received: by mail-pf1-f202.google.com with SMTP id d2e1a72fcca58-81f2481ab87so3528292b3a.0 for ; Wed, 14 Jan 2026 06:52:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1768402378; x=1769007178; darn=vger.kernel.org; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=qY8ISVuzSMYysF5FVAjGM0hrJi0sARJDavcxZKDaL/Y=; b=ljd1EdfInOQ6cmyDkbPMVXO7M5zh/5B7c7M1ti12ttZBC8YOmIkJNKTvB/lH9ubxgD 7U6uvIMTLb3LkA/2eh3Ha3/LZelYVmRYbBoiC9eXrsxLPAd/UUX1g17Sgi5rq0Ov+Onm cIjtsaBXh5SqvTz3615sN0PaWeT+FakD/rmJGfZENxOcU9VAzuGJe4ilXylF3P//bOMX P90pc3T//aHjXxklZqXmmNIE7oy4KGvrgjA0FH3vwRN5mSQ2+0x6CW88Z5CLOUoPvVao bpTNyVh7yOOAH2vjEf9Rp6pGGNKMA4RuwyIA8Y/PBalXoh0bGbxxpu8iJeUi8zm5E3w7 iGkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768402378; x=1769007178; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=qY8ISVuzSMYysF5FVAjGM0hrJi0sARJDavcxZKDaL/Y=; b=MJdW0Y8ltnVzBWtQaHYGMUPxMiS8qTb/ADqrsu1i2X9Cg/0IqZC+NjjHz/+EFAybyS 23dGzEeXBCmexQR6ihf8gs7PGJq8A5IUAIGTyWPv3Tc9Fz2TKmkXsIjyaplBbmsG7c42 MNv+yWn9s+ajy9yFP3xKZKjaCddmyRAr5rSE2oLtxbDa9gVHObNDuHTKxmn7J6+KJGpt 6dsDPXcWg+v+S2C6aj9yyWQe1wOK9QoOu7QGeOeHCdsJ9GAwwzNZJVABniSnLxGru8VF PZF7f7TRKnQYFRyELpdX6iGlZLHFjVbhrPfFldkqMLo1Gf/v9WfElhqwQ9SwUwkI1rjv WJ4Q== X-Forwarded-Encrypted: i=1; AJvYcCU5rOlNiKZO7J6b+2jtRI5TzlD2LSm9LFeSFFh8ovnf0MEFrNe/gn9QSXeRg6/Rcqsog5g25fU8euSfHH4=@vger.kernel.org X-Gm-Message-State: AOJu0Yxzj0/xhcqOtoWmRlSXsxdZBUosVVSjxvtQAMoH1ppabTRdDxDH wk7P6Om9cQTXfahTXeiCMSG41uRvhimvTheQsi/aN/ngoZF1eEIcMjUnutuhttip2R7qO9xEivP TDWGcXD2Gdn12XQ== X-Received: from pfgs36.prod.google.com ([2002:a05:6a00:17a4:b0:7e8:a188:d95e]) (user=lucaswei job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a21:998a:b0:33f:4e3d:afff with SMTP id adf61e73a8af0-38bed0b4ad5mr2928565637.14.1768402378210; Wed, 14 Jan 2026 06:52:58 -0800 (PST) Date: Wed, 14 Jan 2026 14:52:41 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.52.0.457.g6b5491de43-goog Message-ID: <20260114145243.3458315-1-lucaswei@google.com> Subject: [PATCH v3] arm64: errata: Workaround for SI L1 downstream coherency issue From: Lucas Wei To: Catalin Marinas , Will Deacon , Jonathan Corbet Cc: sjadavani@google.com, Lucas Wei , stable@vger.kernel.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When software issues a Cache Maintenance Operation (CMO) targeting a dirty cache line, the CPU and DSU cluster may optimize the operation by combining the CopyBack Write and CMO into a single combined CopyBack Write plus CMO transaction presented to the interconnect (MCN). For these combined transactions, the MCN splits the operation into two separate transactions, one Write and one CMO, and then propagates the write and optionally the CMO to the downstream memory system or external Point of Serialization (PoS). However, the MCN may return an early CompCMO response to the DSU cluster before the corresponding Write and CMO transactions have completed at the external PoS or downstream memory. As a result, stale data may be observed by external observers that are directly connected to the external PoS or downstream memory. This erratum affects any system topology in which the following conditions apply: - The Point of Serialization (PoS) is located downstream of the interconnect. - A downstream observer accesses memory directly, bypassing the interconnect. Conditions: This erratum occurs only when all of the following conditions are met: 1. Software executes a data cache maintenance operation, specifically, a clean or clean&invalidate by virtual address (DC CVAC or DC CIVAC), that hits on unique dirty data in the CPU or DSU cache. This results in a combined CopyBack and CMO being issued to the interconnect. 2. The interconnect splits the combined transaction into separate Write and CMO transactions and returns an early completion response to the CPU or DSU before the write has completed at the downstream memory or PoS. 3. A downstream observer accesses the affected memory address after the early completion response is issued but before the actual memory write has completed. This allows the observer to read stale data that has not yet been updated at the PoS or downstream memory. The implementation of workaround put a second loop of CMOs at the same virtual address whose operation meet erratum conditions to wait until cache data be cleaned to PoC. This way of implementation mitigates performance penalty compared to purely duplicate original CMO. Cc: stable@vger.kernel.org # 6.12.x Signed-off-by: Lucas Wei --- Changes in v3: 1. Fix typos 2. Remove 'lkp@intel.com' from commit message 3. Keep ARM within a single section 4. Remove workaround of #4311569 from `cache_inval_poc()` Changes in v2: 1. Fixed warning from kernel test robot by changing arm_si_l1_workaround_4311569 to static [Reported-by: kernel test robot ] --- Documentation/arch/arm64/silicon-errata.rst | 1 + arch/arm64/Kconfig | 19 +++++++++++++ arch/arm64/include/asm/assembler.h | 10 +++++++ arch/arm64/kernel/cpu_errata.c | 31 +++++++++++++++++++++ arch/arm64/tools/cpucaps | 1 + 5 files changed, 62 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index a7ec57060f64..4c300caad901 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -212,6 +212,7 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | GIC-700 | #2941627 | ARM64_ERRATUM_29416= 27 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | SI L1 | #4311569 | ARM64_ERRATUM_43115= 69 | +----------------+-----------------+-----------------+--------------------= ---------+ | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_84571= 9 | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 93173f0a09c7..89326bb26f48 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1155,6 +1155,25 @@ config ARM64_ERRATUM_3194386 =20 If unsure, say Y. =20 +config ARM64_ERRATUM_4311569 + bool "SI L1: 4311569: workaround for premature CMO completion erratum" + default y + help + This option adds the workaround for ARM SI L1 erratum 4311569. + + The erratum of SI L1 can cause an early response to a combined write + and cache maintenance operation (WR+CMO) before the operation is fully + completed to the Point of Serialization (POS). + This can result in a non-I/O coherent agent observing stale data, + potentially leading to system instability or incorrect behavior. + + Enabling this option implements a software workaround by inserting a + second loop of Cache Maintenance Operation (CMO) immediately following = the + end of function to do CMOs. This ensures that the data is correctly ser= ialized + before the buffer is handed off to a non-coherent agent. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index f0ca7196f6fa..d3d46e5f7188 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -381,6 +381,9 @@ alternative_endif .macro dcache_by_myline_op op, domain, start, end, linesz, tmp, fixup sub \tmp, \linesz, #1 bic \start, \start, \tmp +alternative_if ARM64_WORKAROUND_4311569 + mov \tmp, \start +alternative_else_nop_endif .Ldcache_op\@: .ifc \op, cvau __dcache_op_workaround_clean_cache \op, \start @@ -402,6 +405,13 @@ alternative_endif add \start, \start, \linesz cmp \start, \end b.lo .Ldcache_op\@ +alternative_if ARM64_WORKAROUND_4311569 + .ifnc \op, cvau + mov \start, \tmp + mov \tmp, xzr + cbnz \start, .Ldcache_op\@ + .endif +alternative_else_nop_endif dsb \domain =20 _cond_uaccess_extable .Ldcache_op\@, \fixup diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 8cb3b575a031..5c0ab6bfd44a 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -141,6 +141,30 @@ has_mismatched_cache_type(const struct arm64_cpu_capab= ilities *entry, return (ctr_real !=3D sys) && (ctr_raw !=3D sys); } =20 +#ifdef CONFIG_ARM64_ERRATUM_4311569 +static DEFINE_STATIC_KEY_FALSE(arm_si_l1_workaround_4311569); +static int __init early_arm_si_l1_workaround_4311569_cfg(char *arg) +{ + static_branch_enable(&arm_si_l1_workaround_4311569); + pr_info("Enabling cache maintenance workaround for ARM SI-L1 erratum 4311= 569\n"); + + return 0; +} +early_param("arm_si_l1_workaround_4311569", early_arm_si_l1_workaround_431= 1569_cfg); + +/* + * We have some earlier use cases to call cache maintenance operation func= tions, for example, + * dcache_inval_poc() and dcache_clean_poc() in head.S, before making deci= sion to turn on this + * workaround. Since the scope of this workaround is limited to non-cohere= nt DMA agents, its + * safe to have the workaround off by default. + */ +static bool +need_arm_si_l1_workaround_4311569(const struct arm64_cpu_capabilities *ent= ry, int scope) +{ + return static_branch_unlikely(&arm_si_l1_workaround_4311569); +} +#endif + static void cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) { @@ -870,6 +894,13 @@ const struct arm64_cpu_capabilities arm64_errata[] =3D= { ERRATA_MIDR_RANGE_LIST(erratum_spec_ssbs_list), }, #endif +#ifdef CONFIG_ARM64_ERRATUM_4311569 + { + .capability =3D ARM64_WORKAROUND_4311569, + .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, + .matches =3D need_arm_si_l1_workaround_4311569, + }, +#endif #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD { .desc =3D "ARM errata 2966298, 3117295", diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 0fac75f01534..856b6cf6e71e 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -103,6 +103,7 @@ WORKAROUND_2077057 WORKAROUND_2457168 WORKAROUND_2645198 WORKAROUND_2658417 +WORKAROUND_4311569 WORKAROUND_AMPERE_AC03_CPU_38 WORKAROUND_AMPERE_AC04_CPU_23 WORKAROUND_TRBE_OVERWRITE_FILL_MODE base-commit: 0f61b1860cc3f52aef9036d7235ed1f017632193 --=20 2.52.0.457.g6b5491de43-goog