From nobody Sat Feb 7 08:02:35 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 394A4288C26; Wed, 14 Jan 2026 01:22:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768353729; cv=none; b=Zdpe44RmvvJtYmaHU0J7xJShBF8XW0UmIWz41ELyVFwoRJZ9AxjyYAOK6UuOfcP697TgxybOiWYCel8magMk3TnATmy1bwNCxSUeCkgX/c/S7KytslOER9Ph4bo0m8yyviVMgplhwHLTkuzu4rgvhDd8TBTMAESjjpXRt7nX1uY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768353729; c=relaxed/simple; bh=D8xTGkk/V0sD6orEygOPXkhz2ryiacgml5nzER2bOi8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Qzo1T1Y5Vy8YL1KbvAraadu3c5F194EqZW9hKKuDThqy2Mo7TQXqMCkz/RxaoNLXADAh10iMfI1AdViZiJov7NXFhLSWE9QV91ddM6twR6pCOTk+6p6ltNAuqBSng3RIeqvqd4af/DPxgvyyWSagtVsnhOzszGcv+lyF2D1XYP8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JV/fetab; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JV/fetab" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768353728; x=1799889728; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D8xTGkk/V0sD6orEygOPXkhz2ryiacgml5nzER2bOi8=; b=JV/fetablCCPnMCkmfH0h98Ags9ATCfFDSxurPdAtFWXKL9Zou6crsay DXIZsmr2p9wTg6MHkJakis0WlwKaWTSxNxhVcPSNDf3G+MKQMETa8V7pB 1Y/5pZOPkRaErnVy3yFU+zfh8KEhJLF/qlgLal7cXNNj7jCH6+6+Dh1NH YBLFoRPX9NUG5ayForjjGg22nIZj5n3CSgAOSG0lwYchtEM1Km7V6c2eD +GtHJFn2qxNu9APhwRaSQYkSHWYVwcOuINbPz4sT/HSp08fzsWKQlyoGv ZAm7A2fyEo/OxUAcB1+GZ3U3cG8a4iEZXLjBrfWIh9KPzty0+p6z1Ee5z w==; X-CSE-ConnectionGUID: BUm1ld9KSsylKzl7loy+HA== X-CSE-MsgGUID: NiT8d6HXR+SWd225b/o9PQ== X-IronPort-AV: E=McAfee;i="6800,10657,11670"; a="87231488" X-IronPort-AV: E=Sophos;i="6.21,224,1763452800"; d="scan'208";a="87231488" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jan 2026 17:22:08 -0800 X-CSE-ConnectionGUID: j1vXCdWlSY6/toMMYdqCpA== X-CSE-MsgGUID: xrm5cz0rSxeF2Q4iuTYS0Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,224,1763452800"; d="scan'208";a="204561191" Received: from spr.sh.intel.com ([10.112.230.239]) by orviesa007.jf.intel.com with ESMTP; 13 Jan 2026 17:22:04 -0800 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [Patch v3 1/7] perf/x86/intel: Support the 4 new OMR MSRs introduced in DMR and NVL Date: Wed, 14 Jan 2026 09:17:44 +0800 Message-Id: <20260114011750.350569-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260114011750.350569-1-dapeng1.mi@linux.intel.com> References: <20260114011750.350569-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Diamond Rapids (DMR) and Nova Lake (NVL) introduce an enhanced Off-Module Response (OMR) facility, replacing the Off-Core Response (OCR) Performance Monitoring of previous processors. Legacy microarchitectures used the OCR facility to evaluate off-core and multi-core off-module transactions. The newly named OMR facility improves OCR capabilities for scalable coverage of new memory systems in multi-core module systems. Similar to OCR, 4 additional off-module configuration MSRs (OFFMODULE_RSP_0 to OFFMODULE_RSP_3) are introduced to specify attributes of off-module transactions. When multiple identical OMR events are created, they need to occupy the same OFFMODULE_RSP_x MSR. To ensure these multiple identical OMR events can work simultaneously, the intel_alt_er() and intel_fixup_er() helpers are enhanced to rotate these OMR events across different OFFMODULE_RSP_* MSRs, similar to previous OCR events. For more details about OMR, please refer to section 16.1 "OFF-MODULE RESPONSE (OMR) FACILITY" in ISE documentation. Signed-off-by: Dapeng Mi --- v3: Enhance intel_alt_er() to align with intel_fixup_er() on code style. v2: Optimize intel_fixup_er(). arch/x86/events/intel/core.c | 59 +++++++++++++++++++++++--------- arch/x86/events/perf_event.h | 5 +++ arch/x86/include/asm/msr-index.h | 5 +++ 3 files changed, 52 insertions(+), 17 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 1840ca1918d1..3578c660a904 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3532,17 +3532,32 @@ static int intel_alt_er(struct cpu_hw_events *cpuc, struct extra_reg *extra_regs =3D hybrid(cpuc->pmu, extra_regs); int alt_idx =3D idx; =20 - if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) - return idx; - - if (idx =3D=3D EXTRA_REG_RSP_0) - alt_idx =3D EXTRA_REG_RSP_1; + switch (idx) { + case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1: + if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) + return idx; + if (++alt_idx > EXTRA_REG_RSP_1) + alt_idx =3D EXTRA_REG_RSP_0; + if (config & ~extra_regs[alt_idx].valid_mask) + return idx; + break; =20 - if (idx =3D=3D EXTRA_REG_RSP_1) - alt_idx =3D EXTRA_REG_RSP_0; + case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3: + if (!(x86_pmu.flags & PMU_FL_HAS_OMR)) + return idx; + if (++alt_idx > EXTRA_REG_OMR_3) + alt_idx =3D EXTRA_REG_OMR_0; + /* + * Subtracting EXTRA_REG_OMR_0 ensures to get correct + * OMR extra_reg entries which start from 0. + */ + if (config & ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask) + return idx; + break; =20 - if (config & ~extra_regs[alt_idx].valid_mask) - return idx; + default: + break; + } =20 return alt_idx; } @@ -3550,16 +3565,26 @@ static int intel_alt_er(struct cpu_hw_events *cpuc, static void intel_fixup_er(struct perf_event *event, int idx) { struct extra_reg *extra_regs =3D hybrid(event->pmu, extra_regs); - event->hw.extra_reg.idx =3D idx; + int er_idx; =20 - if (idx =3D=3D EXTRA_REG_RSP_0) { - event->hw.config &=3D ~INTEL_ARCH_EVENT_MASK; - event->hw.config |=3D extra_regs[EXTRA_REG_RSP_0].event; - event->hw.extra_reg.reg =3D MSR_OFFCORE_RSP_0; - } else if (idx =3D=3D EXTRA_REG_RSP_1) { + event->hw.extra_reg.idx =3D idx; + switch (idx) { + case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1: + er_idx =3D idx - EXTRA_REG_RSP_0; event->hw.config &=3D ~INTEL_ARCH_EVENT_MASK; - event->hw.config |=3D extra_regs[EXTRA_REG_RSP_1].event; - event->hw.extra_reg.reg =3D MSR_OFFCORE_RSP_1; + event->hw.config |=3D extra_regs[er_idx].event; + event->hw.extra_reg.reg =3D MSR_OFFCORE_RSP_0 + er_idx; + break; + + case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3: + er_idx =3D idx - EXTRA_REG_OMR_0; + event->hw.config &=3D ~ARCH_PERFMON_EVENTSEL_UMASK; + event->hw.config |=3D 1ULL << (8 + er_idx); + event->hw.extra_reg.reg =3D MSR_OMR_0 + er_idx; + break; + + default: + pr_warn("The extra reg idx %d is not supported.\n", idx); } } =20 diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 3161ec0a3416..586e3fdfe6d8 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -45,6 +45,10 @@ enum extra_reg_type { EXTRA_REG_FE =3D 4, /* fe_* */ EXTRA_REG_SNOOP_0 =3D 5, /* snoop response 0 */ EXTRA_REG_SNOOP_1 =3D 6, /* snoop response 1 */ + EXTRA_REG_OMR_0 =3D 7, /* OMR 0 */ + EXTRA_REG_OMR_1 =3D 8, /* OMR 1 */ + EXTRA_REG_OMR_2 =3D 9, /* OMR 2 */ + EXTRA_REG_OMR_3 =3D 10, /* OMR 3 */ =20 EXTRA_REG_MAX /* number of entries needed */ }; @@ -1099,6 +1103,7 @@ do { \ #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ #define PMU_FL_BR_CNTR 0x400 /* Support branch counter logging */ #define PMU_FL_DYN_CONSTRAINT 0x800 /* Needs dynamic constraint */ +#define PMU_FL_HAS_OMR 0x1000 /* has 4 equivalent OMR regs */ =20 #define EVENT_VAR(_id) event_attr_##_id #define EVENT_PTR(_id) &event_attr_##_id.attr.attr diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3d0a0950d20a..6d1b69ea01c2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -263,6 +263,11 @@ #define MSR_SNOOP_RSP_0 0x00001328 #define MSR_SNOOP_RSP_1 0x00001329 =20 +#define MSR_OMR_0 0x000003e0 +#define MSR_OMR_1 0x000003e1 +#define MSR_OMR_2 0x000003e2 +#define MSR_OMR_3 0x000003e3 + #define MSR_LBR_SELECT 0x000001c8 #define MSR_LBR_TOS 0x000001c9 =20 --=20 2.34.1