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Wed, 14 Jan 2026 07:57:52 -0800 (PST) From: James Clark Date: Wed, 14 Jan 2026 15:57:24 +0000 Subject: [PATCH v5 12/14] perf cs-etm: Don't use hard coded config bits when setting up TRCCONFIGR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-james-perf-config-bits-v5-12-0ef97aaf1ac0@linaro.org> References: <20260114-james-perf-config-bits-v5-0-0ef97aaf1ac0@linaro.org> In-Reply-To: <20260114-james-perf-config-bits-v5-0-0ef97aaf1ac0@linaro.org> To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Leo Yan Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, Leo Yan , James Clark X-Mailer: b4 0.14.0 Perf only looks at attr.config when determining what was programmed into TRCCONFIGR. These bits could theoretically be in any of the config fields. Use the evsel__get_config_val() helper so it's agnostic to which config field they are in. The kernel will also stop publishing the TRCCONFIGR register bits in a header [1] so preempt that by defining them here. [1]: https://lore.kernel.org/linux-arm-kernel/20251128-james-cs-syncfreq-v8= -10-4d319764cc58@linaro.org/ Reviewed-by: Leo Yan Reviewed-by: Ian Rogers Signed-off-by: James Clark --- tools/perf/arch/arm/util/cs-etm.c | 79 +++++++++++++++++------------------= ---- 1 file changed, 34 insertions(+), 45 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/c= s-etm.c index f535027ce862..12b28562c2f3 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -68,6 +68,14 @@ static const char * const metadata_ete_ro[] =3D { =20 enum cs_etm_version { CS_NOT_PRESENT, CS_ETMV3, CS_ETMV4, CS_ETE }; =20 +/* ETMv4 CONFIGR register bits */ +#define TRCCONFIGR_BB BIT(3) +#define TRCCONFIGR_CCI BIT(4) +#define TRCCONFIGR_CID BIT(6) +#define TRCCONFIGR_VMID BIT(7) +#define TRCCONFIGR_TS BIT(11) +#define TRCCONFIGR_RS BIT(12) +#define TRCCONFIGR_VMIDOPT BIT(15) =20 /* ETMv3 ETMCR register bits */ #define ETMCR_CYC_ACC BIT(12) @@ -517,56 +525,37 @@ static u64 cs_etm_synth_etmcr(struct auxtrace_record = *itr) return etmcr; } =20 -static u64 cs_etm_get_config(struct auxtrace_record *itr) +static u64 cs_etmv4_synth_trcconfigr(struct auxtrace_record *itr) { + u64 trcconfigr =3D 0; struct cs_etm_recording *ptr =3D - container_of(itr, struct cs_etm_recording, itr); + container_of(itr, struct cs_etm_recording, itr); struct perf_pmu *cs_etm_pmu =3D ptr->cs_etm_pmu; - struct evlist *evlist =3D ptr->evlist; - struct evsel *evsel =3D cs_etm_get_evsel(evlist, cs_etm_pmu); - - /* - * Variable perf_event_attr::config is assigned to - * ETMv3/PTM. The bit fields have been made to match - * the ETMv3.5 ETRMCR register specification. See the - * PMU_FORMAT_ATTR() declarations in - * drivers/hwtracing/coresight/coresight-perf.c for - * details. - */ - return evsel ? evsel->core.attr.config : 0; -} - -#ifndef BIT -#define BIT(N) (1UL << (N)) -#endif + struct evsel *evsel =3D cs_etm_get_evsel(ptr->evlist, cs_etm_pmu); + u64 val; =20 -static u64 cs_etmv4_get_config(struct auxtrace_record *itr) -{ - u64 config =3D 0; - u64 config_opts =3D 0; + if (!evsel) + return 0; =20 /* - * The perf event variable config bits represent both - * the command line options and register programming - * bits in ETMv3/PTM. For ETMv4 we must remap options - * to real bits + * Synthesize what the kernel programmed into TRCCONFIGR based on + * what options the event was opened with. This doesn't have to be + * complete or 100% accurate, not all bits used by OpenCSD anyway. */ - config_opts =3D cs_etm_get_config(itr); - if (config_opts & BIT(ETM_OPT_CYCACC)) - config |=3D BIT(ETM4_CFG_BIT_CYCACC); - if (config_opts & BIT(ETM_OPT_CTXTID)) - config |=3D BIT(ETM4_CFG_BIT_CTXTID); - if (config_opts & BIT(ETM_OPT_TS)) - config |=3D BIT(ETM4_CFG_BIT_TS); - if (config_opts & BIT(ETM_OPT_RETSTK)) - config |=3D BIT(ETM4_CFG_BIT_RETSTK); - if (config_opts & BIT(ETM_OPT_CTXTID2)) - config |=3D BIT(ETM4_CFG_BIT_VMID) | - BIT(ETM4_CFG_BIT_VMID_OPT); - if (config_opts & BIT(ETM_OPT_BRANCH_BROADCAST)) - config |=3D BIT(ETM4_CFG_BIT_BB); - - return config; + if (!evsel__get_config_val(evsel, "cycacc", &val) && val) + trcconfigr |=3D TRCCONFIGR_CCI; + if (!evsel__get_config_val(evsel, "contextid1", &val) && val) + trcconfigr |=3D TRCCONFIGR_CID; + if (!evsel__get_config_val(evsel, "timestamp", &val) && val) + trcconfigr |=3D TRCCONFIGR_TS; + if (!evsel__get_config_val(evsel, "retstack", &val) && val) + trcconfigr |=3D TRCCONFIGR_RS; + if (!evsel__get_config_val(evsel, "contextid2", &val) && val) + trcconfigr |=3D TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT; + if (!evsel__get_config_val(evsel, "branch_broadcast", &val) && val) + trcconfigr |=3D TRCCONFIGR_BB; + + return trcconfigr; } =20 static size_t @@ -688,7 +677,7 @@ static void cs_etm_save_etmv4_header(__u64 data[], stru= ct auxtrace_record *itr, struct perf_pmu *cs_etm_pmu =3D ptr->cs_etm_pmu; =20 /* Get trace configuration register */ - data[CS_ETMV4_TRCCONFIGR] =3D cs_etmv4_get_config(itr); + data[CS_ETMV4_TRCCONFIGR] =3D cs_etmv4_synth_trcconfigr(itr); /* traceID set to legacy version, in case new perf running on older syste= m */ data[CS_ETMV4_TRCTRACEIDR] =3D cs_etm_get_legacy_trace_id(cpu); =20 @@ -720,7 +709,7 @@ static void cs_etm_save_ete_header(__u64 data[], struct= auxtrace_record *itr, st struct perf_pmu *cs_etm_pmu =3D ptr->cs_etm_pmu; =20 /* Get trace configuration register */ - data[CS_ETE_TRCCONFIGR] =3D cs_etmv4_get_config(itr); + data[CS_ETE_TRCCONFIGR] =3D cs_etmv4_synth_trcconfigr(itr); /* traceID set to legacy version, in case new perf running on older syste= m */ data[CS_ETE_TRCTRACEIDR] =3D cs_etm_get_legacy_trace_id(cpu); =20 --=20 2.34.1