From nobody Tue Feb 10 09:24:38 2026 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE74237F8AF for ; Wed, 14 Jan 2026 14:17:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.67 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400245; cv=none; b=QVzp9/2BLicHu8oMBvxXYB6tBlkNpqMa2g9dSFfdEQBIx2sQELCDiGbCv14lYupyjuA1BYF4lZNPZ0v6IZ+WMXhl+FnFoupja08XWYEsD6N8dBUMPwY24jhVwca7okgXKUdLbgFfv6yJsmgJ3LoizxCmhb9Sy7QaYZmm4OrCzp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400245; c=relaxed/simple; bh=5H0lgDSUScoa7O0SKdxLcVIZHcB9BT1ur3Jx/KZwF8M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ERisOCByAQ6TO7YQN48VrTYjEy4k/7Ekxm2OtnZ271v6cobjIKZ2ZGIHIHWq4uM5s3Cfhrxu+5BBOpubPcukSMtprlb+VOyIR6BZlV8Hw5RBZ94qJd+So9diAmX+dLXxXaBMQmrhakXQWW0PjCKt3c+WHeNaHIhiKvUZMQpwPxM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=hj5jePee; arc=none smtp.client-ip=209.85.128.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="hj5jePee" Received: by mail-wm1-f67.google.com with SMTP id 5b1f17b1804b1-47d493a9b96so50291075e9.1 for ; Wed, 14 Jan 2026 06:17:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768400238; x=1769005038; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=v0+/JV08+r5HaiYcZ+Llw+TpfRxTE/NUdH0Ba5F1Ndg=; b=hj5jePeemiULmluJjNB+Ul6OncGKaSlXLPwMX7K/cILlYGNRpEaXjZ4ANDi2Vd99Fu XOxUAH0AV8BGww98b7Kk7kPukaznZHnqulIxphKRB5TpF0ROv3+KR0V/NUbFeo29CByh co8xZSioa4sZgu0XeblM7ZQZKTF+EbpD3orUTS4PzXeVU1n8PLlYYHeyy++mqvgLEUBa JHDQQ6KXJkW14my9GvgomG3HH2GcY9b/6y9GXv1uUsBn4AkLbmmPjxYGrHMZ+PmVoWH5 eQ7QhzzE10vAMyNNyLwMGSPvCFI9/4SCD1X9MlepUaEGLTiEp+T9vk6HGq918uZpWy8P GH6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768400238; x=1769005038; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=v0+/JV08+r5HaiYcZ+Llw+TpfRxTE/NUdH0Ba5F1Ndg=; b=e0C7u5ySt88wfWBwwx+547qQKQhAmu288JVrSvvyDzaHqP0HtDESvmU47bf9lSLHCT +M6JBGQSbu+0FrcpwTkYZkr/oqAMDCFG0ebYpLHugNVm9J6xNjf6nInv9cTTC/dQV8VR /Kc8UdStQim6bYZWuIR6G5qjRQTS5wWwQS7y2DW+u6XwDSxeFIGG9NAGG8woQR1eJU9x YVoHRqP0vPgLuQgz2cqQ3eoDE2OF+k2YqzKrvrVV4xuVyE/8SetvfQggCBKAuLo2Fwrh SobjUJw45ZEFQDAI6iNtrbepN5fPuTrXlrO+x7CBhds7g+faxOMvdXVZL62iGRQOd5Sl v0SA== X-Forwarded-Encrypted: i=1; AJvYcCWEbw2qD+hFTwKuliGOQvvI3Z4AsbrL+6H1MFH7j0SLMihxRwbpN7fLJz5wnoHVb6WGBFztb4KKs8PIS2k=@vger.kernel.org X-Gm-Message-State: AOJu0Yza1Tw53oQIl/qTtdU3I5J8GTZHFUvEd1nw/uY7F9M5azqt5ID2 w4r+jKiQz3qLsPH5BBHykeyjllnT9tKZxQs7SkijJmVMyNrjwnrM4e6XIO/tSLpRNpg= X-Gm-Gg: AY/fxX6JkjEwLPVzMpSNVkFhk9cqxRZh2C/pRg4pdWjSYlkSsCJhS1/4/Fsy+e5AqC8 bI9CRcIRypktoJqZtbAmATiqG20j+vmh1DlbkkfXKVk1mFMocYvp+d/plMSqxgW14ZIAtym95HI /LeGRgAdeUjLRwM4B9bgCEELecQHivjwzLkPjjFl2xcqZR0cxv4G04FROnV/XADhJakncJMLK0c bfqryyl1dZz5XMZBRH1GDN5D85Guz6XCeI/4t0rsRUwWIFhYBsmSSFf3AOVWGKxkteVCaCdzJQ3 9AE/EkAVV3giSxR37J6tsJv+HAsRurstHW+YRLRAq20k3Ds60Mcqz6jNFCfVomeTY2DxZPsICkz hoTjt76U0OVem1nWHb/YBV2CD/J1ISAZsgPquJkTB35wt3dSv+lnZHvaN4xow6bN3BKdgi8VDiS RYOrhoIjpF+Tzt4vnWLMw0rHBOSUMWItNLYgQeUlpcyB+In9gyyRBwmyvmIrvTEmoQ+gwqXQ== X-Received: by 2002:a05:600c:870b:b0:471:9da:5232 with SMTP id 5b1f17b1804b1-47ee3349d27mr34823075e9.15.1768400238402; Wed, 14 Jan 2026 06:17:18 -0800 (PST) Received: from ta2.c.googlers.com (164.102.240.35.bc.googleusercontent.com. [35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:17 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:35 +0000 Subject: [PATCH 7/8] arm64: dts: exynos: gs101: Add thermal management unit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-7-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=9008; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=5H0lgDSUScoa7O0SKdxLcVIZHcB9BT1ur3Jx/KZwF8M=; b=HXnagG3gv/1lLforBYx+5nePgwHPOp9Z1Gwl0BqqQvYoXOb/bhmpCS7TdePLVZg19tC4RNUjf WV7Y7zCenC7CfdPS4WtdHlZAotXST1JrJmm7B/XOVq99Prf7aEloUTU X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Thermal Management Unit (TMU) nodes for the Google GS101 SoC. This includes: - The top-level TMU sensor node linked to the ACPM block. - The TMU syscon node for direct interrupt register access. - Thermal zones for the CPU clusters (little, mid, big) with associated trip points and cooling maps. This enables thermal monitoring and mitigation on GS101 based devices. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 209 +++++++++++++++++++= ++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 22 +++ 2 files changed, 231 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/= boot/dts/exynos/google/gs101-tmu.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6262c3b890aa2f7ad572c32b30b= f926df804ec1e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 TMU configurations device tree source + * + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include + +/ { + thermal-zones { + cpucl2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 0>; + + trips { + big_cold: big-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_switch_on: big-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_control_temp: big-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + big_pre_switch_on: big-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_alert2: big-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hw_throttling: big-hw-throttling { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_pause: big-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hot: big-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&big_control_temp>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + mid_cold: mid-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_switch_on: mid-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_control_temp: mid-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + mid_pre_switch_on: mid-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_alert2: mid-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hw_throttling: mid-hw-throttling { + temperature =3D <98000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_pause: mid-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hot: mid-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&mid_control_temp>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 2>; + + trips { + little_cold: little-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_switch_on: little-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_control_temp: little-control-temp { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + little_pre_switch_on: little-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_alert2: little-alert2 { + temperature =3D <100000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert5: little-alert5 { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert6: little-alert6 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_hot: little-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&little_control_temp>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 48f3819590cf8c05d6bd7241cfed8720149c7db4..a2d5ed832588b83ec47e8c68330= 73c9ec95f2517 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -74,6 +74,7 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -86,6 +87,7 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -98,6 +100,7 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -110,6 +113,7 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -122,6 +126,7 @@ cpu4: cpu@400 { compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -134,6 +139,7 @@ cpu5: cpu@500 { compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -146,6 +152,7 @@ cpu6: cpu@600 { compatible =3D "arm,cortex-x1"; reg =3D <0x0600>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -158,6 +165,7 @@ cpu7: cpu@700 { compatible =3D "arm,cortex-x1"; reg =3D <0x0700>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -489,6 +497,14 @@ acpm_ipc: power-management { #clock-cells =3D <1>; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; + + tmu_top: thermal-sensor { + compatible =3D "google,gs101-tmu-top"; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + syscon =3D <&tmu_top_syscon>; + #thermal-sensor-cells =3D <1>; + }; }; }; =20 @@ -639,6 +655,11 @@ watchdog_cl1: watchdog@10070000 { status =3D "disabled"; }; =20 + tmu_top_syscon: syscon@100a0000 { + compatible =3D "google,gs101-tmu-syscon", "syscon"; + reg =3D <0x100a0000 0x800>; + }; + trng: rng@10141400 { compatible =3D "google,gs101-trng", "samsung,exynos850-trng"; @@ -1844,3 +1865,4 @@ timer { }; =20 #include "gs101-pinctrl.dtsi" +#include "gs101-tmu.dtsi" --=20 2.52.0.457.g6b5491de43-goog