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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:08 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:31 +0000 Subject: [PATCH 3/8] dt-bindings: mfd: Add Google GS101 TMU Syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-3-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=1858; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=8UojV7uTS3mheivu+7sw0eF9oi43bOc4wBfGZPuFRE4=; b=L7ka53Pavk7o7iv9buy1Uk9Hui9JJggaZxvrQ3ziB2ZiI1QLIDOWA/yKh7O8c0KHhKHL9SBVE ZcmvuXqrAbVA3WmMGUQlhnK9rs6sZ/WjzLR5VHO/HfFM7tqZ8VIaPf2 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Document the bindings for the Thermal Management Unit (TMU) System Controller found on Google GS101 SoCs. This memory-mapped block exposes the registers required for reading thermal interrupt status bits. It functions as a syscon provider, allowing the main thermal driver to access these registers while the firmware manages the core thermal logic. Signed-off-by: Tudor Ambarus --- .../bindings/mfd/google,gs101-tmu-syscon.yaml | 37 ++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.= yaml b/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6a11e43abeaa23ee473be215347= 8436856277714 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/google,gs101-tmu-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 TMU System Controller + +maintainers: + - Tudor Ambarus + +description: | + The TMU System Controller provides a memory-mapped interface for + accessing the interrupt status registers of the Thermal Management + Unit. It is used as a syscon provider for the main TMU driver. + +properties: + compatible: + items: + - const: google,gs101-tmu-syscon + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@100a0000 { + compatible =3D "google,gs101-tmu-syscon", "syscon"; + reg =3D <0x100a0000 0x800>; + }; --=20 2.52.0.457.g6b5491de43-goog