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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:05 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:29 +0000 Subject: [PATCH 1/8] dt-bindings: thermal: Add Google GS101 TMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-1-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=2960; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=WBMqNxSxLS3g+O1kbvkoees1LyjIONc/6PlycT8B4zY=; b=qkqinRurGCRKkQsa99SgSmLgMRLHVY4181hXS5vi68gr9cs3nBlqcOVvGvWCkuaEMoDEcqWQ4 oUyu3DXXIcyDs/tQVSh/3vaUbcXxDGJyaoDJWatqNDcxcQylrw6kBle X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add device tree bindings for the Google GS101 Thermal Management Unit (TMU). The GS101 TMU is a hybrid thermal solution: 1. Configuration (thresholds, hysteresis) is handled via the Alive Clock and Power Manager (ACPM) firmware protocol. 2. Interrupt handling is handled by the kernel via direct register access. This binding documents the required resources, including the APB clock for register access and the phandle to the associated syscon node. Signed-off-by: Tudor Ambarus --- .../bindings/thermal/google,gs101-tmu-top.yaml | 64 ++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top= .yaml b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ecf4a315ecf1ea0649c4e96a207= d531c696282f4 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/google,gs101-tmu-top.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 Thermal Management Unit (TMU) + +maintainers: + - Tudor Ambarus + +description: | + The Google GS101 TMU is a thermal sensor block managed via the ACPM + (Active Core Power Management) firmware. While the firmware handles + the thermal algorithm and thresholds, the kernel requires direct + access to the interrupt pending registers via a syscon interface to + acknowledge and clear thermal interrupts. + +properties: + compatible: + const: google,gs101-tmu-top + + clocks: + maxItems: 1 + description: | + Phandle to the APB peripheral clock (PCLK) required to access + the TMU registers. + + interrupts: + maxItems: 1 + description: | + The combined thermal interrupt signal (Level High). + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the device node representing the TMU System Controller + (compatible with "google,gs101-tmu-syscon"). This node provides the + regmap for INTPEND and INTCLEAR registers. + + "#thermal-sensor-cells": + const: 1 + +required: + - compatible + - clocks + - interrupts + - syscon + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + thermal-sensor { + compatible =3D "google,gs101-tmu-top"; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + syscon =3D <&tmu_top_syscon>; + #thermal-sensor-cells =3D <1>; + }; --=20 2.52.0.457.g6b5491de43-goog