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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:05 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:29 +0000 Subject: [PATCH 1/8] dt-bindings: thermal: Add Google GS101 TMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-1-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=2960; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=WBMqNxSxLS3g+O1kbvkoees1LyjIONc/6PlycT8B4zY=; b=qkqinRurGCRKkQsa99SgSmLgMRLHVY4181hXS5vi68gr9cs3nBlqcOVvGvWCkuaEMoDEcqWQ4 oUyu3DXXIcyDs/tQVSh/3vaUbcXxDGJyaoDJWatqNDcxcQylrw6kBle X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add device tree bindings for the Google GS101 Thermal Management Unit (TMU). The GS101 TMU is a hybrid thermal solution: 1. Configuration (thresholds, hysteresis) is handled via the Alive Clock and Power Manager (ACPM) firmware protocol. 2. Interrupt handling is handled by the kernel via direct register access. This binding documents the required resources, including the APB clock for register access and the phandle to the associated syscon node. Signed-off-by: Tudor Ambarus --- .../bindings/thermal/google,gs101-tmu-top.yaml | 64 ++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top= .yaml b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ecf4a315ecf1ea0649c4e96a207= d531c696282f4 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/google,gs101-tmu-top.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 Thermal Management Unit (TMU) + +maintainers: + - Tudor Ambarus + +description: | + The Google GS101 TMU is a thermal sensor block managed via the ACPM + (Active Core Power Management) firmware. While the firmware handles + the thermal algorithm and thresholds, the kernel requires direct + access to the interrupt pending registers via a syscon interface to + acknowledge and clear thermal interrupts. + +properties: + compatible: + const: google,gs101-tmu-top + + clocks: + maxItems: 1 + description: | + Phandle to the APB peripheral clock (PCLK) required to access + the TMU registers. + + interrupts: + maxItems: 1 + description: | + The combined thermal interrupt signal (Level High). + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the device node representing the TMU System Controller + (compatible with "google,gs101-tmu-syscon"). This node provides the + regmap for INTPEND and INTCLEAR registers. + + "#thermal-sensor-cells": + const: 1 + +required: + - compatible + - clocks + - interrupts + - syscon + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + thermal-sensor { + compatible =3D "google,gs101-tmu-top"; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + syscon =3D <&tmu_top_syscon>; + #thermal-sensor-cells =3D <1>; + }; --=20 2.52.0.457.g6b5491de43-goog From nobody Sun Feb 8 20:59:11 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 517602DE6FF for ; Wed, 14 Jan 2026 14:17:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400232; cv=none; b=esSn3zEg0A4Dm7clFZSwd3Dyb1mIYhkZVJ2AXRj0lUdbTxcyNx2+pZqeFUt/4VdH3tYNG/yAimvfoeK82lIekL1cckHb5FVoFmMwXIiDB9oz8PYJSs8+gUvnitYpMa9EQMfaF4bvHjHFtINNJCwPSAEPV59KKWlm5KOOoiPP3S0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400232; c=relaxed/simple; bh=Y+qelmK4bAlyv/krT1u3T7mbMOZyLus+NJ7siKthjMI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=t75WCuVS2kV4dwYENwT0xecvrOQVTID0mFQaIXAS58rju8CibzZRwxjKHsKJms9C1Q5Iw1I3cpL3j0vSBCBRyyWqr/+V7JZu+AHIt7NL3iTUrGuO7GfVp5XtE5GM8iJcSk0Oe2JtqUA7c7pJnfG2rzNNe4dMrshJZjqR416f3mo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=l6B+ujYV; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="l6B+ujYV" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-47ee974e230so1005275e9.2 for ; Wed, 14 Jan 2026 06:17:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768400229; x=1769005029; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YO5IPtO5cdGkzvneXRvi+dlXdyTwC85OfiFr6xfp5RY=; b=l6B+ujYVKM1sBblbNAMJCTC70KkS2D6EZxpInI8m5TBmcdckqVhkYCM4Vr0rk3EDx6 BsY/9KGnUThwD/foFJER3XuEEexoIDAwHBDsePKSNf0phTuxjnPA4obqoNFSn2yHzsN8 4Uu2hCfrMojRFH4CKOLuQRJxTYRnThz8s0L/fb53Xstj1KP1Wgld44gGJ5yBSQMIG+iv SML4SsOoWTobjtV+cRFy6lZ8NSCFzlDMkFYgINR83W16bcBnFScjnIcux4lKXIpEh8SX TOW9UyvyenBMbzePgouSlZKTFCvdKTo5QKI69rxxwgBG69G0h8/boJSdaE0u6b3KRJug 2OKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768400229; x=1769005029; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=YO5IPtO5cdGkzvneXRvi+dlXdyTwC85OfiFr6xfp5RY=; b=Je/u4RrWjY6fEnCSHW3M/oMd0mvlJZg/t20LYlPaf9PoXtzYJwKLiOcwD0am/AD+b5 XdSFQ6pz2Tc2evULNqb7ArjWukQvUnFzv8UxuBRVeEJWcj5orRwnNdYHg4lrPRUZ/yqN yppgSNd2C4Hgq85tGRFb3Aq8PR1HobKc8Z0J94CS3qceQYFmVXXoDfTL7XIUpH7A1hO6 keyL3POfC+LbF4PoLXliPEV9M/MY3hRHEMxzRyL1Nj02H9vHA8UyD4T9Ta8i5qPjHJQn YFOlMPu26yuRswkCtpHZc+JdIhIM/ktrLUPdzR03JwtA+52k11fCeRxjIHfz61mM7ibC l0jA== X-Forwarded-Encrypted: i=1; AJvYcCWGCIR4pcAALKV00UD00/SrtLRNbmBZRAcUlhlwb0+WQsJokWK2Ibio1rhaL66T8Ilrj46q7Y7/4VgPVDU=@vger.kernel.org X-Gm-Message-State: AOJu0YwBxyZBe3Qg/cv7WHjkUv7UKXcZDZ5NxfO9lyHS27qNmj+/f8U/ 8w5oaJR2Jl81qKt6Qa/wIxM9HpFlLjiW0NzlN6drfR9eGnmZnP4DsHZZ1HO5w4sJix0= X-Gm-Gg: AY/fxX6FsIJqLT7pXkbsFcTXs0Am8eb4VBJgDnnmIw0J7vjhcqSEi98oX+nK81zocUd DKD+YrUM6WnmEZM+JKJ8RASluZcb056k5skU1AcfztIXsSoQV+b2w3mneReYeTz0dus36/T0UEH PDp7g+7/fEvf0BOTPVh/dNBGAXJIsTN3fQCHOBXFEoHBxQfcrWbuR5NuEQ/hn5SQ9tPnanEkzWs vjM0MI+nkYFPUKkfnDGuzWXicTlTAJejanIw/jBKEwxV7P1MRefW1cYZhBqbEoOWUGiB3gH1jlM ImjRF4RLm4r8oJk219RA62agU+UK3YFh0WvznXJx4V9gJF2UvTAXBW5CkwBK1JaazakCPt+3xKy M9juzQeehdFQkjPR8/Q5EuEkMZrhlIcGEdgqN7L/zLF8zaASX85+yGN9v0Z4ypIB4D1eYNG8JIl NwsENvyE/bOAgWNBMt+5ZUx7deCTAZWvxBQ8kbFAgEoqNqEE4kZBfHbBYpc2KUGc/6eYeAoA== X-Received: by 2002:a05:600c:3555:b0:47b:e2a9:2bd7 with SMTP id 5b1f17b1804b1-47ee3363c12mr38044285e9.19.1768400228580; Wed, 14 Jan 2026 06:17:08 -0800 (PST) Received: from ta2.c.googlers.com (164.102.240.35.bc.googleusercontent.com. [35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:07 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:30 +0000 Subject: [PATCH 2/8] dt-bindings: firmware: google,gs101-acpm-ipc: Add TMU child node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-2-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=1633; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=Y+qelmK4bAlyv/krT1u3T7mbMOZyLus+NJ7siKthjMI=; b=C+ZHlnpywyNkQkIYeZeMHaDsZBGpz38Vgp8+GMBcn0/FwlaNnjHtHkxAETXB7iXLe1n+GG1Bf Y6UwZZFTUyAB9FjKozYqzSJoOTCshklD/jjZIt4actl242H/wICUhN9 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The Google GS101 Thermal Management Unit (TMU) is a child device of the ACPM (Alive Clock and Power Manager) block, as it relies on the ACPM protocol for configuration and initialization. Update the ACPM binding to include the thermal-sensor child node. Signed-off-by: Tudor Ambarus --- .../bindings/firmware/google,gs101-acpm-ipc.yaml | 17 +++++++++++++= ++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index d3bca6088d128485618bb2b538ed8596b4ba14f0..4043a6453a9897b9e1d0e618489= f79c19f32f247 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -52,6 +52,15 @@ properties: are used for passing messages to/from the ACPM firmware. maxItems: 1 =20 + thermal-sensor: + description: Child node describing a Thermal Management Unit instance. + type: object + additionalProperties: true + + properties: + compatible: + const: google,gs101-tmu-top + required: - compatible - "#clock-cells" @@ -93,4 +102,12 @@ examples: }; }; }; + + thermal-sensor { + compatible =3D "google,gs101-tmu-top"; + clocks =3D <&cmu_misc 71>; + interrupts =3D <0 769 4 0>; + syscon =3D <&tmu_top_syscon>; + #thermal-sensor-cells =3D <1>; + }; }; --=20 2.52.0.457.g6b5491de43-goog From nobody Sun Feb 8 20:59:11 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88B742DF12E for ; Wed, 14 Jan 2026 14:17:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400240; cv=none; b=A0P8rRNpUUeKs2znVecERd+BP2CQ2/hcnWVSkLQFRUH5nAYO3Bj+LigOSxyJ4JXIMarPoFQRYNMt29xmybd+VMUztlm1pANe29FxPzjnr2Ep8FekGHMUryicB4kt6JfKIVEYsZTSvd74G2l9YELckK3UrZCgpOaX/wGEhk/jB9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400240; c=relaxed/simple; bh=8UojV7uTS3mheivu+7sw0eF9oi43bOc4wBfGZPuFRE4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:08 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:31 +0000 Subject: [PATCH 3/8] dt-bindings: mfd: Add Google GS101 TMU Syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-3-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=1858; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=8UojV7uTS3mheivu+7sw0eF9oi43bOc4wBfGZPuFRE4=; b=L7ka53Pavk7o7iv9buy1Uk9Hui9JJggaZxvrQ3ziB2ZiI1QLIDOWA/yKh7O8c0KHhKHL9SBVE ZcmvuXqrAbVA3WmMGUQlhnK9rs6sZ/WjzLR5VHO/HfFM7tqZ8VIaPf2 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Document the bindings for the Thermal Management Unit (TMU) System Controller found on Google GS101 SoCs. This memory-mapped block exposes the registers required for reading thermal interrupt status bits. It functions as a syscon provider, allowing the main thermal driver to access these registers while the firmware manages the core thermal logic. Signed-off-by: Tudor Ambarus --- .../bindings/mfd/google,gs101-tmu-syscon.yaml | 37 ++++++++++++++++++= ++++ 1 file changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.= yaml b/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6a11e43abeaa23ee473be215347= 8436856277714 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/google,gs101-tmu-syscon.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/google,gs101-tmu-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google GS101 TMU System Controller + +maintainers: + - Tudor Ambarus + +description: | + The TMU System Controller provides a memory-mapped interface for + accessing the interrupt status registers of the Thermal Management + Unit. It is used as a syscon provider for the main TMU driver. + +properties: + compatible: + items: + - const: google,gs101-tmu-syscon + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + syscon@100a0000 { + compatible =3D "google,gs101-tmu-syscon", "syscon"; + reg =3D <0x100a0000 0x800>; + }; --=20 2.52.0.457.g6b5491de43-goog From nobody Sun Feb 8 20:59:11 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 633512DEA68 for ; Wed, 14 Jan 2026 14:17:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400240; cv=none; b=e8QCD1AmT45bTre49xf2jvnDpjN/Ygqm2Fz7ZJfvnLOGxGmkbF2zCRAGg2l8He8CHefks2HTnLRENAvLq/vgvet9CTLuwO/lKSXqCflYK6g+EY6RxulJB7px2oW5lacEWiBgF9LFOLnSRfNifxnrnVsK62EUGpPbSTLky0UxevI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768400240; c=relaxed/simple; bh=scZVLwTECj4CGzumXSOMKU8Ox6ZHln+/s1mUJJlsDnc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VooGIFahJp2GuGsk9IThmAMq/ORKszxTOczwgmIl/TVrsLfPtDiz4rnI3s+YPAupkmwVee8SSinT8EsG3swTfpXBNOf/N42xvmm8V0QN9htr3X7wcEy9FrO+/bVNu03Rdp9oSvmygCy7il1ASa20I1OonAaavEyybJQsaOBE/Ck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=vyXj9OQx; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vyXj9OQx" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-4779a4fc95aso6097805e9.1 for ; Wed, 14 Jan 2026 06:17:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1768400236; x=1769005036; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RUpc7tPcYauEJYqevhj0yziHsT/ZtjU3a5lZkEZyS1w=; b=vyXj9OQxuGNd3gMpdt5ywRHr+7FxdNcTSon0/pXhS6rznhF0WD27kBFhJc6tpExwXv pTZ3wwDSG0nesHCwIyuRPcWcuVL/IJylg+eUwQOghk2qjpMXkWquPqP23anm9L4UHrx9 GXt4W9fZkJ+KW0cHAmOlupXM+0j1gmbHxCBrrfnCGnLs270ot1ryP9SG1J3yXWFCeOig iVFleKwWWdIzc1dBCF/1EsNMrpYELNJcDrEjVBQvhk0kNbCGf3jPNUPx9SM8TilwDKlo HGso+57f+OXA+gxj3TtAaleOpdnECKG6KtfgVi/sLYkGbzJ05A+4DSobCQ7mfgvtCjIr UzaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768400236; x=1769005036; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=RUpc7tPcYauEJYqevhj0yziHsT/ZtjU3a5lZkEZyS1w=; b=mFlHb2aRal1VTZTp6410G4I4OrH52Xq7swcc4Exvuwct4KFN2JMLiT560sjTb8MU1z Zo2k2at1HAoELcAecVolV0TclDzm23mCZJMqLavq9z47tixTdEDPak6ukRhPPwR1RmFl qmb2mLBmKJra0A88sCl/TWpEw95iKGKHTO7od7d9qFRG60OIqYTAtT0X1pOq/OnDYR+0 z+XsEoLf+O6/izCDtS1ajt+swKWM/ijFhwOTYmR4PJveeX1BqGOwMP1kn8osZM0dn/wx ozjFf92boisuPCYvQkY39uSFs95e/nTCsYeF545noqrAa3t9pbEXPifx/lLuzU0fOhx5 M53A== X-Forwarded-Encrypted: i=1; AJvYcCX6eBGWjktu1GsFdoE3DLRosWQbiefj7h27Pe7jnvAmrymP38JuFnvfghYqNa0cH6S7gGLi1Qs5ZJPxuqI=@vger.kernel.org X-Gm-Message-State: AOJu0Yx7Ge/C5RL6uOjZC2/AJnBgA3hb85jyg347bJMXTo8Oi666ykzq ArXNrmywqJeseysnSBcmTBFxh0F8YLeNaVPTu48JBV4Y6B3pg47xEP2mH7/Htdyts9o= X-Gm-Gg: AY/fxX6h8LPHbHyx7bor5uyxq0WzhjYWOKTX0S5+GNPdLkiYjHpSyZfGQv9Zz2HdSTr 3qjgvEuTrp4gH+SVUkY/6tfGAwwdcjcl3a9hQjKigTpKTwtpaFAzwdAs2CkJDNgwblTGzLjCnhU gIJYYyqH26btuvNj7qkDacdy9uU//3XsaC9yBymoWJ8U01QnkZliQOaFq+ZVrXXNoeE+4u4keZh C1Kwz4HK/0cSA1EuMyPyj4wIgFaUJHDEQL4G2NEaFg+w9fyiGEqezHy42GATMCPkcC+7zvRIGzx xwY+e77Xqc5B0sw82GDm7KLpF+3TrN0pqZFZMgIzQGY3ZCYraPrDCxSlyHI9pWpfQ8LNMkpxJdg K9ww1831XMERDXyFYlhwJggmfBNWOfgiQhU00T5+gb3UE6gBTDz1jFEVmuOs876Zb+ibC0nxJ4o sZQwgGkH5mVxFyJYlBwhgknKDGgSwSzZNxnGYO6pHYeL/0Ut9EoIB+dHWGS1wnv/DF2HT3cA== X-Received: by 2002:a05:600c:747:b0:477:9d31:9f76 with SMTP id 5b1f17b1804b1-47ed7c284f3mr55537135e9.12.1768400235738; Wed, 14 Jan 2026 06:17:15 -0800 (PST) Received: from ta2.c.googlers.com (164.102.240.35.bc.googleusercontent.com. [35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:14 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:32 +0000 Subject: [PATCH 4/8] firmware: samsung: acpm: Add TMU protocol support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-4-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=11917; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=scZVLwTECj4CGzumXSOMKU8Ox6ZHln+/s1mUJJlsDnc=; b=5mBrS0mafIwBfkzAx7jh6ZJxc7p3Byf+AqDcw5Ue/nSlE+ZkDs76evSOIhSrOHLU1kRnnU0Oc B2lX0e++yktClE8dn7EwV6KxxKpjWxAEcl8FGBqCsiOlyY9Yx+lm++m X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The Thermal Management Unit (TMU) on Google GS101 SoC is primarily managed by the Alive Clock and Power Manager (ACPM) firmware. Add the protocol helpers required to communicate with the ACPM for thermal operations, including initialization, threshold configuration, temperature reading, and system suspend/resume handshakes. This architecture requires a split responsibility between the kernel and firmware. While the kernel can read the interrupt pending status directly via a syscon interface (for low-latency sensor identification), it shall not write to the status registers directly. Instead, the kernel must issue an ACPM IPC request (`ACPM_TMU_IRQ_CLEAR`) to acknowledge and clear the interrupt, ensuring the firmware's internal state machine remains synchronized. Signed-off-by: Tudor Ambarus --- drivers/firmware/samsung/Makefile | 1 + drivers/firmware/samsung/exynos-acpm-tmu.c | 212 +++++++++++++++++= ++++ drivers/firmware/samsung/exynos-acpm-tmu.h | 33 ++++ drivers/firmware/samsung/exynos-acpm.c | 12 ++ .../linux/firmware/samsung/exynos-acpm-protocol.h | 24 +++ 5 files changed, 282 insertions(+) diff --git a/drivers/firmware/samsung/Makefile b/drivers/firmware/samsung/M= akefile index 80d4f89b33a9558b68c9083da675c70ec3d05f19..5a6f72bececfd98ba5af37d1d65= fed48a3d8f912 100644 --- a/drivers/firmware/samsung/Makefile +++ b/drivers/firmware/samsung/Makefile @@ -3,4 +3,5 @@ acpm-protocol-objs :=3D exynos-acpm.o acpm-protocol-objs +=3D exynos-acpm-pmic.o acpm-protocol-objs +=3D exynos-acpm-dvfs.o +acpm-protocol-objs +=3D exynos-acpm-tmu.o obj-$(CONFIG_EXYNOS_ACPM_PROTOCOL) +=3D acpm-protocol.o diff --git a/drivers/firmware/samsung/exynos-acpm-tmu.c b/drivers/firmware/= samsung/exynos-acpm-tmu.c new file mode 100644 index 0000000000000000000000000000000000000000..7ec4b48074eb8b4e569b39d4bb5= 963d887aa9521 --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-tmu.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#include "exynos-acpm.h" +#include "exynos-acpm-tmu.h" + +/* IPC Request Types */ +#define ACPM_TMU_INIT 0x01 +#define ACPM_TMU_READ_TEMP 0x02 +#define ACPM_TMU_SUSPEND 0x04 +#define ACPM_TMU_RESUME 0x10 +#define ACPM_TMU_THRESHOLD 0x11 +#define ACPM_TMU_INTEN 0x12 +#define ACPM_TMU_CONTROL 0x13 +#define ACPM_TMU_IRQ_CLEAR 0x14 +#define ACPM_TMU_HYSTERESIS 0x16 + +#define ACPM_TMU_TX_DATA_LEN 8 +#define ACPM_TMU_RX_DATA_LEN 7 + +struct acpm_tmu_tx { + u16 ctx; + u16 fw_use; + u8 type; + u8 rsvd0; + u8 tzid; + u8 rsvd1; + u8 data[ACPM_TMU_TX_DATA_LEN]; +} __packed; + +struct acpm_tmu_rx { + u16 ctx; + u16 fw_use; + u8 type; + s8 ret; + u8 tzid; + s8 temp; + u8 rsvd; + u8 data[ACPM_TMU_RX_DATA_LEN]; +} __packed; + +union acpm_tmu_msg { + u32 data[4]; + struct acpm_tmu_tx tx; + struct acpm_tmu_rx rx; +} __packed; + +static void acpm_tmu_set_xfer(struct acpm_xfer *xfer, u32 *cmd, size_t cmd= len, + unsigned int acpm_chan_id) +{ + xfer->acpm_chan_id =3D acpm_chan_id; + xfer->txd =3D cmd; + xfer->txlen =3D cmdlen; + xfer->rxd =3D cmd; + xfer->rxlen =3D cmdlen; +} + +int acpm_tmu_init(const struct acpm_handle *handle, unsigned int acpm_chan= _id) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_INIT; + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_read_temp(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, int *temp) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + int ret; + + msg.tx.type =3D ACPM_TMU_READ_TEMP; + msg.tx.tzid =3D tz; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + ret =3D acpm_do_xfer(handle, &xfer); + if (ret) + return ret; + + *temp =3D msg.rx.temp; + + return 0; +} + +int acpm_tmu_set_threshold(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 temperature[8], size_t tlen) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + int i; + + if (tlen > ACPM_TMU_TX_DATA_LEN) + return -EINVAL; + + msg.tx.type =3D ACPM_TMU_THRESHOLD; + msg.tx.tzid =3D tz; + + for (i =3D 0; i < tlen; i++) + msg.tx.data[i] =3D temperature[i]; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_set_hysteresis(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 hysteresis[8], size_t hlen) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + int i; + + if (hlen > ACPM_TMU_TX_DATA_LEN) + return -EINVAL; + + msg.tx.type =3D ACPM_TMU_HYSTERESIS; + msg.tx.tzid =3D tz; + + for (i =3D 0; i < hlen; i++) + msg.tx.data[i] =3D hysteresis[i]; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_set_interrupt_enable(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, u8 inten) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_INTEN; + msg.tx.tzid =3D tz; + msg.tx.data[0] =3D inten; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_tz_control(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, bool enable) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_CONTROL; + msg.tx.tzid =3D tz; + msg.tx.data[0] =3D enable ? 1 : 0; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_clear_tz_irq(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_IRQ_CLEAR; + msg.tx.tzid =3D tz; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_suspend(const struct acpm_handle *handle, + unsigned int acpm_chan_id) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_SUSPEND; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} + +int acpm_tmu_resume(const struct acpm_handle *handle, unsigned int acpm_ch= an_id) +{ + union acpm_tmu_msg msg =3D {0}; + struct acpm_xfer xfer; + + msg.tx.type =3D ACPM_TMU_RESUME; + + acpm_tmu_set_xfer(&xfer, msg.data, sizeof(msg.data), acpm_chan_id); + + return acpm_do_xfer(handle, &xfer); +} diff --git a/drivers/firmware/samsung/exynos-acpm-tmu.h b/drivers/firmware/= samsung/exynos-acpm-tmu.h new file mode 100644 index 0000000000000000000000000000000000000000..f1a1ac21736d52bea0ad2a7cb3b= 280201fa74ffe --- /dev/null +++ b/drivers/firmware/samsung/exynos-acpm-tmu.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ +#ifndef __EXYNOS_ACPM_TMU_H__ +#define __EXYNOS_ACPM_TMU_H__ + +#include + +struct acpm_handle; + +int acpm_tmu_init(const struct acpm_handle *handle, unsigned int acpm_chan= _id); +int acpm_tmu_read_temp(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, int *temp); +int acpm_tmu_set_threshold(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 temperature[8], size_t tlen); +int acpm_tmu_set_hysteresis(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 hysteresis[8], size_t hlen); +int acpm_tmu_set_interrupt_enable(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, u8 inten); +int acpm_tmu_tz_control(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, bool enable); +int acpm_tmu_clear_tz_irq(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz); +int acpm_tmu_suspend(const struct acpm_handle *handle, + unsigned int acpm_chan_id); +int acpm_tmu_resume(const struct acpm_handle *handle, + unsigned int acpm_chan_id); +#endif /* __EXYNOS_ACPM_TMU_H__ */ diff --git a/drivers/firmware/samsung/exynos-acpm.c b/drivers/firmware/sams= ung/exynos-acpm.c index 0cb269c7046015d4c5fe5731ba0d61d48dcaeee1..cc045370f4b0dc6ccea99e3c2d6= f86a43b2e9671 100644 --- a/drivers/firmware/samsung/exynos-acpm.c +++ b/drivers/firmware/samsung/exynos-acpm.c @@ -31,6 +31,7 @@ #include "exynos-acpm.h" #include "exynos-acpm-dvfs.h" #include "exynos-acpm-pmic.h" +#include "exynos-acpm-tmu.h" =20 #define ACPM_PROTOCOL_SEQNUM GENMASK(21, 16) =20 @@ -595,6 +596,7 @@ static void acpm_setup_ops(struct acpm_info *acpm) { struct acpm_dvfs_ops *dvfs_ops =3D &acpm->handle.ops.dvfs_ops; struct acpm_pmic_ops *pmic_ops =3D &acpm->handle.ops.pmic_ops; + struct acpm_tmu_ops *tmu_ops =3D &acpm->handle.ops.tmu; =20 dvfs_ops->set_rate =3D acpm_dvfs_set_rate; dvfs_ops->get_rate =3D acpm_dvfs_get_rate; @@ -604,6 +606,16 @@ static void acpm_setup_ops(struct acpm_info *acpm) pmic_ops->write_reg =3D acpm_pmic_write_reg; pmic_ops->bulk_write =3D acpm_pmic_bulk_write; pmic_ops->update_reg =3D acpm_pmic_update_reg; + + tmu_ops->init =3D acpm_tmu_init; + tmu_ops->read_temp =3D acpm_tmu_read_temp; + tmu_ops->set_threshold =3D acpm_tmu_set_threshold; + tmu_ops->set_hysteresis =3D acpm_tmu_set_hysteresis; + tmu_ops->set_interrupt_enable =3D acpm_tmu_set_interrupt_enable; + tmu_ops->tz_control =3D acpm_tmu_tz_control; + tmu_ops->clear_tz_irq =3D acpm_tmu_clear_tz_irq; + tmu_ops->suspend =3D acpm_tmu_suspend; + tmu_ops->resume =3D acpm_tmu_resume; } =20 static void acpm_clk_pdev_unregister(void *data) diff --git a/include/linux/firmware/samsung/exynos-acpm-protocol.h b/includ= e/linux/firmware/samsung/exynos-acpm-protocol.h index 2091da965a5ad238b5e16c567a72fe88fafe6095..43d41e11ad2eb985e27a918ce3f= 9e9ac15a194ee 100644 --- a/include/linux/firmware/samsung/exynos-acpm-protocol.h +++ b/include/linux/firmware/samsung/exynos-acpm-protocol.h @@ -40,9 +40,33 @@ struct acpm_pmic_ops { u8 value, u8 mask); }; =20 +struct acpm_tmu_ops { + int (*init)(const struct acpm_handle *handle, + unsigned int acpm_chan_id); + int (*read_temp)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, int *temp); + int (*set_threshold)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 temperature[8], size_t tlen); + int (*set_hysteresis)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, + const u8 hysteresis[8], size_t hlen); + int (*set_interrupt_enable)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, u8 inten); + int (*tz_control)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz, bool enable); + int (*clear_tz_irq)(const struct acpm_handle *handle, + unsigned int acpm_chan_id, u8 tz); + int (*suspend)(const struct acpm_handle *handle, + unsigned int acpm_chan_id); + int (*resume)(const struct acpm_handle *handle, + unsigned int acpm_chan_id); +}; + struct acpm_ops { struct acpm_dvfs_ops dvfs_ops; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:15 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:33 +0000 Subject: [PATCH 5/8] thermal: samsung: Add support for GS101 TMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-5-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=19726; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=ycpTTuEHw1ktY5WMh2z4gJLM2jmFjBFEmH6MdKsS1So=; b=eED9yiRauzhGXIgeGdYP5CwjdKHFDJEMMA2jDrY3zoMHdeoGBrrHvA2fJnMVrzxv0icVFiP08 E4szHaZjxIhBFGBoK34KNK6iumTx+q0/C0Bs40VtYBaHp9BEPIjgYf6 X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the thermal driver for the Google GS101 SoC. The GS101 TMU architecture involves a split responsibility between the kernel and the Alive Core and Power Manager (ACPM) firmware. The kernel is responsible for mapping the interrupt pending registers via syscon to identify thermal events, while the firmware handles sensor configuration, threshold setting, and interrupt acknowledgment via the ACPM protocol. Signed-off-by: Tudor Ambarus --- drivers/thermal/samsung/Kconfig | 16 + drivers/thermal/samsung/Makefile | 2 + drivers/thermal/samsung/acpm-tmu.c | 638 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 656 insertions(+) diff --git a/drivers/thermal/samsung/Kconfig b/drivers/thermal/samsung/Kcon= fig index f4eff5a41a84ce02b12abb85d6a0f8818031d0dc..dfe1c19e982f407e6d8acd65958= ee39d671c6924 100644 --- a/drivers/thermal/samsung/Kconfig +++ b/drivers/thermal/samsung/Kconfig @@ -9,3 +9,19 @@ config EXYNOS_THERMAL the TMU, reports temperature and handles cooling action if defined. This driver uses the Exynos core thermal APIs and TMU configuration data from the supported SoCs. + +config EXYNOS_ACPM_THERMAL + tristate "Exynos ACPM thermal management unit driver" + depends on THERMAL_OF + depends on EXYNOS_ACPM_PROTOCOL || (COMPILE_TEST && !EXYNOS_ACPM_PROTOCOL) + help + Support for the Thermal Management Unit (TMU) on Google GS101 SoC. + + The TMU on GS101 is managed by the Alive Clock and Power Manager + (ACPM) firmware. This driver handles the kernel-side interaction, + including reading interrupt status registers via syscon and + communicating with the firmware via the ACPM protocol for + configuration and thermal events. + + Select this if you want to monitor device temperature and enable + thermal mitigation on GS101 based devices. diff --git a/drivers/thermal/samsung/Makefile b/drivers/thermal/samsung/Mak= efile index f139407150d26940fc9ffcf000505cea4866223f..daed80647c349ba4f937ed8fbe6= be9df06c34aac 100644 --- a/drivers/thermal/samsung/Makefile +++ b/drivers/thermal/samsung/Makefile @@ -4,3 +4,5 @@ # obj-$(CONFIG_EXYNOS_THERMAL) +=3D exynos_thermal.o exynos_thermal-y :=3D exynos_tmu.o +obj-$(CONFIG_EXYNOS_ACPM_THERMAL) +=3D exynos_acpm_thermal.o +exynos_acpm_thermal-y :=3D acpm-tmu.o diff --git a/drivers/thermal/samsung/acpm-tmu.c b/drivers/thermal/samsung/a= cpm-tmu.c new file mode 100644 index 0000000000000000000000000000000000000000..f6ae4c7815421e684d4ea7ac7a4= 86a9968292324 --- /dev/null +++ b/drivers/thermal/samsung/acpm-tmu.c @@ -0,0 +1,638 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2019 Samsung Electronics Co., Ltd. + * Copyright 2025 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../thermal_hwmon.h" + +#define EXYNOS_TMU_SENSOR(i) BIT(i) +#define EXYNOS_TMU_SENSORS_MAX_COUNT 16 + +#define GS101_CPUCL2_SENSOR_MASK (EXYNOS_TMU_SENSOR(0) | \ + EXYNOS_TMU_SENSOR(6) | \ + EXYNOS_TMU_SENSOR(7) | \ + EXYNOS_TMU_SENSOR(8) | \ + EXYNOS_TMU_SENSOR(9)) +#define GS101_CPUCL1_SENSOR_MASK (EXYNOS_TMU_SENSOR(4) | \ + EXYNOS_TMU_SENSOR(5)) +#define GS101_CPUCL0_SENSOR_MASK (EXYNOS_TMU_SENSOR(1) | \ + EXYNOS_TMU_SENSOR(2)) + +#define GS101_REG_INTPEND(i) ((i) * 0x50 + 0xf8) + +enum { + P0_INTPEND, + P1_INTPEND, + P2_INTPEND, + P3_INTPEND, + P4_INTPEND, + P5_INTPEND, + P6_INTPEND, + P7_INTPEND, + P8_INTPEND, + P9_INTPEND, + P10_INTPEND, + P11_INTPEND, + P12_INTPEND, + P13_INTPEND, + P14_INTPEND, + P15_INTPEND, + REG_INTPEND_COUNT, +}; + +struct acpm_tmu_sensor_group { + u16 mask; + u8 id; +}; + +struct acpm_tmu_sensor { + const struct acpm_tmu_sensor_group *group; + struct thermal_zone_device *tzd; + struct acpm_tmu_priv *priv; + struct mutex lock; /* protects sensor state */ + bool enabled; +}; + +struct acpm_tmu_priv { + struct regmap_field *regmap_fields[REG_INTPEND_COUNT]; + const struct acpm_handle *handle; + struct device *dev; + struct clk *clk; + unsigned int mbox_chan_id; + unsigned int num_sensors; + int irq; + struct acpm_tmu_sensor sensors[] __counted_by(num_sensors); +}; + +struct acpm_tmu_driver_data { + const struct reg_field *syscon_reg_fields; + const struct acpm_tmu_sensor_group *sensor_groups; + unsigned int num_sensor_groups; + unsigned int mbox_chan_id; +}; + +struct acpm_tmu_initialize_tripwalkdata { + unsigned char threshold[8]; + unsigned char hysteresis[8]; + unsigned char inten; + int i; +}; + +struct acpm_tmu_trip_temp_tripwalkdata { + const struct thermal_trip *trip; + unsigned char threshold[8]; + int temperature; + int i; +}; + +#define ACPM_TMU_SENSOR_GROUP(_mask, _id) \ + { \ + .mask =3D _mask, \ + .id =3D _id, \ + } + +static const struct acpm_tmu_sensor_group gs101_sensor_groups[] =3D { + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL2_SENSOR_MASK, 0), + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL1_SENSOR_MASK, 1), + ACPM_TMU_SENSOR_GROUP(GS101_CPUCL0_SENSOR_MASK, 2), +}; + +static const struct reg_field gs101_syscon_tmu_reg_fields[REG_INTPEND_COUN= T] =3D { + [P0_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(0), 0, 31), + [P1_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(1), 0, 31), + [P2_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(2), 0, 31), + [P3_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(3), 0, 31), + [P4_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(4), 0, 31), + [P5_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(5), 0, 31), + [P6_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(6), 0, 31), + [P7_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(7), 0, 31), + [P8_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(8), 0, 31), + [P9_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(9), 0, 31), + [P10_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(10), 0, 31), + [P11_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(11), 0, 31), + [P12_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(12), 0, 31), + [P13_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(13), 0, 31), + [P14_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(14), 0, 31), + [P15_INTPEND] =3D REG_FIELD(GS101_REG_INTPEND(15), 0, 31), +}; + +static const struct acpm_tmu_driver_data acpm_tmu_gs101 =3D { + .syscon_reg_fields =3D gs101_syscon_tmu_reg_fields, + .sensor_groups =3D gs101_sensor_groups, + .num_sensor_groups =3D ARRAY_SIZE(gs101_sensor_groups), + .mbox_chan_id =3D 9, +}; + +static int acpm_tmu_op_tz_control(struct acpm_tmu_sensor *sensor, bool on) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + int ret; + + ret =3D ops->tz_control(handle, priv->mbox_chan_id, sensor->group->id, + on); + if (ret) + return ret; + + sensor->enabled =3D on; + + return 0; +} + +static int acpm_tmu_control(struct acpm_tmu_priv *priv, bool on) +{ + struct device *dev =3D priv->dev; + int i, ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + + /* Skip sensors that weren't found in DT */ + if (!sensor->tzd) + continue; + + scoped_guard(mutex, &sensor->lock) { + ret =3D acpm_tmu_op_tz_control(sensor, on); + } + + if (ret) + goto out; + } + +out: + pm_runtime_put_autosuspend(dev); + return ret; +} + +static int acpm_tmu_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct acpm_tmu_sensor *sensor =3D thermal_zone_device_priv(tz); + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + struct device *dev =3D priv->dev; + int acpm_temp, ret; + + if (!sensor->enabled) + return -EAGAIN; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + scoped_guard(mutex, &sensor->lock) { + ret =3D ops->read_temp(handle, priv->mbox_chan_id, + sensor->group->id, &acpm_temp); + } + + pm_runtime_put_autosuspend(dev); + + if (ret) + return ret; + + *temp =3D acpm_temp * MILLIDEGREE_PER_DEGREE; + + return 0; +} + +static int acpm_tmu_trip_temp_walk_cb(struct thermal_trip *trip, void *dat= a) +{ + struct acpm_tmu_trip_temp_tripwalkdata * const twd =3D data; + int temperature; + + if (twd->i >=3D ARRAY_SIZE(twd->threshold)) + return -ERANGE; + + if (trip->type =3D=3D THERMAL_TRIP_PASSIVE) + goto out; + + temperature =3D (trip =3D=3D twd->trip) ? twd->temperature : trip->temper= ature; + + twd->threshold[twd->i] =3D temperature / MILLIDEGREE_PER_DEGREE; + +out: + ++twd->i; + return 0; +} + +static int acpm_tmu_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temperature) +{ + struct acpm_tmu_sensor *sensor =3D thermal_zone_device_priv(tz); + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + struct device *dev =3D priv->dev; + struct acpm_tmu_trip_temp_tripwalkdata twd =3D { + .trip =3D trip, + .temperature =3D temperature, + }; + int ret; + + if (trip->type =3D=3D THERMAL_TRIP_PASSIVE) + return 0; + + for_each_thermal_trip(tz, acpm_tmu_trip_temp_walk_cb, &twd); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + guard(mutex)(&sensor->lock); + + if (!sensor->enabled) { + ret =3D ops->set_threshold(handle, priv->mbox_chan_id, + sensor->group->id, twd.threshold, + ARRAY_SIZE(twd.threshold)); + goto out; + } + + ret =3D acpm_tmu_op_tz_control(sensor, false); + if (ret) + goto out; + + ret =3D ops->set_threshold(handle, priv->mbox_chan_id, sensor->group->id, + twd.threshold, ARRAY_SIZE(twd.threshold)); + if (ret) + goto out; + + ret =3D acpm_tmu_op_tz_control(sensor, true); + +out: + pm_runtime_put_autosuspend(dev); + return ret; +} + +static const struct thermal_zone_device_ops acpm_tmu_sensor_ops =3D { + .get_temp =3D acpm_tmu_get_temp, + .set_trip_temp =3D acpm_tmu_set_trip_temp, +}; + +static int acpm_tmu_has_pending_irq(struct acpm_tmu_sensor *sensor, + bool *pending_irq) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + unsigned long mask =3D sensor->group->mask; + int i, ret; + u32 val; + + guard(mutex)(&sensor->lock); + + for_each_set_bit(i, &mask, EXYNOS_TMU_SENSORS_MAX_COUNT) { + ret =3D regmap_field_read(priv->regmap_fields[i], &val); + if (ret) + return ret; + + if (val) { + *pending_irq =3D true; + break; + } + } + + return 0; +} + +static irqreturn_t acpm_tmu_thread_fn(int irq, void *id) +{ + struct acpm_tmu_priv *priv =3D id; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + struct device *dev =3D priv->dev; + int i, ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) { + dev_err(dev, "Failed to resume: %d\n", ret); + return IRQ_NONE; + } + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + bool pending_irq =3D false; + + if (!sensor->tzd) + continue; + + ret =3D acpm_tmu_has_pending_irq(sensor, &pending_irq); + if (ret || !pending_irq) + continue; + + thermal_zone_device_update(sensor->tzd, + THERMAL_EVENT_UNSPECIFIED); + + scoped_guard(mutex, &sensor->lock) { + ret =3D ops->clear_tz_irq(handle, priv->mbox_chan_id, + sensor->group->id); + if (ret) + dev_err(priv->dev, "Sensor %d: failed to clear IRQ (%d)\n", + i, ret); + } + } + + pm_runtime_put_autosuspend(dev); + + return IRQ_HANDLED; +} + +static int acpm_tmu_init_sensor(struct acpm_tmu_sensor *sensor, + const struct acpm_tmu_initialize_tripwalkdata *twd) +{ + struct acpm_tmu_priv *priv =3D sensor->priv; + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + unsigned int mbox_chan_id =3D priv->mbox_chan_id; + u8 acpm_sensor_id =3D sensor->group->id; + int ret; + + guard(mutex)(&sensor->lock); + + ret =3D ops->set_threshold(handle, mbox_chan_id, acpm_sensor_id, + twd->threshold, + ARRAY_SIZE(twd->threshold)); + if (ret) + return ret; + + ret =3D ops->set_hysteresis(handle, mbox_chan_id, acpm_sensor_id, + twd->hysteresis, + ARRAY_SIZE(twd->threshold)); + if (ret) + return ret; + + ret =3D ops->set_interrupt_enable(handle, mbox_chan_id, acpm_sensor_id, + twd->inten); + return ret; +} + +static int acpm_tmu_initialize_walk_cb(struct thermal_trip *trip, void *da= ta) +{ + struct acpm_tmu_initialize_tripwalkdata * const twd =3D data; + int i; + + if (twd->i >=3D ARRAY_SIZE(twd->threshold)) + return -ERANGE; + + if (trip->type =3D=3D THERMAL_TRIP_PASSIVE) + goto out; + + i =3D twd->i; + + twd->threshold[i] =3D trip->temperature / MILLIDEGREE_PER_DEGREE; + twd->hysteresis[i] =3D trip->hysteresis / MILLIDEGREE_PER_DEGREE; + + twd->inten |=3D BIT(i); + +out: + ++twd->i; + return 0; +} + +static int acpm_tmu_init_sensors(struct acpm_tmu_priv *priv) +{ + int i, ret; + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + struct acpm_tmu_initialize_tripwalkdata twd =3D {}; + + /* Skip sensors that weren't found in DT */ + if (!sensor->tzd) + continue; + + thermal_zone_for_each_trip(sensor->tzd, + acpm_tmu_initialize_walk_cb, &twd); + + ret =3D acpm_tmu_init_sensor(sensor, &twd); + if (ret) + return ret; + } + + return 0; +} + +static const struct of_device_id acpm_tmu_match[] =3D { + { .compatible =3D "google,gs101-tmu-top", .data =3D &acpm_tmu_gs101 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, acpm_tmu_match); + +static int acpm_tmu_probe(struct platform_device *pdev) +{ + const struct acpm_tmu_driver_data *data; + const struct acpm_handle *acpm_handle; + struct device *dev =3D &pdev->dev; + struct acpm_tmu_priv *priv; + struct regmap *regmap; + int i, ret; + + acpm_handle =3D devm_acpm_get_by_node(dev, dev->parent->of_node); + if (IS_ERR(acpm_handle)) + return dev_err_probe(dev, PTR_ERR(acpm_handle), + "Failed to get ACPM handle\n"); + + data =3D of_device_get_match_data(dev); + if (!data) + return dev_err_probe(dev, -EINVAL, + "Failed to get match data\n"); + + priv =3D devm_kzalloc(dev, + struct_size(priv, sensors, data->num_sensor_groups), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev =3D dev; + priv->handle =3D acpm_handle; + priv->mbox_chan_id =3D data->mbox_chan_id; + priv->num_sensors =3D data->num_sensor_groups; + + platform_set_drvdata(pdev, priv); + + regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "syscon"); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Unable to map syscon\n"); + + ret =3D devm_regmap_field_bulk_alloc(dev, regmap, priv->regmap_fields, + data->syscon_reg_fields, + REG_INTPEND_COUNT); + if (ret) + return dev_err_probe(dev, ret, + "Unable to map syscon registers\n"); + + priv->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "Failed to get the clock\n"); + + priv->irq =3D platform_get_irq(pdev, 0); + if (priv->irq < 0) + return dev_err_probe(dev, priv->irq, "Failed to get irq\n"); + + ret =3D devm_request_threaded_irq(dev, priv->irq, NULL, + acpm_tmu_thread_fn, IRQF_ONESHOT, + dev_name(dev), priv); + if (ret) + return dev_err_probe(dev, ret, "Failed to request irq\n"); + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to resume device\n"); + + ret =3D acpm_handle->ops.tmu.init(acpm_handle, priv->mbox_chan_id); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to init TMU\n"); + goto err_pm_put; + } + + for (i =3D 0; i < priv->num_sensors; i++) { + struct acpm_tmu_sensor *sensor =3D &priv->sensors[i]; + + mutex_init(&sensor->lock); + sensor->group =3D &data->sensor_groups[i]; + sensor->priv =3D priv; + + sensor->tzd =3D devm_thermal_of_zone_register(dev, i, sensor, + &acpm_tmu_sensor_ops); + if (IS_ERR(sensor->tzd)) { + ret =3D PTR_ERR(sensor->tzd); + if (ret =3D=3D -ENODEV) { + sensor->tzd =3D NULL; + dev_dbg(dev, "Sensor %d not used in DT, skipping\n", i); + continue; + } + + ret =3D dev_err_probe(dev, ret, "Failed to register sensor %d\n", i); + goto err_pm_put; + } + + ret =3D devm_thermal_add_hwmon_sysfs(dev, sensor->tzd); + if (ret) + dev_warn(dev, "Failed to add hwmon sysfs!\n"); + } + + ret =3D acpm_tmu_init_sensors(priv); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to init sensors\n"); + goto err_pm_put; + } + + ret =3D acpm_tmu_control(priv, true); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Failed to enable TMU\n"); + goto err_pm_put; + } + + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +err_pm_put: + pm_runtime_put_sync(dev); + return ret; +} + +static void acpm_tmu_remove(struct platform_device *pdev) +{ + struct acpm_tmu_priv *priv =3D platform_get_drvdata(pdev); + + /* Stop IRQ first to prevent race with thread_fn */ + disable_irq(priv->irq); + + acpm_tmu_control(priv, false); +} + +static int acpm_tmu_suspend(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + int ret; + + ret =3D acpm_tmu_control(priv, false); + if (ret) + return ret; + + /* APB clock not required for this specific msg */ + return ops->suspend(handle, priv->mbox_chan_id); +} + +static int acpm_tmu_resume(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + const struct acpm_handle *handle =3D priv->handle; + const struct acpm_tmu_ops *ops =3D &handle->ops.tmu; + int ret; + + /* APB clock not required for this specific msg */ + ret =3D ops->resume(handle, priv->mbox_chan_id); + if (ret) + return ret; + + return acpm_tmu_control(priv, true); +} + +static int acpm_tmu_runtime_suspend(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int acpm_tmu_runtime_resume(struct device *dev) +{ + struct acpm_tmu_priv *priv =3D dev_get_drvdata(dev); + + return clk_prepare_enable(priv->clk); +} + +static const struct dev_pm_ops acpm_tmu_pm_ops =3D { + SYSTEM_SLEEP_PM_OPS(acpm_tmu_suspend, acpm_tmu_resume) + RUNTIME_PM_OPS(acpm_tmu_runtime_suspend, acpm_tmu_runtime_resume, NULL) +}; + +static struct platform_driver acpm_tmu_driver =3D { + .driver =3D { + .name =3D "gs-tmu", + .pm =3D pm_ptr(&acpm_tmu_pm_ops), + .of_match_table =3D acpm_tmu_match, + }, + .probe =3D acpm_tmu_probe, + .remove =3D acpm_tmu_remove, +}; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:16 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:34 +0000 Subject: [PATCH 6/8] MAINTAINERS: Add entry for Samsung Exynos ACPM thermal driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-6-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. 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Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=971; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=7HVJFrG3U/QwDFKx95QyYbsMuRfAm1hbMd+GcbM229I=; b=pUkUka+ewej0krIsviJjojhdqN6KPY64IUp5KIuBVVECn9qSsLgLN4eTbUtjxiRCJF+4NmjV0 aVbDoNVDAOlDzQjkDBwgjyH42sK2PdrvjnCTG1nPFaq9xixN3Ygv0sh X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add a MAINTAINERS entry for the Samsung Exynos ACPM thermal driver. Signed-off-by: Tudor Ambarus --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5b11839cba9de1e9e43f63787578edd8c429ca39..ab44f2de8e8e03ad9bb022ebdf1= b6c0058fb0425 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23171,6 +23171,14 @@ F: drivers/clk/samsung/clk-acpm.c F: drivers/firmware/samsung/exynos-acpm* F: include/linux/firmware/samsung/exynos-acpm-protocol.h =20 +SAMSUNG EXYNOS ACPM THERMAL DRIVER +M: Tudor Ambarus +L: linux-kernel@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/thermal/google,gs101-tmu-top.yaml +F: drivers/thermal/samsung/acpm-tmu.c + SAMSUNG EXYNOS MAILBOX DRIVER M: Tudor Ambarus L: linux-kernel@vger.kernel.org --=20 2.52.0.457.g6b5491de43-goog From nobody Sun Feb 8 20:59:11 2026 Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE74237F8AF for ; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:17 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:35 +0000 Subject: [PATCH 7/8] arm64: dts: exynos: gs101: Add thermal management unit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-7-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=9008; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=5H0lgDSUScoa7O0SKdxLcVIZHcB9BT1ur3Jx/KZwF8M=; b=HXnagG3gv/1lLforBYx+5nePgwHPOp9Z1Gwl0BqqQvYoXOb/bhmpCS7TdePLVZg19tC4RNUjf WV7Y7zCenC7CfdPS4WtdHlZAotXST1JrJmm7B/XOVq99Prf7aEloUTU X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Add the Thermal Management Unit (TMU) nodes for the Google GS101 SoC. This includes: - The top-level TMU sensor node linked to the ACPM block. - The TMU syscon node for direct interrupt register access. - Thermal zones for the CPU clusters (little, mid, big) with associated trip points and cooling maps. This enables thermal monitoring and mitigation on GS101 based devices. Signed-off-by: Tudor Ambarus --- arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi | 209 +++++++++++++++++++= ++++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 22 +++ 2 files changed, 231 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi b/arch/arm64/= boot/dts/exynos/google/gs101-tmu.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6262c3b890aa2f7ad572c32b30b= f926df804ec1e --- /dev/null +++ b/arch/arm64/boot/dts/exynos/google/gs101-tmu.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Google GS101 TMU configurations device tree source + * + * Copyright 2020 Samsung Electronics Co., Ltd. + * Copyright 2020 Google LLC. + * Copyright 2026 Linaro Ltd. + */ + +#include + +/ { + thermal-zones { + cpucl2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 0>; + + trips { + big_cold: big-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_switch_on: big-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_control_temp: big-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + big_pre_switch_on: big-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + big_alert2: big-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hw_throttling: big-hw-throttling { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_pause: big-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + big_hot: big-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&big_control_temp>; + cooling-device =3D <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + mid_cold: mid-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_switch_on: mid-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_control_temp: mid-control-temp { + temperature =3D <90000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + mid_pre_switch_on: mid-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + mid_alert2: mid-alert2 { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hw_throttling: mid-hw-throttling { + temperature =3D <98000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_pause: mid-pause { + temperature =3D <108000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + mid_hot: mid-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&mid_control_temp>; + cooling-device =3D <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpucl0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 2>; + + trips { + little_cold: little-cold { + temperature =3D <20000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_switch_on: little-switch-on { + temperature =3D <70000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_control_temp: little-control-temp { + temperature =3D <95000>; + hysteresis =3D <5000>; + type =3D "passive"; + }; + + little_pre_switch_on: little-pre-switch-on { + temperature =3D <55000>; + hysteresis =3D <2000>; + type =3D "active"; + }; + + little_alert2: little-alert2 { + temperature =3D <100000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert5: little-alert5 { + temperature =3D <103000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_alert6: little-alert6 { + temperature =3D <110000>; + hysteresis =3D <5000>; + type =3D "active"; + }; + + little_hot: little-hot { + temperature =3D <115000>; + hysteresis =3D <3000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&little_control_temp>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index 48f3819590cf8c05d6bd7241cfed8720149c7db4..a2d5ed832588b83ec47e8c68330= 73c9ec95f2517 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -74,6 +74,7 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a55"; reg =3D <0x0000>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -86,6 +87,7 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a55"; reg =3D <0x0100>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -98,6 +100,7 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a55"; reg =3D <0x0200>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -110,6 +113,7 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a55"; reg =3D <0x0300>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&ananke_cpu_sleep>; capacity-dmips-mhz =3D <250>; @@ -122,6 +126,7 @@ cpu4: cpu@400 { compatible =3D "arm,cortex-a76"; reg =3D <0x0400>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -134,6 +139,7 @@ cpu5: cpu@500 { compatible =3D "arm,cortex-a76"; reg =3D <0x0500>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&enyo_cpu_sleep>; capacity-dmips-mhz =3D <620>; @@ -146,6 +152,7 @@ cpu6: cpu@600 { compatible =3D "arm,cortex-x1"; reg =3D <0x0600>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -158,6 +165,7 @@ cpu7: cpu@700 { compatible =3D "arm,cortex-x1"; reg =3D <0x0700>; clocks =3D <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>; + #cooling-cells =3D <2>; enable-method =3D "psci"; cpu-idle-states =3D <&hera_cpu_sleep>; capacity-dmips-mhz =3D <1024>; @@ -489,6 +497,14 @@ acpm_ipc: power-management { #clock-cells =3D <1>; mboxes =3D <&ap2apm_mailbox>; shmem =3D <&apm_sram>; + + tmu_top: thermal-sensor { + compatible =3D "google,gs101-tmu-top"; + clocks =3D <&cmu_misc CLK_GOUT_MISC_TMU_TOP_PCLK>; + interrupts =3D ; + syscon =3D <&tmu_top_syscon>; + #thermal-sensor-cells =3D <1>; + }; }; }; =20 @@ -639,6 +655,11 @@ watchdog_cl1: watchdog@10070000 { status =3D "disabled"; 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[35.240.102.164]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47ee57a2613sm29595445e9.6.2026.01.14.06.17.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jan 2026 06:17:18 -0800 (PST) From: Tudor Ambarus Date: Wed, 14 Jan 2026 14:16:36 +0000 Subject: [PATCH 8/8] arm64: defconfig: enable Exynos ACPM thermal support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260114-acpm-tmu-v1-8-cfe56d93e90f@linaro.org> References: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> In-Reply-To: <20260114-acpm-tmu-v1-0-cfe56d93e90f@linaro.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= , Bartlomiej Zolnierkiewicz , Kees Cook , "Gustavo A. R. Silva" Cc: willmcvicker@google.com, jyescas@google.com, shin.son@samsung.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-hardening@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1768400224; l=969; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=4R2WX+ZJeXKAug4HVmP5YDimNXbTtbG2dMJBRwWnt8o=; b=VnsK9/fLTj9mjFXQo/4xOaDgDR3JfubzIq3NbGbuODD2OJ1c6XHTPf+LI9LbcMoZ3NCIW9wy/ IJLw4Q7eeDiAhz67Bq9hsH5OJkql4RdLF5r4fJcduQpSKMK/g4HWwqv X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Enable the Exynos ACPM thermal driver (CONFIG_EXYNOS_ACPM_THERMAL) to allow temperature monitoring and thermal management on Samsung Exynos SoCs that use the Alive Clock and Power Manager (ACPM) protocol. This ensures that thermal zones are properly exposed and handled on platforms such as the GS101. Signed-off-by: Tudor Ambarus --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 45288ec9eaf7365427d98195c48e2f8065a8bb1b..1bfe37857f51663c9d745cd575f= 107fef183008f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -752,6 +752,7 @@ CONFIG_BCM2711_THERMAL=3Dm CONFIG_BCM2835_THERMAL=3Dm CONFIG_BRCMSTB_THERMAL=3Dm CONFIG_EXYNOS_THERMAL=3Dy +CONFIG_EXYNOS_ACPM_THERMAL=3Dy CONFIG_TEGRA_SOCTHERM=3Dm CONFIG_TEGRA_BPMP_THERMAL=3Dm CONFIG_GENERIC_ADC_THERMAL=3Dm --=20 2.52.0.457.g6b5491de43-goog