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Wysocki" , Len Brown , Bjorn Helgaas , Greg Kroah-Hartman , Kenji Kaneshige Cc: =?UTF-8?q?H=C3=A5kon=20Bugge?= , linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] PCI/ACPI: Confine program_hpx_type2 to the AER bits Date: Tue, 13 Jan 2026 18:15:20 +0100 Message-ID: <20260113171522.3446407-1-haakon.bugge@oracle.com> X-Mailer: git-send-email 2.43.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-13_04,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 mlxscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2512120000 definitions=main-2601130144 X-Proofpoint-ORIG-GUID: 6tYubRi1b2uYOr6BuduKNDOcCzX90x4P X-Authority-Analysis: v=2.4 cv=YKOSCBGx c=1 sm=1 tr=0 ts=69667daf cx=c_pps a=OOZaFjgC48PWsiFpTAqLcw==:117 a=OOZaFjgC48PWsiFpTAqLcw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=M51BFTxLslgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=yPCof4ZbAAAA:8 a=4OF2stnPnCnJDZRIKM8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEzMDE0MyBTYWx0ZWRfX67cRX88Et4Zi yNQeui5xGdmQsw+7lPvCWomV7Z3wGzkjF3JPAZoBDZ470sYg3lEUUDiR04LwphuReHdynWroVx0 HWL81WYfPiO+WTUg/bLZ0iunPb/pNxIbY8OT7nmqEzUK10QuaP/+MkNuUAe3Oxcb1IZ6eUAPIeR hlo2FcLCHFdK6GrhwdhWuI64Wh7B7BSk4yOgzS7mtIDqonVad6feEzo6m/YjZlZtmgc0sNSnW1M 6pSaPv0JnIPPZheXMhs6nGzPKEyfRNPfXsGPb+fiMeBPUP9bHnWVgWURBtRmhsJTjXkKOxEvGHh kdRYVHQcbFh3quAA50xEv+yJeP0/xQmrS4O0rb29BP39Dt9J6EYqnqHATAzsCtri2X5jSTkDOsj f6kYkSJNDVx2UexJFYdelIW61QJxXP2lSSw1UTgCe4tj1WVEWi+hRrnNFjXuYq0tqrRXiQ/19BD 42I5PqR27sHkUeYoAPA== X-Proofpoint-GUID: 6tYubRi1b2uYOr6BuduKNDOcCzX90x4P program_hpx_type2() is today unconditionally called, despite the fact that when the _HPX was added to the ACPI spec. v3.0, the description stated: OSPM [1] will only evaluate _HPX with Setting Record =E2=80=93 Type 2 if O= SPM is not controlling the PCI Express Advanced Error Reporting capability. Hence, we only call program_hpx_type2() when the OSPM owns the PCIe hotplug capability but not the AER. The Advanced Configuration and Power Interface (ACPI) Specification version 6.6 has a provision that gives the OSPM the ability to control the other PCIe Device Control bits any way. In a note in section 6.2.9, it is stated: "OSPM may override the settings provided by the _HPX object's Type2 record (PCI Express Settings) or Type3 record (PCI Express Descriptor Settings) when OSPM has assumed native control of the corresponding feature." So, in order to preserve the non-AER bits in PCIe Device Control, in particular the performance sensitive ExtTag and RO, we make sure program_hpx_type2() if called, doesn't modify any non-AER bits. Also, when program_hpx_type2() is called, and any bits in the PCIe Link Control register is set, we log a warning. [1] Operating System-directed configuration and Power Management Fixes: 40abb96c51bb ("[PATCH] pciehp: Fix programming hotplug parameters") Signed-off-by: H=C3=A5kon Bugge --- drivers/pci/pci-acpi.c | 71 ++++++++++++++++++++++-------------------- 1 file changed, 37 insertions(+), 34 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9369377725fa0..f36b51f6721a6 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -271,21 +271,6 @@ static acpi_status decode_type1_hpx_record(union acpi_= object *record, return AE_OK; } =20 -static bool pcie_root_rcb_set(struct pci_dev *dev) -{ - struct pci_dev *rp =3D pcie_find_root_port(dev); - u16 lnkctl; - - if (!rp) - return false; - - pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl); - if (lnkctl & PCI_EXP_LNKCTL_RCB) - return true; - - return false; -} - /* _HPX PCI Express Setting Record (Type 2) */ struct hpx_type2 { u32 revision; @@ -311,6 +296,7 @@ static void program_hpx_type2(struct pci_dev *dev, stru= ct hpx_type2 *hpx) { int pos; u32 reg32; + const struct pci_host_bridge *host; =20 if (!hpx) return; @@ -318,40 +304,57 @@ static void program_hpx_type2(struct pci_dev *dev, st= ruct hpx_type2 *hpx) if (!pci_is_pcie(dev)) return; =20 + host =3D pci_find_host_bridge(dev->bus); + + /* We only do the HP programming if we own the PCIe native + * hotplug and not the AER ownership + */ + if (!host->native_pcie_hotplug || host->native_aer) + return; + if (hpx->revision > 1) { pci_warn(dev, "PCIe settings rev %d not supported\n", hpx->revision); return; } =20 - /* - * Don't allow _HPX to change MPS or MRRS settings. We manage - * those to make sure they're consistent with the rest of the + /* We only allow _HPX to program the AER registers, namely + * PCI_EXP_DEVCTL_CERE, PCI_EXP_DEVCTL_NFERE, + * PCI_EXP_DEVCTL_FERE, and PCI_EXP_DEVCTL_URRE. + * + * The other settings in PCIe DEVCTL are managed by OS in + * order to make sure they're consistent with the rest of the * platform. */ - hpx->pci_exp_devctl_and |=3D PCI_EXP_DEVCTL_PAYLOAD | - PCI_EXP_DEVCTL_READRQ; - hpx->pci_exp_devctl_or &=3D ~(PCI_EXP_DEVCTL_PAYLOAD | - PCI_EXP_DEVCTL_READRQ); + hpx->pci_exp_devctl_and |=3D PCI_EXP_DEVCTL_RELAX_EN | + PCI_EXP_DEVCTL_PAYLOAD | + PCI_EXP_DEVCTL_EXT_TAG | + PCI_EXP_DEVCTL_PHANTOM | + PCI_EXP_DEVCTL_AUX_PME | + PCI_EXP_DEVCTL_NOSNOOP_EN | + PCI_EXP_DEVCTL_READRQ | + PCI_EXP_DEVCTL_BCR_FLR; + hpx->pci_exp_devctl_or &=3D ~(PCI_EXP_DEVCTL_RELAX_EN | + PCI_EXP_DEVCTL_PAYLOAD | + PCI_EXP_DEVCTL_EXT_TAG | + PCI_EXP_DEVCTL_PHANTOM | + PCI_EXP_DEVCTL_AUX_PME | + PCI_EXP_DEVCTL_NOSNOOP_EN | + PCI_EXP_DEVCTL_READRQ | + PCI_EXP_DEVCTL_BCR_FLR); =20 /* Initialize Device Control Register */ pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL, ~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or); =20 - /* Initialize Link Control Register */ + /* Log the Link Control Register if any bits are set */ if (pcie_cap_has_lnkctl(dev)) { + u16 lnkctl; =20 - /* - * If the Root Port supports Read Completion Boundary of - * 128, set RCB to 128. Otherwise, clear it. - */ - hpx->pci_exp_lnkctl_and |=3D PCI_EXP_LNKCTL_RCB; - hpx->pci_exp_lnkctl_or &=3D ~PCI_EXP_LNKCTL_RCB; - if (pcie_root_rcb_set(dev)) - hpx->pci_exp_lnkctl_or |=3D PCI_EXP_LNKCTL_RCB; - - pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, - ~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or); + pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnkctl); + if (lnkctl) + pci_warn(dev, "Some bits in PCIe Link Control are set: 0x%04x\n", + lnkctl); } =20 /* Find Advanced Error Reporting Enhanced Capability */ --=20 2.43.5