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charset="utf-8" Introduce a new EPC feature bit (dynamic_inbound_mapping) that indicates whether an Endpoint Controller can update the inbound address translation for a BAR without requiring the EPF driver to clear/reset the BAR first. Endpoint Function drivers (e.g. vNTB) can use this information to decide whether it really is safe to call pci_epc_set_bar() multiple times to update inbound mappings for the BAR. Suggested-by: Niklas Cassel Reviewed-by: Niklas Cassel Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- include/linux/pci-epc.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 4286bfdbfdfa..4c8516756c56 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -223,6 +223,10 @@ struct pci_epc_bar_desc { /** * struct pci_epc_features - features supported by a EPC device per functi= on * @linkup_notifier: indicate if the EPC device can notify EPF driver on l= ink up + * @dynamic_inbound_mapping: indicate if the EPC device supports updating + * inbound mappings for an already configured BAR + * (i.e. allow calling pci_epc_set_bar() again + * without first calling pci_epc_clear_bar()) * @msi_capable: indicate if the endpoint function has MSI capability * @msix_capable: indicate if the endpoint function has MSI-X capability * @intx_capable: indicate if the endpoint can raise INTx interrupts @@ -231,6 +235,7 @@ struct pci_epc_bar_desc { */ struct pci_epc_features { unsigned int linkup_notifier : 1; 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charset="utf-8" Extend the PCI endpoint core to support mapping subranges within a BAR. Introduce a new 'submap' field and a 'use_submap' flag in struct pci_epf_bar so an endpoint function driver can request inbound mappings that fully cover the BAR. Add a subrange_mapping feature bit to struct pci_epc_features so EPC drivers can explicitly advertise support. Make pci_epc_set_bar() reject use_submap requests (-EINVAL) when the EPC does not advertise subrange_mapping, to avoid silently accepting a configuration that the controller cannot implement. The submap array describes the complete BAR layout (no overlaps and no gaps are allowed to avoid exposing untranslated address ranges). This provides the generic infrastructure needed to map multiple logical regions into a single BAR at different offsets, without assuming a controller-specific inbound address translation mechanism. Also, the array must be sorted in ascending order by offset. Reviewed-by: Niklas Cassel Signed-off-by: Koichiro Den --- drivers/pci/endpoint/pci-epc-core.c | 5 +++++ include/linux/pci-epc.h | 4 ++++ include/linux/pci-epf.h | 31 +++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index ca7f19cc973a..4870e6cdb458 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -596,6 +596,11 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u= 8 vfunc_no, if (!epc_features) return -EINVAL; =20 + if (epf_bar->use_submap && + !(epc_features->dynamic_inbound_mapping && + epc_features->subrange_mapping)) + return -EINVAL; + if (epc_features->bar[bar].type =3D=3D BAR_RESIZABLE && (epf_bar->size < SZ_1M || (u64)epf_bar->size > (SZ_128G * 1024))) return -EINVAL; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 4c8516756c56..c021c7af175f 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -227,6 +227,9 @@ struct pci_epc_bar_desc { * inbound mappings for an already configured BAR * (i.e. allow calling pci_epc_set_bar() again * without first calling pci_epc_clear_bar()) + * @subrange_mapping: indicate if the EPC device can map inbound subranges= for a + * BAR. This feature depends on @dynamic_inbound_mapping + * feature. * @msi_capable: indicate if the endpoint function has MSI capability * @msix_capable: indicate if the endpoint function has MSI-X capability * @intx_capable: indicate if the endpoint can raise INTx interrupts @@ -236,6 +239,7 @@ struct pci_epc_bar_desc { struct pci_epc_features { unsigned int linkup_notifier : 1; unsigned int dynamic_inbound_mapping : 1; + unsigned int subrange_mapping : 1; unsigned int msi_capable : 1; unsigned int msix_capable : 1; unsigned int intx_capable : 1; diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 48f68c4dcfa5..91f2e3489cda 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -110,6 +110,28 @@ struct pci_epf_driver { =20 #define to_pci_epf_driver(drv) container_of_const((drv), struct pci_epf_dr= iver, driver) =20 +/** + * struct pci_epf_bar_submap - BAR subrange for inbound mapping + * @phys_addr: target physical/DMA address for this subrange + * @size: the size of the subrange to be mapped + * @offset: byte offset within the BAR base + * + * When pci_epf_bar.use_submap is set, pci_epf_bar.submap describes the + * complete BAR layout. This allows an EPC driver to program multiple + * inbound translation windows for a single BAR when supported by the + * controller. + * + * Note that the subranges: + * - must be non-overlapping + * - must exactly cover the BAR (i.e. no holes) + * - must be sorted (in ascending order by offset) + */ +struct pci_epf_bar_submap { + dma_addr_t phys_addr; + size_t size; + size_t offset; +}; + /** * struct pci_epf_bar - represents the BAR of EPF device * @phys_addr: physical address that should be mapped to the BAR @@ -119,6 +141,10 @@ struct pci_epf_driver { * requirement * @barno: BAR number * @flags: flags that are set for the BAR + * @use_submap: set true to request subrange mappings within this BAR + * @num_submap: number of entries in @submap + * @submap: array of subrange descriptors allocated by the caller. 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Tue, 13 Jan 2026 16:27:27 +0000 From: Koichiro Den To: jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, cassel@kernel.org Cc: vigneshr@ti.com, s-vadapalli@ti.com, hongxing.zhu@nxp.com, l.stach@pengutronix.de, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, jesper.nilsson@axis.com, heiko@sntech.de, srikanth.thokala@intel.com, marek.vasut+renesas@gmail.com, yoshihiro.shimoda.uh@renesas.com, geert+renesas@glider.be, magnus.damm@gmail.com, christian.bruel@foss.st.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, thierry.reding@gmail.com, jonathanh@nvidia.com, hayashi.kunihiko@socionext.com, mhiramat@kernel.org, kishon@kernel.org, jirislaby@kernel.org, rongqianfeng@vivo.com, 18255117159@163.com, shawn.lin@rock-chips.com, nicolas.frattaroli@collabora.com, linux.amoon@gmail.com, vidyas@nvidia.com, Frank.Li@nxp.com, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-tegra@vger.kernel.org Subject: [PATCH v7 3/6] PCI: dwc: Allow glue drivers to return mutable EPC features Date: Wed, 14 Jan 2026 01:27:16 +0900 Message-ID: <20260113162719.3710268-4-den@valinux.co.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260113162719.3710268-1-den@valinux.co.jp> References: <20260113162719.3710268-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TY4P301CA0013.JPNP301.PROD.OUTLOOK.COM (2603:1096:405:26f::19) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY7P286MB7722:EE_|TYWP286MB3400:EE_ X-MS-Office365-Filtering-Correlation-Id: 652379bb-589d-4c0d-b5c8-08de52c0a428 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016|10070799003; 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charset="utf-8" The DesignWare EP midlayer needs to advertise additional capabilities at the DWC layer (e.g. subrange_mapping) without duplicating the same bit in every DWC-based glue driver and without copying feature structures. Change dw_pcie_ep_ops.get_features() to return a mutable struct pci_epc_features * and update all DWC-based glue drivers accordingly. The DWC midlayer can then adjust/augment the returned features while still exposing a const struct pci_epc_features * to the PCI EPC core. No functional change on its own. Suggested-by: Niklas Cassel Reviewed-by: Niklas Cassel Signed-off-by: Koichiro Den --- drivers/pci/controller/dwc/pci-dra7xx.c | 4 +- drivers/pci/controller/dwc/pci-imx6.c | 10 ++-- drivers/pci/controller/dwc/pci-keystone.c | 4 +- .../pci/controller/dwc/pci-layerscape-ep.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 4 +- .../pci/controller/dwc/pcie-designware-plat.c | 4 +- drivers/pci/controller/dwc/pcie-designware.h | 2 +- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 8 +-- drivers/pci/controller/dwc/pcie-keembay.c | 4 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +- drivers/pci/controller/dwc/pcie-rcar-gen4.c | 4 +- drivers/pci/controller/dwc/pcie-stm32-ep.c | 4 +- drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- drivers/pci/controller/dwc/pcie-uniphier-ep.c | 58 ++++++++++--------- 14 files changed, 60 insertions(+), 56 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controll= er/dwc/pci-dra7xx.c index 01cfd9aeb0b8..e67f8b7b56cb 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -423,12 +423,12 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *e= p, u8 func_no, return 0; } =20 -static const struct pci_epc_features dra7xx_pcie_epc_features =3D { +static struct pci_epc_features dra7xx_pcie_epc_features =3D { .linkup_notifier =3D true, .msi_capable =3D true, }; =20 -static const struct pci_epc_features* +static struct pci_epc_features* dra7xx_pcie_get_features(struct dw_pcie_ep *ep) { return &dra7xx_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 4668fc9648bf..fe1de30b3df6 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -131,7 +131,7 @@ struct imx_pcie_drvdata { const u32 ltssm_mask; const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; - const struct pci_epc_features *epc_features; + struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); int (*core_reset)(struct imx_pcie *pcie, bool assert); @@ -1386,7 +1386,7 @@ static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *e= p, u8 func_no, return 0; } =20 -static const struct pci_epc_features imx8m_pcie_epc_features =3D { +static struct pci_epc_features imx8m_pcie_epc_features =3D { .msi_capable =3D true, .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, @@ -1395,7 +1395,7 @@ static const struct pci_epc_features imx8m_pcie_epc_f= eatures =3D { .align =3D SZ_64K, }; =20 -static const struct pci_epc_features imx8q_pcie_epc_features =3D { +static struct pci_epc_features imx8q_pcie_epc_features =3D { .msi_capable =3D true, .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, @@ -1415,13 +1415,13 @@ static const struct pci_epc_features imx8q_pcie_epc= _features =3D { * BAR4 | Enable | 32-bit | 1 MB | Programmable Size * BAR5 | Enable | 32-bit | 64 KB | Programmable Size */ -static const struct pci_epc_features imx95_pcie_epc_features =3D { +static struct pci_epc_features imx95_pcie_epc_features =3D { .msi_capable =3D true, .bar[BAR_1] =3D { .type =3D BAR_FIXED, .fixed_size =3D SZ_64K, }, .align =3D SZ_4K, }; =20 -static const struct pci_epc_features* +static struct pci_epc_features* imx_pcie_ep_get_features(struct dw_pcie_ep *ep) { struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/contro= ller/dwc/pci-keystone.c index f86d9111f863..4292007a9b3a 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -929,7 +929,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *e= p, u8 func_no, return 0; } =20 -static const struct pci_epc_features ks_pcie_am654_epc_features =3D { +static struct pci_epc_features ks_pcie_am654_epc_features =3D { .msi_capable =3D true, .msix_capable =3D true, .bar[BAR_0] =3D { .type =3D BAR_RESERVED, }, @@ -941,7 +941,7 @@ static const struct pci_epc_features ks_pcie_am654_epc_= features =3D { .align =3D SZ_64K, }; =20 -static const struct pci_epc_features* +static struct pci_epc_features* ks_pcie_am654_get_features(struct dw_pcie_ep *ep) { return &ks_pcie_am654_epc_features; diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/c= ontroller/dwc/pci-layerscape-ep.c index a4a800699f89..8d48413050ef 100644 --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c @@ -138,7 +138,7 @@ static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep = *pcie, return 0; } =20 -static const struct pci_epc_features* +static struct pci_epc_features* ls_pcie_ep_get_features(struct dw_pcie_ep *ep) { struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/contro= ller/dwc/pcie-artpec6.c index f4a136ee2daf..84111d8257f2 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -369,11 +369,11 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *= ep, u8 func_no, return 0; } =20 -static const struct pci_epc_features artpec6_pcie_epc_features =3D { +static struct pci_epc_features artpec6_pcie_epc_features =3D { .msi_capable =3D true, }; =20 -static const struct pci_epc_features * +static struct pci_epc_features * artpec6_pcie_get_features(struct dw_pcie_ep *ep) { return &artpec6_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pc= i/controller/dwc/pcie-designware-plat.c index 12f41886c65d..60ada0eb838e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -60,12 +60,12 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep = *ep, u8 func_no, return 0; } =20 -static const struct pci_epc_features dw_plat_pcie_epc_features =3D { +static struct pci_epc_features dw_plat_pcie_epc_features =3D { .msi_capable =3D true, .msix_capable =3D true, }; =20 -static const struct pci_epc_features* +static struct pci_epc_features* dw_plat_pcie_get_features(struct dw_pcie_ep *ep) { return &dw_plat_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index f87c67a7a482..4dda9a38d46b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -449,7 +449,7 @@ struct dw_pcie_ep_ops { void (*init)(struct dw_pcie_ep *ep); int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num); - const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); + struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep); /* * Provide a method to implement the different func config space * access for different platform, if different func have different diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/co= ntroller/dwc/pcie-dw-rockchip.c index 352f513ebf03..1f3c91368dc3 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -100,7 +100,7 @@ struct rockchip_pcie { =20 struct rockchip_pcie_of_data { enum dw_pcie_device_mode mode; - const struct pci_epc_features *epc_features; + struct pci_epc_features *epc_features; }; =20 static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg) @@ -383,7 +383,7 @@ static int rockchip_pcie_raise_irq(struct dw_pcie_ep *e= p, u8 func_no, return 0; } =20 -static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 =3D= { +static struct pci_epc_features rockchip_pcie_epc_features_rk3568 =3D { .linkup_notifier =3D true, .msi_capable =3D true, .msix_capable =3D true, @@ -403,7 +403,7 @@ static const struct pci_epc_features rockchip_pcie_epc_= features_rk3568 =3D { * default.) If the host could write to BAR4, the iATU settings (for all o= ther * BARs) would be overwritten, resulting in (all other BARs) no longer wor= king. */ -static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 =3D= { +static struct pci_epc_features rockchip_pcie_epc_features_rk3588 =3D { .linkup_notifier =3D true, .msi_capable =3D true, .msix_capable =3D true, @@ -416,7 +416,7 @@ static const struct pci_epc_features rockchip_pcie_epc_= features_rk3588 =3D { .bar[BAR_5] =3D { .type =3D BAR_RESIZABLE, }, }; =20 -static const struct pci_epc_features * +static struct pci_epc_features * rockchip_pcie_get_features(struct dw_pcie_ep *ep) { struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/contro= ller/dwc/pcie-keembay.c index 60e74ac782af..e6de5289329f 100644 --- a/drivers/pci/controller/dwc/pcie-keembay.c +++ b/drivers/pci/controller/dwc/pcie-keembay.c @@ -308,7 +308,7 @@ static int keembay_pcie_ep_raise_irq(struct dw_pcie_ep = *ep, u8 func_no, } } =20 -static const struct pci_epc_features keembay_pcie_epc_features =3D { +static struct pci_epc_features keembay_pcie_epc_features =3D { .msi_capable =3D true, .msix_capable =3D true, .bar[BAR_0] =3D { .only_64bit =3D true, }, @@ -320,7 +320,7 @@ static const struct pci_epc_features keembay_pcie_epc_f= eatures =3D { .align =3D SZ_16K, }; =20 -static const struct pci_epc_features * +static struct pci_epc_features * keembay_pcie_get_features(struct dw_pcie_ep *ep) { return &keembay_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/contro= ller/dwc/pcie-qcom-ep.c index f1bc0ac81a92..6ad033301909 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -819,7 +819,7 @@ static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_= ep *pcie_ep) qcom_pcie_ep_link_transition_count); } =20 -static const struct pci_epc_features qcom_pcie_epc_features =3D { +static struct pci_epc_features qcom_pcie_epc_features =3D { .linkup_notifier =3D true, .msi_capable =3D true, .align =3D SZ_4K, @@ -829,7 +829,7 @@ static const struct pci_epc_features qcom_pcie_epc_feat= ures =3D { .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, }; =20 -static const struct pci_epc_features * +static struct pci_epc_features * qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep) { return &qcom_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/cont= roller/dwc/pcie-rcar-gen4.c index 80778917d2dd..ff0c4af90eff 100644 --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c @@ -419,7 +419,7 @@ static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_e= p *ep, u8 func_no, return 0; } =20 -static const struct pci_epc_features rcar_gen4_pcie_epc_features =3D { +static struct pci_epc_features rcar_gen4_pcie_epc_features =3D { .msi_capable =3D true, .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, @@ -428,7 +428,7 @@ static const struct pci_epc_features rcar_gen4_pcie_epc= _features =3D { .align =3D SZ_1M, }; =20 -static const struct pci_epc_features* +static struct pci_epc_features* rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep) { return &rcar_gen4_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/contr= oller/dwc/pcie-stm32-ep.c index 2cecf32d2b0f..8a892def54f5 100644 --- a/drivers/pci/controller/dwc/pcie-stm32-ep.c +++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c @@ -69,12 +69,12 @@ static int stm32_pcie_raise_irq(struct dw_pcie_ep *ep, = u8 func_no, } } =20 -static const struct pci_epc_features stm32_pcie_epc_features =3D { +static struct pci_epc_features stm32_pcie_epc_features =3D { .msi_capable =3D true, .align =3D SZ_64K, }; =20 -static const struct pci_epc_features* +static struct pci_epc_features* stm32_pcie_get_features(struct dw_pcie_ep *ep) { return &stm32_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/contr= oller/dwc/pcie-tegra194.c index 0ddeef70726d..06f45a17e52c 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1987,7 +1987,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep = *ep, u8 func_no, return 0; } =20 -static const struct pci_epc_features tegra_pcie_epc_features =3D { +static struct pci_epc_features tegra_pcie_epc_features =3D { .linkup_notifier =3D true, .msi_capable =3D true, .bar[BAR_0] =3D { .type =3D BAR_FIXED, .fixed_size =3D SZ_1M, @@ -2000,7 +2000,7 @@ static const struct pci_epc_features tegra_pcie_epc_f= eatures =3D { .align =3D SZ_64K, }; =20 -static const struct pci_epc_features* +static struct pci_epc_features* tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) { return &tegra_pcie_epc_features; diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/co= ntroller/dwc/pcie-uniphier-ep.c index d6e73811216e..ddb5ff70340c 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -82,7 +82,7 @@ struct uniphier_pcie_ep_soc_data { bool has_gio; void (*init)(struct uniphier_pcie_ep_priv *priv); int (*wait)(struct uniphier_pcie_ep_priv *priv); - const struct pci_epc_features features; + struct pci_epc_features *features; }; =20 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) @@ -273,13 +273,13 @@ static int uniphier_pcie_ep_raise_irq(struct dw_pcie_= ep *ep, u8 func_no, return 0; } =20 -static const struct pci_epc_features* +static struct pci_epc_features* uniphier_pcie_get_features(struct dw_pcie_ep *ep) { struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); struct uniphier_pcie_ep_priv *priv =3D to_uniphier_pcie(pci); =20 - return &priv->data->features; + return priv->data->features; } =20 static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops =3D { @@ -415,40 +415,44 @@ static int uniphier_pcie_ep_probe(struct platform_dev= ice *pdev) return 0; } =20 +static struct pci_epc_features uniphier_pro5_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, + .align =3D 1 << 16, + .bar[BAR_0] =3D { .only_64bit =3D true, }, + .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_2] =3D { .only_64bit =3D true, }, + .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_4] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_5] =3D { .type =3D BAR_RESERVED, }, +}; + +static struct pci_epc_features uniphier_nx1_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D false, + .align =3D 1 << 12, + .bar[BAR_0] =3D { .only_64bit =3D true, }, + .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_2] =3D { .only_64bit =3D true, }, + .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, + .bar[BAR_4] =3D { .only_64bit =3D true, }, + .bar[BAR_5] =3D { .type =3D BAR_RESERVED, }, +}; + static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data =3D { .has_gio =3D true, .init =3D uniphier_pcie_pro5_init_ep, .wait =3D NULL, - .features =3D { - .linkup_notifier =3D false, - .msi_capable =3D true, - .msix_capable =3D false, - .align =3D 1 << 16, - .bar[BAR_0] =3D { .only_64bit =3D true, }, - .bar[BAR_1] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_2] =3D { .only_64bit =3D true, }, - .bar[BAR_3] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_4] =3D { .type =3D BAR_RESERVED, }, - .bar[BAR_5] =3D { .type =3D BAR_RESERVED, }, - }, + .features =3D &uniphier_pro5_features, }; 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charset="utf-8" The DesignWare EP core has supported updating the inbound iATU mapping for an already configured BAR (i.e. allowing pci_epc_set_bar() to be called again without a prior pci_epc_clear_bar()) since commit 4284c88fff0e ("PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address"). Now that the EPC layer exposes this capability via the dynamic_inbound_mapping feature bit, set the bit centrally in the DesignWare EP layer so that all DWC-based EP glue drivers report it consistently, without duplicating the same flag in each individual driver. No functional change intended. This only advertises existing behavior to EPF drivers. Suggested-by: Niklas Cassel Signed-off-by: Koichiro Den Reviewed-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 1195d401df19..0e5a8d200b00 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -626,11 +626,19 @@ static const struct pci_epc_features* dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct pci_epc_features *features; =20 if (!ep->ops->get_features) return NULL; =20 - return ep->ops->get_features(ep); + features =3D ep->ops->get_features(ep); + if (!features) + return NULL; + + /* All DWC-based glue drivers support dynamic inbound mapping */ + features->dynamic_inbound_mapping =3D true; + + return features; } =20 static const struct pci_epc_ops epc_ops =3D { --=20 2.51.0 From nobody Mon Feb 9 01:11:51 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11020097.outbound.protection.outlook.com [52.101.229.97]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5E7962F362A; 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charset="utf-8" Extend dw_pcie_ep_set_bar() to support inbound mappings for BAR subranges using Address Match Mode IB iATU. Rename the existing BAR-match helper into dw_pcie_ep_ib_atu_bar() and introduce dw_pcie_ep_ib_atu_addr() for Address Match Mode. When use_submap is set, read the assigned BAR base address and program one inbound iATU window per subrange. Validate the submap array before programming: - each subrange is aligned to pci->region_align - subranges cover the whole BAR (no gaps and no overlaps) - subranges are sorted in ascending order by offset Track Address Match Mode mappings and tear them down on clear_bar() and on set_bar() error paths to avoid leaving half-programmed state or untranslated BAR holes. Advertise this capability by setting subrange_mapping in the EPC features returned from dw_pcie_ep_get_features(). Reviewed-by: Niklas Cassel Signed-off-by: Koichiro Den --- .../pci/controller/dwc/pcie-designware-ep.c | 230 +++++++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 2 + 2 files changed, 222 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 0e5a8d200b00..b2ea2c2c986f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -139,9 +139,10 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc= , u8 func_no, u8 vfunc_no, return 0; } =20 -static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int t= ype, - dma_addr_t parent_bus_addr, enum pci_barno bar, - size_t size) +/* BAR Match Mode inbound iATU mapping */ +static int dw_pcie_ep_ib_atu_bar(struct dw_pcie_ep *ep, u8 func_no, int ty= pe, + dma_addr_t parent_bus_addr, enum pci_barno bar, + size_t size) { int ret; u32 free_win; @@ -174,6 +175,208 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *= ep, u8 func_no, int type, return 0; } =20 +/* Inbound mapping bookkeeping for Address Match Mode */ +struct dw_pcie_ib_map { + struct list_head list; + enum pci_barno bar; + u64 pci_addr; + u64 parent_bus_addr; + u64 size; + u32 index; +}; + +static void dw_pcie_ep_clear_ib_maps(struct dw_pcie_ep *ep, enum pci_barno= bar) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + struct dw_pcie_ib_map *m, *tmp; + struct device *dev =3D pci->dev; + u32 atu_index; + + /* Tear down the BAR Match Mode mapping, if any. */ + if (ep->bar_to_atu[bar]) { + atu_index =3D ep->bar_to_atu[bar] - 1; + dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index); + clear_bit(atu_index, ep->ib_window_map); + ep->bar_to_atu[bar] =3D 0; + } + + /* Tear down all Address Match Mode mappings, if any. */ + guard(spinlock_irqsave)(&ep->ib_map_lock); + list_for_each_entry_safe(m, tmp, &ep->ib_map_list, list) { + if (m->bar !=3D bar) + continue; + dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, m->index); + clear_bit(m->index, ep->ib_window_map); + list_del(&m->list); + devm_kfree(dev, m); + } +} + +static u64 dw_pcie_ep_read_bar_assigned(struct dw_pcie_ep *ep, u8 func_no, + enum pci_barno bar, int flags) +{ + u32 reg =3D PCI_BASE_ADDRESS_0 + (4 * bar); + u32 lo, hi; + u64 addr; + + lo =3D dw_pcie_ep_readl_dbi(ep, func_no, reg); + + if (flags & PCI_BASE_ADDRESS_SPACE) + return lo & PCI_BASE_ADDRESS_IO_MASK; + + addr =3D lo & PCI_BASE_ADDRESS_MEM_MASK; + if (!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) + return addr; + + hi =3D dw_pcie_ep_readl_dbi(ep, func_no, reg + 4); + return addr | ((u64)hi << 32); +} + +static int dw_pcie_ep_validate_submap(struct dw_pcie_ep *ep, + const struct pci_epf_bar_submap *submap, + unsigned int num_submap, size_t bar_size) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + u32 align =3D pci->region_align; + size_t expected =3D 0; + size_t size, off; + unsigned int i; + + if (!align || !IS_ALIGNED(bar_size, align)) + return -EINVAL; + + /* + * The array is expected to be sorted by offset before calling this + * helper. With sorted entries, we can enforce a strict, gapless + * decomposition of the BAR: + * - each entry has a non-zero size + * - offset/size/phys_addr are aligned to pci->region_align + * - each entry lies within the BAR range + * - entries are contiguous (no overlaps, no holes) + * - the entries exactly cover the whole BAR + * + * Note: dw_pcie_prog_inbound_atu() also checks alignment for + * offset/phys_addr, but validating up-front avoids partially + * programming iATU windows in vain. + */ + for (i =3D 0; i < num_submap; i++) { + off =3D submap[i].offset; + size =3D submap[i].size; + + if (!size) + return -EINVAL; + + if (!IS_ALIGNED(size, align) || !IS_ALIGNED(off, align)) + return -EINVAL; + + if (!IS_ALIGNED(submap[i].phys_addr, align)) + return -EINVAL; + + if (off > bar_size || size > bar_size - off) + return -EINVAL; + + /* Enforce contiguity (no overlaps, no holes). */ + if (off !=3D expected) + return -EINVAL; + + expected +=3D size; + } + if (expected !=3D bar_size) + return -EINVAL; + + return 0; +} + +/* Address Match Mode inbound iATU mapping */ +static int dw_pcie_ep_ib_atu_addr(struct dw_pcie_ep *ep, u8 func_no, int t= ype, + const struct pci_epf_bar *epf_bar) +{ + const struct pci_epf_bar_submap *submap =3D epf_bar->submap; + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + enum pci_barno bar =3D epf_bar->barno; + struct device *dev =3D pci->dev; + u64 pci_addr, parent_bus_addr; + struct dw_pcie_ib_map *new; + u64 size, off, base; + unsigned long flags; + int free_win, ret; + unsigned int i; + + if (!epf_bar->num_submap || !submap || !epf_bar->size) + return -EINVAL; + + ret =3D dw_pcie_ep_validate_submap(ep, submap, epf_bar->num_submap, + epf_bar->size); + if (ret) + return ret; + + base =3D dw_pcie_ep_read_bar_assigned(ep, func_no, bar, epf_bar->flags); + if (!base) { + dev_err(dev, + "BAR%u not assigned, cannot set up sub-range mappings\n", + bar); + return -EINVAL; + } + + /* Tear down any existing mappings before (re)programming. */ + dw_pcie_ep_clear_ib_maps(ep, bar); + + for (i =3D 0; i < epf_bar->num_submap; i++) { + off =3D submap[i].offset; + size =3D submap[i].size; + parent_bus_addr =3D submap[i].phys_addr; + + if (off > (~0ULL) - base) { + ret =3D -EINVAL; + goto err; + } + + pci_addr =3D base + off; + + new =3D devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); + if (!new) { + ret =3D -ENOMEM; + goto err; + } + + spin_lock_irqsave(&ep->ib_map_lock, flags); + + free_win =3D find_first_zero_bit(ep->ib_window_map, + pci->num_ib_windows); + if (free_win >=3D pci->num_ib_windows) { + spin_unlock_irqrestore(&ep->ib_map_lock, flags); + devm_kfree(dev, new); + ret =3D -ENOSPC; + goto err; + } + set_bit(free_win, ep->ib_window_map); + + new->bar =3D bar; + new->index =3D free_win; + new->pci_addr =3D pci_addr; + new->parent_bus_addr =3D parent_bus_addr; + new->size =3D size; + list_add_tail(&new->list, &ep->ib_map_list); + + spin_unlock_irqrestore(&ep->ib_map_lock, flags); + + ret =3D dw_pcie_prog_inbound_atu(pci, free_win, type, + parent_bus_addr, pci_addr, size); + if (ret) { + spin_lock_irqsave(&ep->ib_map_lock, flags); + list_del(&new->list); + clear_bit(free_win, ep->ib_window_map); + spin_unlock_irqrestore(&ep->ib_map_lock, flags); + devm_kfree(dev, new); + goto err; + } + } + return 0; +err: + dw_pcie_ep_clear_ib_maps(ep, bar); + return ret; +} + static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, struct dw_pcie_ob_atu_cfg *atu) { @@ -204,17 +407,15 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc,= u8 func_no, u8 vfunc_no, struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); enum pci_barno bar =3D epf_bar->barno; - u32 atu_index =3D ep->bar_to_atu[bar] - 1; =20 - if (!ep->bar_to_atu[bar]) + if (!ep->epf_bar[bar]) return; =20 __dw_pcie_ep_reset_bar(pci, func_no, bar, epf_bar->flags); =20 - dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, atu_index); - clear_bit(atu_index, ep->ib_window_map); + dw_pcie_ep_clear_ib_maps(ep, bar); + ep->epf_bar[bar] =3D NULL; - ep->bar_to_atu[bar] =3D 0; } =20 static unsigned int dw_pcie_ep_get_rebar_offset(struct dw_pcie *pci, @@ -408,8 +609,12 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 = func_no, u8 vfunc_no, else type =3D PCIE_ATU_TYPE_IO; =20 - ret =3D dw_pcie_ep_inbound_atu(ep, func_no, type, epf_bar->phys_addr, bar, - size); + if (epf_bar->use_submap) + ret =3D dw_pcie_ep_ib_atu_addr(ep, func_no, type, epf_bar); + else + ret =3D dw_pcie_ep_ib_atu_bar(ep, func_no, type, + epf_bar->phys_addr, bar, size); + if (ret) return ret; =20 @@ -638,6 +843,9 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no= , u8 vfunc_no) /* All DWC-based glue drivers support dynamic inbound mapping */ features->dynamic_inbound_mapping =3D true; =20 + /* All DWC-based glue drivers support inbound subrange mapping */ + features->subrange_mapping =3D true; + return features; } =20 @@ -1128,6 +1336,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct device *dev =3D pci->dev; =20 INIT_LIST_HEAD(&ep->func_list); + INIT_LIST_HEAD(&ep->ib_map_list); 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Received: from TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) by TYWP286MB2282.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:13d::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9499.7; Tue, 13 Jan 2026 16:27:29 +0000 Received: from TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM ([fe80::2305:327c:28ec:9b32]) by TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM ([fe80::2305:327c:28ec:9b32%5]) with mapi id 15.20.9499.005; Tue, 13 Jan 2026 16:27:29 +0000 From: Koichiro Den To: jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org, bhelgaas@google.com, cassel@kernel.org Cc: vigneshr@ti.com, s-vadapalli@ti.com, hongxing.zhu@nxp.com, l.stach@pengutronix.de, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, jesper.nilsson@axis.com, heiko@sntech.de, srikanth.thokala@intel.com, marek.vasut+renesas@gmail.com, yoshihiro.shimoda.uh@renesas.com, geert+renesas@glider.be, magnus.damm@gmail.com, christian.bruel@foss.st.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, thierry.reding@gmail.com, jonathanh@nvidia.com, hayashi.kunihiko@socionext.com, mhiramat@kernel.org, kishon@kernel.org, jirislaby@kernel.org, rongqianfeng@vivo.com, 18255117159@163.com, shawn.lin@rock-chips.com, nicolas.frattaroli@collabora.com, linux.amoon@gmail.com, vidyas@nvidia.com, Frank.Li@nxp.com, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@axis.com, linux-rockchip@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-tegra@vger.kernel.org Subject: [PATCH v7 6/6] Documentation: PCI: endpoint: Clarify pci_epc_set_bar() usage Date: Wed, 14 Jan 2026 01:27:19 +0900 Message-ID: <20260113162719.3710268-7-den@valinux.co.jp> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260113162719.3710268-1-den@valinux.co.jp> References: <20260113162719.3710268-1-den@valinux.co.jp> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: TYCPR01CA0038.jpnprd01.prod.outlook.com (2603:1096:405:1::26) To TY7P286MB7722.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:38f::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY7P286MB7722:EE_|TYWP286MB2282:EE_ X-MS-Office365-Filtering-Correlation-Id: 161d4cf4-b79d-4b65-ff8b-08de52c0a572 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|376014|7416014|366016|1800799024; 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charset="utf-8" The current documentation implies that pci_epc_set_bar() is only used before the host enumerates the endpoint. In practice, some Endpoint Controllers support calling pci_epc_set_bar() multiple times for the same BAR (without clearing it) in order to update inbound address translations after the host has programmed the BAR base address, which some Endpoint Functions such as vNTB already relies on. Add document text for that. Also document the expected call flow for BAR subrange mapping (pci_epf_bar.use_submap / pci_epf_bar.submap), which may require a second pci_epc_set_bar() call after the host has programmed the BAR base address. Reviewed-by: Niklas Cassel Signed-off-by: Koichiro Den Reviewed-by: Frank Li --- Documentation/PCI/endpoint/pci-endpoint.rst | 24 +++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/PCI/endpoint/pci-endpoint.rst b/Documentation/PC= I/endpoint/pci-endpoint.rst index 0741c8cbd74e..09b892de9280 100644 --- a/Documentation/PCI/endpoint/pci-endpoint.rst +++ b/Documentation/PCI/endpoint/pci-endpoint.rst @@ -95,6 +95,30 @@ by the PCI endpoint function driver. Register space of the function driver is usually configured using this API. =20 + Some endpoint controllers also support calling pci_epc_set_bar() again + for the same BAR (without calling pci_epc_clear_bar()) to update inbound + address translations after the host has programmed the BAR base address. + Endpoint function drivers can check this capability via the + dynamic_inbound_mapping EPC feature bit. + + When pci_epf_bar.use_submap is set, the endpoint function driver is + requesting BAR subrange mapping using pci_epf_bar.submap. This requires + the EPC to advertise support via the subrange_mapping EPC feature bit. + + When an EPF driver wants to make use of the inbound subrange mapping + feature, it requires that the BAR base address has been programmed by + the host during enumeration. Thus, it needs to call pci_epc_set_bar() + twice for the same BAR (requires dynamic_inbound_mapping): first with + use_submap cleared to configure the BAR size, then after the PCIe link + is up and the host enumerates the endpoint and programs the BAR base + address, again with use_submap set. + + Note that when making use of the inbound subrange mapping feature, the + EPF driver must not call pci_epc_clear_bar() between the two + pci_epc_set_bar() calls, because clearing the BAR can clear/disable the + BAR register or BAR decode on the endpoint while the host still expects + the assigned BAR address to remain valid. + * pci_epc_clear_bar() =20 The PCI endpoint function driver should use pci_epc_clear_bar() to reset --=20 2.51.0