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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:10.4270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffe773a8-723d-45b3-f471-08de52ae70eb X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB5893 Content-Type: text/plain; charset="utf-8" Add DQS (Data Strobe) parameter to cqspi_readdata_capture() to control data capture timing. DQS mode uses a dedicated strobe signal for improved timing margins in high-speed SPI modes. Signed-off-by: Santhosh Kumar K Reviewed-by: Miquel Raynal --- drivers/spi/spi-cadence-quadspi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 303064fdfe2c..1d708dde4463 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -186,6 +186,7 @@ struct cqspi_driver_platdata { #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF +#define CQSPI_REG_READCAPTURE_DQS_LSB 8 =20 #define CQSPI_REG_SIZE 0x14 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 @@ -451,7 +452,7 @@ static int cqspi_wait_idle(struct cqspi_st *cqspi) } =20 static void cqspi_readdata_capture(struct cqspi_st *cqspi, const bool bypa= ss, - const unsigned int delay) + const bool dqs, const unsigned int delay) { void __iomem *reg_base =3D cqspi->iobase; unsigned int reg; @@ -469,6 +470,11 @@ static void cqspi_readdata_capture(struct cqspi_st *cq= spi, const bool bypass, reg |=3D (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) << CQSPI_REG_READCAPTURE_DELAY_LSB; =20 + if (dqs) + reg |=3D BIT(CQSPI_REG_READCAPTURE_DQS_LSB); + else + reg &=3D ~BIT(CQSPI_REG_READCAPTURE_DQS_LSB); + writel(reg, reg_base + CQSPI_REG_READCAPTURE); } =20 @@ -1310,7 +1316,7 @@ static void cqspi_configure(struct cqspi_flash_pdata = *f_pdata, cqspi->sclk =3D sclk; cqspi_config_baudrate_div(cqspi); cqspi_delay(f_pdata); - cqspi_readdata_capture(cqspi, !cqspi->rclk_en, + cqspi_readdata_capture(cqspi, !cqspi->rclk_en, false, f_pdata->read_delay); } =20 --=20 2.34.1