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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:16:58.3359 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cdd4ae85-4c3e-4cd9-e923-08de52ae69b2 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR10MB4443 Content-Type: text/plain; charset="utf-8" Add the optional 'spi-has-dqs' boolean property for SPI flash device subnodes. This property indicates the flash device supports DQS (Data Strobe) mode, which provides improved timing margins for data capture in high-speed SPI operations. Signed-off-by: Santhosh Kumar K --- .../devicetree/bindings/spi/spi-peripheral-props.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yam= l b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index 8b6e8fc009db..c6f330fd32aa 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -89,6 +89,12 @@ properties: description: Delay, in microseconds, after a write transfer. =20 + spi-has-dqs: + description: + Indicates the SPI flash device supports DQS (Data Strobe) mode for + improved data capture timing. + $ref: /schemas/types.yaml#/definitions/flag + stacked-memories: description: Several SPI memories can be wired in stacked mode. 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:04.7168 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 903920bd-4942-4b1c-b48d-08de52ae6d84 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022573.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR10MB7554 Content-Type: text/plain; charset="utf-8" High-speed SPI memory controllers often require timing calibration to operate reliably at maximum frequencies. Parameters such as sampling points and delays need to be tuned based on the specific hardware configuration and operating conditions. Add spi_mem_execute_tuning() to allow SPI memory drivers to request controller-specific tuning. The function takes a mandatory read operation template and an optional write template, as most tuning procedures are based on read operations and calls the corresponding execute_tuning callback to spi_controller_mem_ops to allow controller drivers to implement their tuning procedures. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-mem.c | 34 ++++++++++++++++++++++++++++++++++ include/linux/spi/spi-mem.h | 5 +++++ 2 files changed, 39 insertions(+) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index c8b2add2640e..2d34469323ea 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -633,6 +633,40 @@ u64 spi_mem_calc_op_duration(struct spi_mem *mem, stru= ct spi_mem_op *op) } EXPORT_SYMBOL_GPL(spi_mem_calc_op_duration); =20 +/** + * spi_mem_execute_tuning() - Execute controller tuning procedure + * @mem: the SPI memory device + * @read_op: read operation template (mandatory) + * @write_op: write operation template (optional, may be NULL) + * + * Requests the controller to perform tuning to optimize timing parameters + * for high-speed operation. Controllers use the provided operation templa= tes + * to construct their tuning sequences. + * + * Return: 0 on success, -EINVAL if @mem or @read_op is NULL, + * -EOPNOTSUPP if controller doesn't support tuning, + * or a controller-specific error code on failure. + */ +int spi_mem_execute_tuning(struct spi_mem *mem, struct spi_mem_op *read_op, + struct spi_mem_op *write_op) +{ + struct spi_controller *ctlr; + + if (!mem || !read_op) + return -EINVAL; + + ctlr =3D mem->spi->controller; + if (!ctlr->mem_ops || !ctlr->mem_ops->execute_tuning) + return -EOPNOTSUPP; + + spi_mem_adjust_op_freq(mem, read_op); + if (write_op) + spi_mem_adjust_op_freq(mem, write_op); + + return ctlr->mem_ops->execute_tuning(mem, read_op, write_op); +} +EXPORT_SYMBOL_GPL(spi_mem_execute_tuning); + static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs, size_t len, void *buf) { diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 82390712794c..871e46297517 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -344,6 +344,8 @@ struct spi_controller_mem_ops { unsigned long initial_delay_us, unsigned long polling_rate_us, unsigned long timeout_ms); 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:16:52.1180 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1f5df55-46d9-4a9a-79ee-08de52ae6602 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV0PR10MB997612 Content-Type: text/plain; charset="utf-8" SPI controllers may need tuning for reliable high-speed operation. Without it, controllers use conservative timing that limits performance. Call spi_mem_execute_tuning() during probe to optimize timing for the device's read and write operations. Failures are non-fatal as controllers fall back to default timing. Signed-off-by: Santhosh Kumar K --- drivers/mtd/nand/spi/core.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 0346916b032b..2a45d1047736 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1658,6 +1658,7 @@ static int spinand_probe(struct spi_mem *mem) { struct spinand_device *spinand; struct mtd_info *mtd; + struct spi_mem_op read_op, write_op; int ret; =20 spinand =3D devm_kzalloc(&mem->spi->dev, sizeof(*spinand), @@ -1676,6 +1677,19 @@ static int spinand_probe(struct spi_mem *mem) if (ret) return ret; =20 + read_op =3D *spinand->op_templates.read_cache; + write_op =3D *spinand->op_templates.write_cache; + + ret =3D spi_mem_execute_tuning(mem, &read_op, &write_op); + if (ret && ret !=3D -EOPNOTSUPP) { + dev_warn(&mem->spi->dev, "Failed to execute PHY tuning: %d\n", + ret); + /* + * Tuning failure is non-fatal; the controller falls back to + * default timing, reducing speed but ensuring operation. + */ + } + ret =3D mtd_device_register(mtd, NULL, 0); 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:16:52.8383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cae61bc1-2579-4300-2ba4-08de52ae6670 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A103.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB5682 Content-Type: text/plain; charset="utf-8" From: Pratyush Yadav spi_nor_spimem_read_data() and spi_nor_create_read_dirmap() duplicate the logic for constructing read operations: both create a spi_mem_op, call spi_nor_spimem_setup_op(), and convert dummy cycles to bytes. Extract this into spi_nor_spimem_get_read_op() to eliminate duplication. The helper returns a configured template that callers populate with address, data length, and buffer. Signed-off-by: Pratyush Yadav Signed-off-by: Santhosh Kumar K --- drivers/mtd/spi-nor/core.c | 60 +++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index d3f8a78efd3b..63f3051d7a6b 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -188,6 +188,31 @@ static int spi_nor_controller_ops_erase(struct spi_nor= *nor, loff_t offs) return nor->controller_ops->erase(nor, offs); } =20 +/** + * spi_nor_spimem_get_read_op() - get spi_mem read operation template + * @nor: the spi-nor device + * + * Returns a read operation template with buswidths and dummy cycles + * configured. Caller must set address, data length, and data buffer. + */ +static struct spi_mem_op spi_nor_spimem_get_read_op(struct spi_nor *nor) +{ + struct spi_mem_op op =3D + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), + SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), + SPI_MEM_OP_DUMMY(nor->read_dummy, 0), + SPI_MEM_OP_DATA_IN(1, NULL, 0)); + + spi_nor_spimem_setup_op(nor, &op, nor->read_proto); + + /* convert the dummy cycles to the number of bytes */ + op.dummy.nbytes =3D (nor->read_dummy * op.dummy.buswidth) / 8; + if (spi_nor_protocol_is_dtr(nor->read_proto)) + op.dummy.nbytes *=3D 2; + + return op; +} + /** * spi_nor_spimem_read_data() - read data from flash's memory region via * spi-mem @@ -201,21 +226,14 @@ static int spi_nor_controller_ops_erase(struct spi_no= r *nor, loff_t offs) static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from, size_t len, u8 *buf) { - struct spi_mem_op op =3D - SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), - SPI_MEM_OP_ADDR(nor->addr_nbytes, from, 0), - SPI_MEM_OP_DUMMY(nor->read_dummy, 0), - SPI_MEM_OP_DATA_IN(len, buf, 0)); + struct spi_mem_op op =3D spi_nor_spimem_get_read_op(nor); bool usebouncebuf; ssize_t nbytes; int error; =20 - spi_nor_spimem_setup_op(nor, &op, nor->read_proto); - - /* convert the dummy cycles to the number of bytes */ - op.dummy.nbytes =3D (nor->read_dummy * op.dummy.buswidth) / 8; - if (spi_nor_protocol_is_dtr(nor->read_proto)) - op.dummy.nbytes *=3D 2; + op.addr.val =3D from; + op.data.nbytes =3D len; + op.data.buf.in =3D buf; =20 usebouncebuf =3D spi_nor_spimem_bounce(nor, &op); =20 @@ -3641,28 +3659,10 @@ EXPORT_SYMBOL_GPL(spi_nor_scan); static int spi_nor_create_read_dirmap(struct spi_nor *nor) { struct spi_mem_dirmap_info info =3D { - .op_tmpl =3D SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), - SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0), - SPI_MEM_OP_DUMMY(nor->read_dummy, 0), - SPI_MEM_OP_DATA_IN(0, NULL, 0)), + .op_tmpl =3D spi_nor_spimem_get_read_op(nor), .offset =3D 0, .length =3D nor->params->size, }; - struct spi_mem_op *op =3D &info.op_tmpl; - - spi_nor_spimem_setup_op(nor, op, nor->read_proto); - - /* convert the dummy cycles to the number of bytes */ - op->dummy.nbytes =3D (nor->read_dummy * op->dummy.buswidth) / 8; - if (spi_nor_protocol_is_dtr(nor->read_proto)) - op->dummy.nbytes *=3D 2; - - /* - * Since spi_nor_spimem_setup_op() only sets buswidth when the number - * of data bytes is non-zero, the data buswidth won't be set here. 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:17.0137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 047575b6-92a1-4418-795f-08de52ae74d9 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022573.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR10MB4321 Content-Type: text/plain; charset="utf-8" SPI controllers may need tuning for reliable high-speed operation. Without it, controllers use conservative timing that limits performance. Call spi_mem_execute_tuning() during probe to optimize timing for the device's read operation. Failures are non-fatal as controllers fall back to default timing. Signed-off-by: Santhosh Kumar K --- drivers/mtd/spi-nor/core.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 63f3051d7a6b..d69cb8eaad83 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3704,6 +3704,7 @@ static int spi_nor_probe(struct spi_mem *spimem) struct device *dev =3D &spi->dev; struct flash_platform_data *data =3D dev_get_platdata(dev); struct spi_nor *nor; + struct spi_mem_op read_op; /* * Enable all caps by default. The core will mask them after * checking what's really supported using spi_mem_supports_op(). @@ -3773,6 +3774,16 @@ static int spi_nor_probe(struct spi_mem *spimem) if (ret) return ret; =20 + read_op =3D spi_nor_spimem_get_read_op(nor); + ret =3D spi_mem_execute_tuning(spimem, &read_op, NULL); + if (ret && ret !=3D -EOPNOTSUPP) { + dev_warn(dev, "Failed to execute PHY tuning: %d\n", ret); + /* + * Tuning failure is non-fatal; the controller falls back to + * default timing, reducing speed but ensuring operation. + */ + } + return mtd_device_register(&nor->mtd, data ? data->parts : NULL, data ? data->nr_parts : 0); } --=20 2.34.1 From nobody Sun Feb 8 11:40:22 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010067.outbound.protection.outlook.com [52.101.56.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43D141DEFE9; Tue, 13 Jan 2026 14:17:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:02.5010 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 05556bbc-4311-4832-8980-08de52ae6c2c X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCBF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH3PPFE7CE61147 Content-Type: text/plain; charset="utf-8" Move cqspi_readdata_capture() function earlier in the file. This is preparatory refactoring for upcoming PHY tuning support for read and write operations. No functional changes. Signed-off-by: Santhosh Kumar K Reviewed-by: Miquel Raynal --- drivers/spi/spi-cadence-quadspi.c | 45 +++++++++++++++---------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index b1cf182d6566..303064fdfe2c 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -450,6 +450,28 @@ static int cqspi_wait_idle(struct cqspi_st *cqspi) } } =20 +static void cqspi_readdata_capture(struct cqspi_st *cqspi, const bool bypa= ss, + const unsigned int delay) +{ + void __iomem *reg_base =3D cqspi->iobase; + unsigned int reg; + + reg =3D readl(reg_base + CQSPI_REG_READCAPTURE); + + if (bypass) + reg |=3D BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); + else + reg &=3D ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); + + reg &=3D ~(CQSPI_REG_READCAPTURE_DELAY_MASK + << CQSPI_REG_READCAPTURE_DELAY_LSB); + + reg |=3D (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) + << CQSPI_REG_READCAPTURE_DELAY_LSB; + + writel(reg, reg_base + CQSPI_REG_READCAPTURE); +} + static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) { void __iomem *reg_base =3D cqspi->iobase; @@ -1267,29 +1289,6 @@ static void cqspi_config_baudrate_div(struct cqspi_s= t *cqspi) writel(reg, reg_base + CQSPI_REG_CONFIG); } =20 -static void cqspi_readdata_capture(struct cqspi_st *cqspi, - const bool bypass, - const unsigned int delay) -{ - void __iomem *reg_base =3D cqspi->iobase; - unsigned int reg; - - reg =3D readl(reg_base + CQSPI_REG_READCAPTURE); - - if (bypass) - reg |=3D BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); - else - reg &=3D ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB); - - reg &=3D ~(CQSPI_REG_READCAPTURE_DELAY_MASK - << CQSPI_REG_READCAPTURE_DELAY_LSB); - - reg |=3D (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) - << CQSPI_REG_READCAPTURE_DELAY_LSB; - - writel(reg, reg_base + CQSPI_REG_READCAPTURE); -} - static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, unsigned long sclk) { --=20 2.34.1 From nobody Sun Feb 8 11:40:22 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012057.outbound.protection.outlook.com [52.101.48.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3333A285CA9; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:10.4270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffe773a8-723d-45b3-f471-08de52ae70eb X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.195];Helo=[lewvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB5893 Content-Type: text/plain; charset="utf-8" Add DQS (Data Strobe) parameter to cqspi_readdata_capture() to control data capture timing. DQS mode uses a dedicated strobe signal for improved timing margins in high-speed SPI modes. Signed-off-by: Santhosh Kumar K Reviewed-by: Miquel Raynal --- drivers/spi/spi-cadence-quadspi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 303064fdfe2c..1d708dde4463 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -186,6 +186,7 @@ struct cqspi_driver_platdata { #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF +#define CQSPI_REG_READCAPTURE_DQS_LSB 8 =20 #define CQSPI_REG_SIZE 0x14 #define CQSPI_REG_SIZE_ADDRESS_LSB 0 @@ -451,7 +452,7 @@ static int cqspi_wait_idle(struct cqspi_st *cqspi) } =20 static void cqspi_readdata_capture(struct cqspi_st *cqspi, const bool bypa= ss, - const unsigned int delay) + const bool dqs, const unsigned int delay) { void __iomem *reg_base =3D cqspi->iobase; unsigned int reg; @@ -469,6 +470,11 @@ static void cqspi_readdata_capture(struct cqspi_st *cq= spi, const bool bypass, reg |=3D (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) << CQSPI_REG_READCAPTURE_DELAY_LSB; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:44.3916 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7dbb856a-7abc-4a7d-67b8-08de52ae8527 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR10MB8156 Content-Type: text/plain; charset="utf-8" Add a boolean field to struct cqspi_flash_pdata to store whether the attached flash device supports DQS (Data Strobe) mode. Read this from the 'spi-has-dqs' device tree property during flash node parsing. This is preparatory infrastructure for PHY tuning support. The field will be used by subsequent patches to configure read data capture timing with DQS enabled for improved margins in high-speed operations. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 1d708dde4463..0df286d24256 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -70,6 +70,7 @@ struct cqspi_flash_pdata { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; + bool has_dqs; u8 cs; }; =20 @@ -1583,6 +1584,8 @@ static int cqspi_of_get_flash_pdata(struct platform_d= evice *pdev, return -ENXIO; } =20 + f_pdata->has_dqs =3D of_property_read_bool(np, "spi-has-dqs"); + return 0; } =20 --=20 2.34.1 From nobody Sun Feb 8 11:40:22 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010048.outbound.protection.outlook.com [52.101.85.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0893027B353; Tue, 13 Jan 2026 14:17:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:38.0562 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d69ccaa-d774-47b0-f4ca-08de52ae8163 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB4815 Content-Type: text/plain; charset="utf-8" Implement the spi_controller_mem_ops execute_tuning callback to enable PHY tuning support for the Cadence controller. PHY tuning optimizes data capture timing at high frequencies by calibrating the read data capture delay through the controller's PHY interface. Tuning algorithm functions (cqspi_phy_tuning_ddr/sdr and cqspi_phy_pre/post_config) are placeholders to be implemented in subsequent commits. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 241 ++++++++++++++++++++++++++++++ 1 file changed, 241 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 0df286d24256..b8b0e85f4f68 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -32,6 +32,7 @@ =20 #define CQSPI_NAME "cadence-qspi" #define CQSPI_MAX_CHIPSELECT 4 +#define CQSPI_AM654_NON_PHY_CLK_RATE 25000000 =20 static_assert(CQSPI_MAX_CHIPSELECT <=3D SPI_DEVICE_CS_CNT_MAX); =20 @@ -65,6 +66,7 @@ struct cqspi_st; struct cqspi_flash_pdata { struct cqspi_st *cqspi; u32 clk_rate; + u32 non_phy_clk_rate; u32 read_delay; u32 tshsl_ns; u32 tsd2d_ns; @@ -72,6 +74,8 @@ struct cqspi_flash_pdata { u32 tslch_ns; bool has_dqs; u8 cs; + struct spi_mem_op phy_read_op; + struct spi_mem_op phy_write_op; }; =20 struct cqspi_st { @@ -124,6 +128,9 @@ struct cqspi_driver_platdata { u32 (*get_dma_status)(struct cqspi_st *cqspi); int (*jh7110_clk_init)(struct platform_device *pdev, struct cqspi_st *cqspi); + int (*execute_tuning)(struct spi_mem *mem, struct spi_mem_op *read_op, + struct spi_mem_op *write_op); + u32 (*get_non_phy_clk_rate)(struct cqspi_st *cqspi); }; =20 /* Operation timeout value */ @@ -314,6 +321,25 @@ struct cqspi_driver_platdata { =20 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 =20 +/* + * PHY tuning pattern for calibrating read data capture delay. This 128-by= te + * pattern provides sufficient bit transitions across all byte lanes to + * reliably detect timing windows at high frequencies. + */ +static const u8 phy_tuning_pattern[] __aligned(64) =3D { + 0xFE, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0xFE, 0xFE, 0x01, + 0x01, 0x01, 0x01, 0x00, 0x00, 0xFE, 0xFE, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x00, 0x00, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFE, + 0xFE, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFE, 0x00, 0xFE, 0xFE, 0x01, + 0x01, 0x01, 0x01, 0xFE, 0x00, 0xFE, 0xFE, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFE, 0x00, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0xFE, + 0xFE, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0xFE, 0xFE, 0xFE, 0x01, + 0x01, 0x01, 0x01, 0x00, 0xFE, 0xFE, 0xFE, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x00, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xFE, 0xFE, + 0xFE, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01, + 0x01, 0x01, 0x01, 0xFE, 0xFE, 0xFE, 0xFE, 0x01, +}; + static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata, void __iomem *reg, const u32 mask, bool clr, bool busywait) @@ -1550,6 +1576,214 @@ static bool cqspi_supports_mem_op(struct spi_mem *m= em, return spi_mem_default_supports_op(mem, op); } =20 +static int cqspi_write_pattern_to_cache(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, + struct spi_mem_op *write_op) +{ + struct device *dev =3D &f_pdata->cqspi->pdev->dev; + int ret; + + write_op->data.nbytes =3D sizeof(phy_tuning_pattern); + write_op->data.buf.out =3D phy_tuning_pattern; + + ret =3D spi_mem_exec_op(mem, write_op); + if (ret) { + dev_err(dev, "Failed to write PHY pattern to cache: %d\n", ret); + return ret; + } + dev_dbg(dev, "PHY pattern (%zu bytes) written to cache\n", + sizeof(phy_tuning_pattern)); + + return 0; +} + +static int cqspi_get_phy_pattern_offset(struct device *dev, u32 *offset) +{ + struct device_node *np, *flash_np =3D NULL; + struct device_node *partition_np, *part_np; + const char *label; + const __be32 *reg; + int len; + + if (!dev || !dev->of_node) + return -EINVAL; + + for_each_child_of_node(dev->of_node, np) { + if (of_node_name_prefix(np, "flash")) { + flash_np =3D np; + break; + } + } + + if (!flash_np) + return -ENODEV; + + partition_np =3D of_get_child_by_name(flash_np, "partitions"); + if (!partition_np) { + of_node_put(flash_np); + return -ENODEV; + } + + for_each_child_of_node(partition_np, part_np) { + if (of_property_read_string(part_np, "label", &label) || + !strstr(label, "phypattern")) + continue; + + reg =3D of_get_property(part_np, "reg", &len); + if (reg && len >=3D sizeof(__be32)) { + *offset =3D be32_to_cpu(reg[0]); + of_node_put(part_np); + of_node_put(partition_np); + of_node_put(flash_np); + return 0; + } + } + + of_node_put(partition_np); + of_node_put(flash_np); + return -ENOENT; +} + +static int cqspi_phy_check_pattern(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem) +{ + struct spi_mem_op op; + u8 *read_data; + int ret; + + read_data =3D kmalloc_array(1, sizeof(phy_tuning_pattern), GFP_KERNEL); + if (!read_data) + return -ENOMEM; + + op =3D f_pdata->phy_read_op; + op.data.buf.in =3D read_data; + op.data.nbytes =3D sizeof(phy_tuning_pattern); + + ret =3D spi_mem_exec_op(mem, &op); + if (ret) + goto out; + + if (memcmp(read_data, phy_tuning_pattern, sizeof(phy_tuning_pattern))) + ret =3D -EAGAIN; + +out: + kfree(read_data); + return ret; +} + +static void cqspi_phy_pre_config(struct cqspi_st *cqspi, + struct cqspi_flash_pdata *f_pdata, + const bool bypass) +{ + /* Placeholder for PHY pre-configuration */ +} + +static void cqspi_phy_post_config(struct cqspi_st *cqspi, + const unsigned int delay) +{ + /* Placeholder for PHY post-configuration */ +} + +static int cqspi_phy_tuning_ddr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem) +{ + /* Placeholder for DDR mode PHY tuning algorithm */ + return 0; +} + +static int cqspi_phy_tuning_sdr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem) +{ + /* Placeholder for SDR mode PHY tuning algorithm */ + return 0; +} + +static int cqspi_am654_ospi_execute_tuning(struct spi_mem *mem, + struct spi_mem_op *read_op, + struct spi_mem_op *write_op) +{ + struct cqspi_st *cqspi =3D + spi_controller_get_devdata(mem->spi->controller); + struct cqspi_flash_pdata *f_pdata; + struct device *dev =3D &cqspi->pdev->dev; + int ret; + u32 phy_offset; + + f_pdata =3D &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; + + if (read_op->max_freq <=3D f_pdata->non_phy_clk_rate) { + dev_dbg(dev, + "Frequency %u Hz below PHY threshold %u Hz, skipping tuning\n", + read_op->max_freq, f_pdata->non_phy_clk_rate); + return 0; + } + + if (write_op) { + ret =3D cqspi_write_pattern_to_cache(f_pdata, mem, write_op); + if (ret) { + dev_warn(dev, + "failed to write pattern to cache: %d, skipping PHY tuning\n", + ret); + return ret; + } + + f_pdata->phy_write_op =3D *write_op; + } else { + ret =3D cqspi_get_phy_pattern_offset(dev, &phy_offset); + if (ret) { + dev_warn(dev, + "PHY pattern partition not found: %d, skipping PHY tuning\n", + ret); + return ret; + } + + read_op->addr.val =3D phy_offset; + } + + f_pdata->phy_read_op =3D *read_op; + + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + if (ret) { + dev_err(dev, "PHY pattern not found: %d, skipping PHY tuning\n", + ret); + return ret; + } + + if (read_op->cmd.dtr || read_op->addr.dtr || read_op->dummy.dtr || + read_op->data.dtr) { + cqspi_phy_pre_config(cqspi, f_pdata, false); + ret =3D cqspi_phy_tuning_ddr(f_pdata, mem); + } else { + cqspi_phy_pre_config(cqspi, f_pdata, true); + ret =3D cqspi_phy_tuning_sdr(f_pdata, mem); + } + + if (ret) + dev_warn(dev, "PHY tuning failed: %d\n", ret); + + cqspi_phy_post_config(cqspi, f_pdata->read_delay); + + return ret; +} + +static u32 cqspi_am654_ospi_get_non_phy_clk_rate(struct cqspi_st *cqspi) +{ + return CQSPI_AM654_NON_PHY_CLK_RATE; +} + +static int cqspi_mem_op_execute_tuning(struct spi_mem *mem, + struct spi_mem_op *read_op, + struct spi_mem_op *write_op) +{ + struct cqspi_st *cqspi =3D + spi_controller_get_devdata(mem->spi->controller); + + if (!cqspi->ddata->execute_tuning) + return -EOPNOTSUPP; + + return cqspi->ddata->execute_tuning(mem, read_op, write_op); +} + static int cqspi_of_get_flash_pdata(struct platform_device *pdev, struct cqspi_flash_pdata *f_pdata, struct device_node *np) @@ -1584,6 +1818,10 @@ static int cqspi_of_get_flash_pdata(struct platform_= device *pdev, return -ENXIO; } =20 + if (f_pdata->cqspi->ddata->get_non_phy_clk_rate) + f_pdata->non_phy_clk_rate =3D + f_pdata->cqspi->ddata->get_non_phy_clk_rate(f_pdata->cqspi); + f_pdata->has_dqs =3D of_property_read_bool(np, "spi-has-dqs"); =20 return 0; @@ -1725,6 +1963,7 @@ static const struct spi_controller_mem_ops cqspi_mem_= ops =3D { .exec_op =3D cqspi_exec_mem_op, .get_name =3D cqspi_get_name, .supports_op =3D cqspi_supports_mem_op, + .execute_tuning =3D cqspi_mem_op_execute_tuning, }; =20 static const struct spi_controller_mem_caps cqspi_mem_caps =3D { @@ -2136,6 +2375,8 @@ static const struct cqspi_driver_platdata k2g_qspi = =3D { static const struct cqspi_driver_platdata am654_ospi =3D { .hwcaps_mask =3D CQSPI_SUPPORTS_OCTAL | CQSPI_SUPPORTS_QUAD, .quirks =3D CQSPI_NEEDS_WR_DELAY, + .execute_tuning =3D cqspi_am654_ospi_execute_tuning, + .get_non_phy_clk_rate =3D cqspi_am654_ospi_get_non_phy_clk_rate, }; =20 static const struct cqspi_driver_platdata intel_lgm_qspi =3D { --=20 2.34.1 From nobody Sun Feb 8 11:40:22 2026 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013061.outbound.protection.outlook.com [40.107.201.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09E2F2836A0; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:17:57.4990 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 67f2d51e-96bb-4a06-60c7-08de52ae8cf8 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR10MB4674 Implement PHY tuning for SDR and DDR modes. PHY tuning calibrates RX and TX delay lines to find optimal timing for high-speed operation. Add DLL management functions: - cqspi_resync_dll(): Reset DLL and wait for lock - cqspi_set_dll(): Configure RX/TX delays (0-127) Add pre/post config functions that enable PHY mode during tuning and restore normal operation afterward. PHY mode consumes one dummy cycle, so adjust dummy count to maintain correct flash timing. SDR tuning uses 1D search across RX delays at fixed TX. Search for two valid windows at consecutive read_delay values, select the larger window, and use the midpoint. DDR tuning uses 2D search across RX and TX delays: - Primary and secondary RX boundary searches at different TX values - Binary search for gap boundaries within valid region - Temperature compensation with midpoint calculation - Systematic boundary searches using 4-step increments The DDR algorithm finds the four corners of the valid region, identifies gaps, calculates temperature-aware midpoints, and validates final settings. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 1519 ++++++++++++++++++++++++++++- 1 file changed, 1513 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index b8b0e85f4f68..930ea094f6d8 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -63,6 +63,12 @@ enum { =20 struct cqspi_st; =20 +struct phy_setting { + u8 rx; + u8 tx; + u8 read_delay; +}; + struct cqspi_flash_pdata { struct cqspi_st *cqspi; u32 clk_rate; @@ -73,7 +79,9 @@ struct cqspi_flash_pdata { u32 tchsh_ns; u32 tslch_ns; bool has_dqs; + bool use_phy; u8 cs; + struct phy_setting phy_setting; struct spi_mem_op phy_read_op; struct spi_mem_op phy_write_op; }; @@ -137,6 +145,7 @@ struct cqspi_driver_platdata { #define CQSPI_TIMEOUT_MS 500 #define CQSPI_READ_TIMEOUT_MS 10 #define CQSPI_BUSYWAIT_TIMEOUT_US 500 +#define CQSPI_DLL_TIMEOUT_US 300 =20 /* Runtime_pm autosuspend delay */ #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 @@ -150,12 +159,14 @@ struct cqspi_driver_platdata { /* Register map */ #define CQSPI_REG_CONFIG 0x00 #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0) +#define CQSPI_REG_CONFIG_PHY_EN BIT(3) #define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7) #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9) #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10 #define CQSPI_REG_CONFIG_DMA_MASK BIT(15) #define CQSPI_REG_CONFIG_BAUD_LSB 19 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24) +#define CQSPI_REG_CONFIG_PHY_PIPELINE BIT(25) #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30) #define CQSPI_REG_CONFIG_IDLE_LSB 31 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF @@ -194,6 +205,7 @@ struct cqspi_driver_platdata { #define CQSPI_REG_READCAPTURE_BYPASS_LSB 0 #define CQSPI_REG_READCAPTURE_DELAY_LSB 1 #define CQSPI_REG_READCAPTURE_DELAY_MASK 0xF +#define CQSPI_REG_READCAPTURE_EDGE_LSB 5 #define CQSPI_REG_READCAPTURE_DQS_LSB 8 =20 #define CQSPI_REG_SIZE 0x14 @@ -273,6 +285,27 @@ struct cqspi_driver_platdata { #define CQSPI_REG_POLLING_STATUS 0xB0 #define CQSPI_REG_POLLING_STATUS_DUMMY_LSB 16 =20 +#define CQSPI_REG_PHY_CONFIG 0xB4 +#define CQSPI_REG_PHY_CONFIG_RX_DEL_LSB 0 +#define CQSPI_REG_PHY_CONFIG_RX_DEL_MASK 0x7F +#define CQSPI_REG_PHY_CONFIG_TX_DEL_LSB 16 +#define CQSPI_REG_PHY_CONFIG_TX_DEL_MASK 0x7F +#define CQSPI_REG_PHY_CONFIG_DLL_RESET BIT(30) +#define CQSPI_REG_PHY_CONFIG_RESYNC BIT(31) + +#define CQSPI_REG_PHY_DLL_MASTER 0xB8 +#define CQSPI_REG_PHY_DLL_MASTER_INIT_DELAY_LSB 0 +#define CQSPI_REG_PHY_DLL_MASTER_INIT_DELAY_VAL 16 +#define CQSPI_REG_PHY_DLL_MASTER_DLY_ELMTS_LEN 0x7 +#define CQSPI_REG_PHY_DLL_MASTER_DLY_ELMTS_LSB 20 +#define CQSPI_REG_PHY_DLL_MASTER_DLY_ELMTS_3 0x2 +#define CQSPI_REG_PHY_DLL_MASTER_BYPASS BIT(23) +#define CQSPI_REG_PHY_DLL_MASTER_CYCLE BIT(24) + +#define CQSPI_REG_DLL_OBS_LOW 0xBC +#define CQSPI_REG_DLL_OBS_LOW_DLL_LOCK BIT(0) +#define CQSPI_REG_DLL_OBS_LOW_LOOPBACK_LOCK BIT(15) + #define CQSPI_REG_OP_EXT_LOWER 0xE0 #define CQSPI_REG_OP_EXT_READ_LSB 24 #define CQSPI_REG_OP_EXT_WRITE_LSB 16 @@ -321,6 +354,33 @@ struct cqspi_driver_platdata { =20 #define CQSPI_REG_VERSAL_DMA_VAL 0x602 =20 +#define CQSPI_PHY_INIT_RD 1 +#define CQSPI_PHY_MAX_RD 4 +#define CQSPI_PHY_MAX_DELAY 127 +#define CQSPI_PHY_DDR_SEARCH_STEP 4 +#define CQSPI_PHY_MAX_RX 63 +#define CQSPI_PHY_MAX_TX 63 +#define CQSPI_PHY_TX_LOOKUP_LOW_START 28 +#define CQSPI_PHY_TX_LOOKUP_LOW_END 48 +#define CQSPI_PHY_TX_LOOKUP_HIGH_START 60 +#define CQSPI_PHY_TX_LOOKUP_HIGH_END 96 +#define CQSPI_PHY_RX_LOW_SEARCH_START 0 +#define CQSPI_PHY_RX_LOW_SEARCH_END 40 +#define CQSPI_PHY_RX_HIGH_SEARCH_START 24 +#define CQSPI_PHY_RX_HIGH_SEARCH_END 127 +#define CQSPI_PHY_TX_LOW_SEARCH_START 0 +#define CQSPI_PHY_TX_LOW_SEARCH_END 64 +#define CQSPI_PHY_TX_HIGH_SEARCH_START 78 +#define CQSPI_PHY_TX_HIGH_SEARCH_END 127 +#define CQSPI_PHY_SEARCH_OFFSET 8 + +#define CQSPI_PHY_DEFAULT_TEMP 45 +#define CQSPI_PHY_MIN_TEMP -45 +#define CQSPI_PHY_MAX_TEMP 130 +#define CQSPI_PHY_MID_TEMP (CQSPI_PHY_MIN_TEMP + \ + ((CQSPI_PHY_MAX_TEMP - \ + CQSPI_PHY_MIN_TEMP) / 2)) + /* * PHY tuning pattern for calibrating read data capture delay. This 128-by= te * pattern provides sufficient bit transitions across all byte lanes to @@ -1671,31 +1731,1478 @@ static int cqspi_phy_check_pattern(struct cqspi_f= lash_pdata *f_pdata, return ret; } =20 +static void cqspi_phy_set_dll_master(struct cqspi_st *cqspi) +{ + void __iomem *reg_base =3D cqspi->iobase; + unsigned int reg; + + reg =3D readl(reg_base + CQSPI_REG_PHY_DLL_MASTER); + reg &=3D ~((CQSPI_REG_PHY_DLL_MASTER_DLY_ELMTS_LEN + << CQSPI_REG_PHY_DLL_MASTER_DLY_ELMTS_LSB) | + CQSPI_REG_PHY_DLL_MASTER_BYPASS | + CQSPI_REG_PHY_DLL_MASTER_CYCLE); + reg |=3D ((CQSPI_REG_PHY_DLL_MASTER_DLY_ELMTS_3 + << CQSPI_REG_PHY_DLL_MASTER_DLY_ELMTS_LSB) | + CQSPI_REG_PHY_DLL_MASTER_CYCLE); + + writel(reg, reg_base + CQSPI_REG_PHY_DLL_MASTER); +} + static void cqspi_phy_pre_config(struct cqspi_st *cqspi, struct cqspi_flash_pdata *f_pdata, const bool bypass) { - /* Placeholder for PHY pre-configuration */ + void __iomem *reg_base =3D cqspi->iobase; + unsigned int reg; + u8 dummy; + + cqspi_readdata_capture(cqspi, bypass, f_pdata->has_dqs, + f_pdata->phy_setting.read_delay); + + reg =3D readl(reg_base + CQSPI_REG_CONFIG); + reg &=3D ~(CQSPI_REG_CONFIG_PHY_EN | CQSPI_REG_CONFIG_PHY_PIPELINE); + reg |=3D CQSPI_REG_CONFIG_PHY_EN; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + reg =3D readl(reg_base + CQSPI_REG_RD_INSTR); + dummy =3D FIELD_GET(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + reg); + dummy--; + reg &=3D ~(CQSPI_REG_RD_INSTR_DUMMY_MASK << CQSPI_REG_RD_INSTR_DUMMY_LSB); + reg |=3D FIELD_PREP(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + dummy); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); + + cqspi_phy_set_dll_master(cqspi); } =20 static void cqspi_phy_post_config(struct cqspi_st *cqspi, const unsigned int delay) { - /* Placeholder for PHY post-configuration */ + void __iomem *reg_base =3D cqspi->iobase; + unsigned int reg; + u8 dummy; + + reg =3D readl(reg_base + CQSPI_REG_READCAPTURE); + reg &=3D ~(CQSPI_REG_READCAPTURE_DELAY_MASK + << CQSPI_REG_READCAPTURE_DELAY_LSB); + + reg |=3D (delay & CQSPI_REG_READCAPTURE_DELAY_MASK) + << CQSPI_REG_READCAPTURE_DELAY_LSB; + writel(reg, reg_base + CQSPI_REG_READCAPTURE); + + reg =3D readl(reg_base + CQSPI_REG_CONFIG); + reg &=3D ~(CQSPI_REG_CONFIG_PHY_EN | CQSPI_REG_CONFIG_PHY_PIPELINE); + writel(reg, reg_base + CQSPI_REG_CONFIG); + + reg =3D readl(reg_base + CQSPI_REG_RD_INSTR); + dummy =3D FIELD_GET(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + reg); + dummy++; + reg &=3D ~(CQSPI_REG_RD_INSTR_DUMMY_MASK << CQSPI_REG_RD_INSTR_DUMMY_LSB); + reg |=3D FIELD_PREP(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + dummy); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); +} + +static void cqspi_set_dll(void __iomem *reg_base, u8 rx_dll, u8 tx_dll) +{ + unsigned int reg; + + reg =3D readl(reg_base + CQSPI_REG_PHY_CONFIG); + reg &=3D ~((CQSPI_REG_PHY_CONFIG_RX_DEL_MASK + << CQSPI_REG_PHY_CONFIG_RX_DEL_LSB) | + (CQSPI_REG_PHY_CONFIG_TX_DEL_MASK + << CQSPI_REG_PHY_CONFIG_TX_DEL_LSB)); + reg |=3D ((rx_dll & CQSPI_REG_PHY_CONFIG_RX_DEL_MASK) + << CQSPI_REG_PHY_CONFIG_RX_DEL_LSB) | + ((tx_dll & CQSPI_REG_PHY_CONFIG_TX_DEL_MASK) + << CQSPI_REG_PHY_CONFIG_TX_DEL_LSB) | + CQSPI_REG_PHY_CONFIG_RESYNC; + writel(reg, reg_base + CQSPI_REG_PHY_CONFIG); +} + +static int cqspi_resync_dll(struct cqspi_st *cqspi) +{ + void __iomem *reg_base =3D cqspi->iobase; + unsigned int reg; + int ret; + + ret =3D cqspi_wait_idle(cqspi); + if (ret) + return ret; + + reg =3D readl(reg_base + CQSPI_REG_CONFIG); + reg &=3D ~(CQSPI_REG_CONFIG_ENABLE_MASK); + writel(reg, reg_base + CQSPI_REG_CONFIG); + + reg =3D readl(reg_base + CQSPI_REG_PHY_CONFIG); + reg &=3D ~(CQSPI_REG_PHY_CONFIG_DLL_RESET | + CQSPI_REG_PHY_CONFIG_RESYNC); + writel(reg, reg_base + CQSPI_REG_PHY_CONFIG); + + reg =3D readl(reg_base + CQSPI_REG_PHY_DLL_MASTER); + reg |=3D (CQSPI_REG_PHY_DLL_MASTER_INIT_DELAY_VAL + << CQSPI_REG_PHY_DLL_MASTER_INIT_DELAY_LSB); + writel(reg, reg_base + CQSPI_REG_PHY_DLL_MASTER); + + reg =3D readl(reg_base + CQSPI_REG_PHY_CONFIG); + reg |=3D CQSPI_REG_PHY_CONFIG_DLL_RESET; + writel(reg, reg_base + CQSPI_REG_PHY_CONFIG); + + ret =3D readl_poll_timeout(reg_base + CQSPI_REG_DLL_OBS_LOW, reg, + (reg & CQSPI_REG_DLL_OBS_LOW_DLL_LOCK), 0, + CQSPI_DLL_TIMEOUT_US); + if (ret) + return ret; + + ret =3D readl_poll_timeout(reg_base + CQSPI_REG_DLL_OBS_LOW, reg, + (reg & CQSPI_REG_DLL_OBS_LOW_LOOPBACK_LOCK), 0, + CQSPI_DLL_TIMEOUT_US); + if (ret) + return ret; + + reg =3D readl(reg_base + CQSPI_REG_PHY_CONFIG); + reg |=3D CQSPI_REG_PHY_CONFIG_RESYNC; + writel(reg, reg_base + CQSPI_REG_PHY_CONFIG); + + reg =3D readl(reg_base + CQSPI_REG_CONFIG); + reg |=3D CQSPI_REG_CONFIG_ENABLE_MASK; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + return 0; +} + +static int cqspi_phy_apply_setting(struct cqspi_flash_pdata *f_pdata, + struct phy_setting *phy) +{ + struct cqspi_st *cqspi =3D f_pdata->cqspi; + unsigned int reg; + + reg =3D readl(cqspi->iobase + CQSPI_REG_READCAPTURE); + reg |=3D BIT(CQSPI_REG_READCAPTURE_EDGE_LSB); + writel(reg, cqspi->iobase + CQSPI_REG_READCAPTURE); + + cqspi_set_dll(cqspi->iobase, phy->rx, phy->tx); + f_pdata->phy_setting.read_delay =3D phy->read_delay; + + return cqspi_resync_dll(cqspi); +} + +static int cqspi_find_rx_low_ddr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, struct phy_setting *phy) +{ + struct device *dev =3D &f_pdata->cqspi->pdev->dev; + int ret; + + do { + phy->rx =3D CQSPI_PHY_RX_LOW_SEARCH_START; + do { + ret =3D cqspi_phy_apply_setting(f_pdata, phy); + if (!ret) { + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + if (!ret) + return 0; + } + + phy->rx +=3D CQSPI_PHY_DDR_SEARCH_STEP; + } while (phy->rx <=3D CQSPI_PHY_RX_LOW_SEARCH_END); + + phy->read_delay++; + } while (phy->read_delay <=3D CQSPI_PHY_MAX_RD); + + dev_dbg(dev, "Unable to find RX low\n"); + return -ENOENT; +} + +static int cqspi_find_rx_low_sdr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, struct phy_setting *phy) +{ + struct device *dev =3D &f_pdata->cqspi->pdev->dev; + int ret; + + phy->rx =3D 0; + do { + ret =3D cqspi_phy_apply_setting(f_pdata, phy); + if (!ret) { + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + if (!ret) + return 0; + } + phy->rx++; + } while (phy->rx < CQSPI_PHY_MAX_DELAY - 1); + + dev_dbg(dev, "Unable to find RX low\n"); + return -ENOENT; +} + +static int cqspi_find_rx_high_ddr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, struct phy_setting *phy) +{ + struct device *dev =3D &f_pdata->cqspi->pdev->dev; + int ret; + + do { + phy->rx =3D CQSPI_PHY_RX_HIGH_SEARCH_END; + do { + ret =3D cqspi_phy_apply_setting(f_pdata, phy); + if (!ret) { + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + if (!ret) + return 0; + } + + phy->rx -=3D CQSPI_PHY_DDR_SEARCH_STEP; + } while (phy->rx >=3D CQSPI_PHY_RX_HIGH_SEARCH_START); + + phy->read_delay--; + } while (phy->read_delay >=3D CQSPI_PHY_INIT_RD); + + dev_dbg(dev, "Unable to find RX high\n"); + return -ENOENT; +} + +static int cqspi_find_rx_high_sdr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, struct phy_setting *phy, + u8 lowerbound) +{ + struct device *dev =3D &f_pdata->cqspi->pdev->dev; + int ret; + + phy->rx =3D CQSPI_PHY_MAX_DELAY; + do { + ret =3D cqspi_phy_apply_setting(f_pdata, phy); + if (!ret) { + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + if (!ret) + return 0; + } + phy->rx--; + } while (phy->rx > lowerbound); + + dev_dbg(dev, "Unable to find RX high\n"); + return -ENOENT; +} + +static int cqspi_find_tx_low_ddr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, struct phy_setting *phy) +{ + struct device *dev =3D &f_pdata->cqspi->pdev->dev; + int ret; + + do { + phy->tx =3D CQSPI_PHY_TX_LOW_SEARCH_START; + do { + ret =3D cqspi_phy_apply_setting(f_pdata, phy); + if (!ret) { + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + if (!ret) + return 0; + } + + phy->tx +=3D CQSPI_PHY_DDR_SEARCH_STEP; + } while (phy->tx <=3D CQSPI_PHY_TX_LOW_SEARCH_END); + + phy->read_delay++; + } while (phy->read_delay <=3D CQSPI_PHY_MAX_RD); + + dev_dbg(dev, "Unable to find TX low\n"); + return -ENOENT; +} + +static int cqspi_find_tx_high_ddr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, struct phy_setting *phy) +{ + struct device *dev =3D &f_pdata->cqspi->pdev->dev; + int ret; + + do { + phy->tx =3D CQSPI_PHY_TX_HIGH_SEARCH_END; + do { + ret =3D cqspi_phy_apply_setting(f_pdata, phy); + if (!ret) { + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + if (!ret) + return 0; + } + + phy->tx -=3D CQSPI_PHY_DDR_SEARCH_STEP; + } while (phy->tx >=3D CQSPI_PHY_TX_HIGH_SEARCH_START); + + phy->read_delay--; + } while (phy->read_delay >=3D CQSPI_PHY_INIT_RD); + + dev_dbg(dev, "Unable to find TX high\n"); + return -ENOENT; +} + +static int cqspi_phy_find_gaplow_ddr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, + struct phy_setting *bottomleft, + struct phy_setting *topright, + struct phy_setting *gaplow) +{ + struct phy_setting left, right, mid; + int ret; + + left =3D *bottomleft; + right =3D *topright; + + mid.tx =3D left.tx + ((right.tx - left.tx) / 2); + mid.rx =3D left.rx + ((right.rx - left.rx) / 2); + mid.read_delay =3D left.read_delay; + + do { + ret =3D cqspi_phy_apply_setting(f_pdata, &mid); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret) { + /* The pattern was not found. Go to the lower half. */ + right.tx =3D mid.tx; + right.rx =3D mid.rx; + + mid.tx =3D left.tx + ((mid.tx - left.tx) / 2); + mid.rx =3D left.rx + ((mid.rx - left.rx) / 2); + } else { + /* The pattern was found. Go to the upper half. */ + left.tx =3D mid.tx; + left.rx =3D mid.rx; + + mid.tx =3D mid.tx + ((right.tx - mid.tx) / 2); + mid.rx =3D mid.rx + ((right.rx - mid.rx) / 2); + } + + /* Break the loop if the window has closed. */ + } while ((right.tx - left.tx >=3D 2) && (right.rx - left.rx >=3D 2)); + + *gaplow =3D mid; + return 0; +} + +static int cqspi_phy_find_gaphigh_ddr(struct cqspi_flash_pdata *f_pdata, + struct spi_mem *mem, + struct phy_setting *bottomleft, + struct phy_setting *topright, + struct phy_setting *gaphigh) +{ + struct phy_setting left, right, mid; + int ret; + + left =3D *bottomleft; + right =3D *topright; + + mid.tx =3D left.tx + ((right.tx - left.tx) / 2); + mid.rx =3D left.rx + ((right.rx - left.rx) / 2); + mid.read_delay =3D right.read_delay; + + do { + ret =3D cqspi_phy_apply_setting(f_pdata, &mid); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret) { + /* The pattern was not found. Go to the upper half. */ + left.tx =3D mid.tx; + left.rx =3D mid.rx; + + mid.tx =3D mid.tx + ((right.tx - mid.tx) / 2); + mid.rx =3D mid.rx + ((right.rx - mid.rx) / 2); + } else { + /* The pattern was found. Go to the lower half. */ + right.tx =3D mid.tx; + right.rx =3D mid.rx; + + mid.tx =3D left.tx + ((mid.tx - left.tx) / 2); + mid.rx =3D left.rx + ((mid.rx - left.rx) / 2); + } + + /* Break the loop if the window has closed. */ + } while ((right.tx - left.tx >=3D 2) && (right.rx - left.rx >=3D 2)); + + *gaphigh =3D mid; + return 0; +} + +static int cqspi_get_temp(int *temp) +{ + /* + * TODO: Implement temperature sensor reading for DDR PHY tuning. + * + * The DDR tuning algorithm uses temperature compensation to adjust + * the final tuning point based on current die temperature. The valid + * timing region shifts with temperature variations, and this offset + * helps maintain optimal settings across the operating range + * (-45=C2=B0C to 130=C2=B0C). + * + * This function should: + * - Read the SoC die temperature from the thermal sensor + * - Populate the temp parameter with temperature in degrees Celsius + * - Return 0 on success, negative error code on failure + * + * Until implemented, the tuning algorithm falls back to assuming + * room temperature (45=C2=B0C) for temperature compensation calculations. + */ + + return -EOPNOTSUPP; +} + +static inline void cqspi_phy_reset_setting(struct phy_setting *phy) +{ + *phy =3D (struct phy_setting){ .rx =3D 0, .tx =3D 127, .read_delay =3D 0 = }; } =20 static int cqspi_phy_tuning_ddr(struct cqspi_flash_pdata *f_pdata, struct spi_mem *mem) { - /* Placeholder for DDR mode PHY tuning algorithm */ - return 0; + struct cqspi_st *cqspi =3D f_pdata->cqspi; + struct device *dev =3D &cqspi->pdev->dev; + struct phy_setting rxlow, rxhigh, txlow, txhigh; + struct phy_setting srxlow, srxhigh; + struct phy_setting bottomleft, topright, searchpoint; + struct phy_setting gaplow, gaphigh; + struct phy_setting backuppoint, backupcornerpoint; + int ret, tmp; + bool primary =3D 1, secondary =3D 1; + + /* + * DDR tuning: 2D search across RX and TX delays for optimal timing. + * + * Algorithm: Find RX boundaries (rxlow/rxhigh) using TX window search, + * find TX boundaries (txlow/txhigh) at fixed RX, define valid region, + * locate gaps via binary search, select final point with temperature + * compensation. + * + * rx + * 127 ^ + * | topright + * | * + * | xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * | xxxxxxx ++++++++++++++++++ + * | xxxxxxxx +++++++++++++++++ + * | xxxxxxxxx ++++++++++++++++ + * | xxxxxxxxxx +++++++++++++++ + * | xxxxxxxxxxx ++++++++++++++ + * | xxxxxxxxxxxx +++++++++++++ + * | xxxxxxxxxxxxx ++++++++++++ + * | xxxxxxxxxxxxxx +++++++++++ + * | xxxxxxxxxxxxxxx ++++++++++ + * | xxxxxxxxxxxxxxxx +++++++++ + * | xxxxxxxxxxxxxxxxx ++++++++ + * | xxxxxxxxxxxxxxxxxx +++++++ + * | * + * | bottomleft + * -----------------------------------------> tx + * 0 127 + */ + + f_pdata->use_phy =3D true; + + /* Golden rxlow search: Find lower RX boundary using TX window sweep */ + + /* + * rx + * 127 ^ + * | xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * | xxxxxxx ++++++++++++++++++ + * | xxxxxxxx +++++++++++++++++ + * | xxxxxxxxx ++++++++++++++++ + * | xxxxxxxxxx +++++++++++++++ + * | xxxxxxxxxxx ++++++++++++++ + * | |xxxxx|xxxxx +++++++++++++ + * | |xxxxx|xxxxxx ++++++++++++ + * search | |xxxxx|xxxxxxx +++++++++++ + * rxlow --------->|xxxxx|xxxxxxxx ++++++++++ + * | |xxxxx|xxxxxxxxx +++++++++ + * | |xxxxx|xxxxxxxxxx ++++++++ + * | |xxxxx|xxxxxxxxxxx +++++++ + * | | | + * --------|-----|----------------------------> tx + * 0 | | 127 + * txlow txlow + * start end + * + * |----------------------------------------------------------| + * | Primary | Secondary | Final | + * | Search | Search | Point | + * |---------|-----------|------------------------------------| + * | Fail | Fail | Return Fail | + * |---------|-----------|------------------------------------| + * | Fail | Pass | Return Fail | + * |---------|-----------|------------------------------------| + * | Pass | Fail | Return Fail | + * |---------|-----------|------------------------------------| + * | Pass | Pass | rx =3D min(primary.rx, secondary.rx) | + * | | | tx =3D primary.tx | + * | | | read_delay =3D | + * | | | min(primary.read_delay, | + * | | | secondary.read_delay) | + * |----------------------------------------------------------| + */ + + /* Primary rxlow: Sweep TX window to find valid RX lower bound */ + + rxlow.tx =3D CQSPI_PHY_TX_LOOKUP_LOW_START; + do { + dev_dbg(dev, "Searching for Golden Primary rxlow on TX =3D %d\n", + rxlow.tx); + rxlow.read_delay =3D CQSPI_PHY_INIT_RD; + ret =3D cqspi_find_rx_low_ddr(f_pdata, mem, &rxlow); + rxlow.tx +=3D CQSPI_PHY_DDR_SEARCH_STEP; + } while (ret && rxlow.tx <=3D CQSPI_PHY_TX_LOOKUP_LOW_END); + if (ret) + goto out; + dev_dbg(dev, "Golden Primary rxlow: RX: %d TX: %d RD: %d\n", rxlow.rx, + rxlow.tx, rxlow.read_delay); + + /* Secondary rxlow: Verify at offset TX for robustness */ + + if (rxlow.tx <=3D (CQSPI_PHY_TX_LOOKUP_LOW_END - CQSPI_PHY_SEARCH_OFFSET)) + srxlow.tx =3D rxlow.tx + CQSPI_PHY_SEARCH_OFFSET; + else + srxlow.tx =3D CQSPI_PHY_TX_LOOKUP_LOW_END; + dev_dbg(dev, "Searching for Golden Secondary rxlow on TX =3D %d\n", + srxlow.tx); + srxlow.read_delay =3D CQSPI_PHY_INIT_RD; + ret =3D cqspi_find_rx_low_ddr(f_pdata, mem, &srxlow); + if (ret) + goto out; + dev_dbg(dev, "Golden Secondary rxlow: RX: %d TX: %d RD: %d\n", + srxlow.rx, srxlow.tx, srxlow.read_delay); + + rxlow.rx =3D min(rxlow.rx, srxlow.rx); + rxlow.read_delay =3D min(rxlow.read_delay, srxlow.read_delay); + dev_dbg(dev, "Golden Final rxlow: RX: %d TX: %d RD: %d\n", rxlow.rx, + rxlow.tx, rxlow.read_delay); + + /* Golden rxhigh search: Find upper RX boundary at fixed TX */ + + /* + * rx + * 127 ^ + * | |xxxx ++++++++++++++++++++ + * | |xxxxx +++++++++++++++++++ + * search | |xxxxxx ++++++++++++++++++ + * rxhigh --------->|xxxxxxx +++++++++++++++++ + * on fixed | |xxxxxxxx ++++++++++++++++ + * tx | |xxxxxxxxx +++++++++++++++ + * | |xxxxxxxxxx ++++++++++++++ + * | xxxxxxxxxxxx +++++++++++++ + * | xxxxxxxxxxxxx ++++++++++++ + * | xxxxxxxxxxxxxx +++++++++++ + * | xxxxxxxxxxxxxxx ++++++++++ + * | xxxxxxxxxxxxxxxx +++++++++ + * | xxxxxxxxxxxxxxxxx ++++++++ + * | xxxxxxxxxxxxxxxxxx +++++++ + * | + * -------------------------------------------> tx + * 0 127 + * + * |----------------------------------------------------------| + * | Primary | Secondary | Final | + * | Search | Search | Point | + * |---------|-----------|------------------------------------| + * | Fail | Fail | Return Fail | + * |---------|-----------|------------------------------------| + * | Fail | Pass | Choose Secondary | + * |---------|-----------|------------------------------------| + * | Pass | Fail | Choose Primary | + * |---------|-----------|------------------------------------| + * | Pass | Pass | if (secondary.rx > primary.rx) | + * | | | Choose Secondary | + * | | | else | + * | | | Choose Primary | + * |----------------------------------------------------------| + */ + + /* Primary rxhigh: Search at rxlow's TX, decrement from max read_delay */ + + rxhigh.tx =3D rxlow.tx; + dev_dbg(dev, "Searching for Golden Primary rxhigh on TX =3D %d\n", + rxhigh.tx); + rxhigh.read_delay =3D CQSPI_PHY_MAX_RD; + ret =3D cqspi_find_rx_high_ddr(f_pdata, mem, &rxhigh); + if (ret) + primary =3D 0; + dev_dbg(dev, "Golden Primary rxhigh: RX: %d TX: %d RD: %d\n", rxhigh.rx, + rxhigh.tx, rxhigh.read_delay); + + /* Secondary rxhigh: Verify at offset TX */ + + if (rxhigh.tx <=3D + (CQSPI_PHY_TX_LOOKUP_LOW_END - CQSPI_PHY_SEARCH_OFFSET)) + srxhigh.tx =3D rxhigh.tx + CQSPI_PHY_SEARCH_OFFSET; + else + srxhigh.tx =3D CQSPI_PHY_TX_LOOKUP_LOW_END; + dev_dbg(dev, "Searching for Golden Secondary rxhigh on TX =3D %d\n", + srxhigh.tx); + srxhigh.read_delay =3D CQSPI_PHY_MAX_RD; + ret =3D cqspi_find_rx_high_ddr(f_pdata, mem, &srxhigh); + if (ret) + secondary =3D 0; + dev_dbg(dev, "Golden Secondary rxhigh: RX: %d TX: %d RD: %d\n", + srxhigh.rx, srxhigh.tx, srxhigh.read_delay); + + if (primary || secondary) { + if (srxhigh.rx > rxhigh.rx) + rxhigh =3D srxhigh; + } else { + goto out; + } + dev_dbg(dev, "Golden Final rxhigh: RX: %d TX: %d RD: %d\n", rxhigh.rx, + rxhigh.tx, rxhigh.read_delay); + + primary =3D 1; + secondary =3D 1; + + /* If rxlow/rxhigh at same read_delay, search backup at upper TX range */ + + if (rxlow.read_delay =3D=3D rxhigh.read_delay) { + dev_dbg(dev, "rxlow and rxhigh at the same read delay.\n"); + + /* Backup rxlow: Search at high TX window */ + + /* + * rx + * 127 ^ + * | xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * | xxxxxxx ++++++++++++++++++ + * | xxxxxxxx +++++++++++++++++ + * | xxxxxxxxx ++++++++++++++++ + * | xxxxxxxxxx +++++++++++++++ + * | xxxxxxxxxxx ++++++++++++++ + * | xxxxxxxxxxxx +++++++|++++| + * | xxxxxxxxxxxxx ++++++|++++| + * search | xxxxxxxxxxxxxx +++++|++++| + * rxlow --------------------------------->|++++| + * | xxxxxxxxxxxxxxxx +++|++++| + * | xxxxxxxxxxxxxxxxx ++|++++| + * | xxxxxxxxxxxxxxxxxx +|++++| + * | | | + * --------------------------------|----|-----> tx + * 0 | | 127 + * txhigh txhigh + * start end + * + * |-----------------------------------------------------| + * | Primary | Secondary | Final | + * | Search | Search | Point | + * |---------|-----------|-------------------------------| + * | Fail | Fail | Return Fail | + * |---------|-----------|-------------------------------| + * | Fail | Pass | Return Fail | + * |---------|-----------|-------------------------------| + * | Pass | Fail | Return Fail | + * |---------|-----------|-------------------------------| + * | Pass | Pass | rx =3D | + * | | | min(primary.rx, secondary.rx)| + * | | | tx =3D primary.tx | + * | | | read_delay =3D | + * | | | min(primary.read_delay, | + * | | | secondary.read_delay) | + * |-----------------------------------------------------| + */ + + /* Primary backup: Decrement TX from high window end */ + + backuppoint.tx =3D CQSPI_PHY_TX_LOOKUP_HIGH_END; + do { + dev_dbg(dev, + "Searching for Backup Primary rxlow on TX =3D %d\n", + backuppoint.tx); + backuppoint.read_delay =3D CQSPI_PHY_INIT_RD; + ret =3D cqspi_find_rx_low_ddr(f_pdata, mem, &backuppoint); + backuppoint.tx -=3D CQSPI_PHY_DDR_SEARCH_STEP; + } while (ret && + backuppoint.tx >=3D CQSPI_PHY_TX_LOOKUP_HIGH_START); + if (ret) + goto out; + dev_dbg(dev, "Backup Primary rxlow: RX: %d TX: %d RD: %d\n", + backuppoint.rx, backuppoint.tx, backuppoint.read_delay); + + /* Secondary backup: Verify at offset TX */ + + if (backuppoint.tx >=3D + (CQSPI_PHY_TX_LOOKUP_HIGH_START + CQSPI_PHY_SEARCH_OFFSET)) + srxlow.tx =3D backuppoint.tx - CQSPI_PHY_SEARCH_OFFSET; + else + srxlow.tx =3D CQSPI_PHY_TX_LOOKUP_HIGH_START; + dev_dbg(dev, + "Searching for Backup Secondary rxlow on TX =3D %d\n", + srxlow.tx); + srxlow.read_delay =3D CQSPI_PHY_INIT_RD; + ret =3D cqspi_find_rx_low_ddr(f_pdata, mem, &srxlow); + if (ret) + goto out; + dev_dbg(dev, "Backup Secondary rxlow: RX: %d TX: %d RD: %d\n", + srxlow.rx, srxlow.tx, srxlow.read_delay); + + backuppoint.rx =3D min(backuppoint.rx, srxlow.rx); + backuppoint.read_delay =3D + min(backuppoint.read_delay, srxlow.read_delay); + dev_dbg(dev, "Backup Final rxlow: RX: %d TX: %d RD: %d\n", + backuppoint.rx, backuppoint.tx, backuppoint.read_delay); + + if (backuppoint.rx < rxlow.rx) { + rxlow =3D backuppoint; + dev_dbg(dev, "Updating rxlow to the one at TX =3D %d\n", + backuppoint.tx); + } + dev_dbg(dev, "Final rxlow: RX: %d TX: %d RD: %d\n", rxlow.rx, + rxlow.tx, rxlow.read_delay); + + /* Backup rxhigh: Search at fixed backup TX */ + + /* + * rx + * 127 ^ + * | xxxxx +++++++++++++++++++| + * | xxxxxx ++++++++++++++++++| + * search | xxxxxxx +++++++++++++++++| + * rxhigh -------------------------------------->| + * on fixed | xxxxxxxxx +++++++++++++++| + * tx | xxxxxxxxxx ++++++++++++++| + * | xxxxxxxxxxx +++++++++++++| + * | xxxxxxxxxxxx +++++++++++++ + * | xxxxxxxxxxxxx ++++++++++++ + * | xxxxxxxxxxxxxx +++++++++++ + * | xxxxxxxxxxxxxxx ++++++++++ + * | xxxxxxxxxxxxxxxx +++++++++ + * | xxxxxxxxxxxxxxxxx ++++++++ + * | xxxxxxxxxxxxxxxxxx +++++++ + * | + * -------------------------------------------> tx + * 0 127 + * + * |-----------------------------------------------------| + * | Primary | Secondary | Final | + * | Search | Search | Point | + * |---------|-----------|-------------------------------| + * | Fail | Fail | Return Fail | + * |---------|-----------|-------------------------------| + * | Fail | Pass | Choose Secondary | + * |---------|-----------|-------------------------------| + * | Pass | Fail | Choose Primary | + * |---------|-----------|-------------------------------| + * | Pass | Pass | if (secondary.rx > primary.rx)| + * | | | Choose Secondary | + * | | | else | + * | | | Choose Primary | + * |-----------------------------------------------------| + */ + + /* Primary backup rxhigh: Use backup TX, decrement from max read_delay */ + + dev_dbg(dev, "Searching for Backup Primary rxhigh on TX =3D %d\n", + backuppoint.tx); + backuppoint.read_delay =3D CQSPI_PHY_MAX_RD; + ret =3D cqspi_find_rx_high_ddr(f_pdata, mem, &backuppoint); + if (ret) + primary =3D 0; + dev_dbg(dev, "Backup Primary rxhigh: RX: %d TX: %d RD: %d\n", + backuppoint.rx, backuppoint.tx, backuppoint.read_delay); + + /* Secondary backup rxhigh: Verify at offset TX */ + + if (backuppoint.tx >=3D + (CQSPI_PHY_TX_LOOKUP_HIGH_START + CQSPI_PHY_SEARCH_OFFSET)) + srxhigh.tx =3D backuppoint.tx - CQSPI_PHY_SEARCH_OFFSET; + else + srxhigh.tx =3D CQSPI_PHY_TX_LOOKUP_HIGH_START; + dev_dbg(dev, + "Searching for Backup Secondary rxhigh on TX =3D %d\n", + srxhigh.tx); + srxhigh.read_delay =3D CQSPI_PHY_MAX_RD; + ret =3D cqspi_find_rx_high_ddr(f_pdata, mem, &srxhigh); + if (ret) + secondary =3D 0; + dev_dbg(dev, "Backup Secondary rxhigh: RX: %d TX: %d RD: %d\n", + srxhigh.rx, srxhigh.tx, srxhigh.read_delay); + + if (primary || secondary) { + if (srxhigh.rx > backuppoint.rx) + backuppoint =3D srxhigh; + } else { + goto out; + } + dev_dbg(dev, "Backup Final rxhigh: RX: %d TX: %d RD: %d\n", + backuppoint.rx, backuppoint.tx, backuppoint.read_delay); + + if (backuppoint.rx > rxhigh.rx) { + rxhigh =3D backuppoint; + dev_dbg(dev, "Updating rxhigh to the one at TX =3D %d\n", + backuppoint.tx); + } + dev_dbg(dev, "Final rxhigh: RX: %d TX: %d RD: %d\n", rxhigh.rx, + rxhigh.tx, rxhigh.read_delay); + } + + /* Golden txlow: Fix RX at 1/4 of RX window, search TX lower bound */ + + /* + * rx + * 127 ^ + * | + * rxhigh --------->xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * | xxxxxxx ++++++++++++++++++ + * | xxxxxxxx +++++++++++++++++ + * | xxxxxxxxx ++++++++++++++++ + * | xxxxxxxxxx +++++++++++++++ + * | xxxxxxxxxxx ++++++++++++++ + * | xxxxxxxxxxxx +++++++++++++ + * fix rx | xxxxxxxxxxxxx ++++++++++++ + * 1/4 b/w ---------><------->xxxxx +++++++++++ + * rxlow and | xxxx|xxxxxxxxxx ++++++++++ + * rxhigh | xxxx|xxxxxxxxxxx +++++++++ + * | xxxx|xxxxxxxxxxxx ++++++++ + * rxlow --------->xxxx|xxxxxxxxxxxxx +++++++ + * | | + * ------------|------------------------------> tx + * 0 | 127 + * search + * txlow + */ + + tmp =3D rxhigh.rx - rxlow.rx; + txlow.rx =3D rxlow.rx + (tmp / 4); + dev_dbg(dev, "Searching for Golden txlow on RX =3D %d\n", txlow.rx); + txlow.read_delay =3D CQSPI_PHY_INIT_RD; + ret =3D cqspi_find_tx_low_ddr(f_pdata, mem, &txlow); + if (ret) + goto out; + dev_dbg(dev, "Golden txlow: RX: %d TX: %d RD: %d\n", txlow.rx, txlow.tx, + txlow.read_delay); + + /* Golden txhigh: Same RX as txlow, decrement from max read_delay */ + + /* + * rx + * 127 ^ + * | + * rxhigh --------->xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * | xxxxxxx ++++++++++++++++++ + * | xxxxxxxx +++++++++++++++++ + * | xxxxxxxxx ++++++++++++++++ + * | xxxxxxxxxx +++++++++++++++ + * | xxxxxxxxxxx ++++++++++++++ + * | xxxxxxxxxxxx +++++++++++++ + * fix rx | xxxxxxxxxxxxx ++++++++++++ + * 1/4 b/w --------------------------------><-----> + * rxlow and | xxxxxxxxxxxxxxx ++++++|+++ + * rxhigh | xxxxxxxxxxxxxxxx +++++|+++ + * | xxxxxxxxxxxxxxxxx ++++|+++ + * rxlow --------->xxxxxxxxxxxxxxxxxx +++|+++ + * | | + * ----------------------------------|--------> tx + * 0 | 127 + * search + * txhigh + */ + + txhigh.rx =3D txlow.rx; + dev_dbg(dev, "Searching for Golden txhigh on RX =3D %d\n", txhigh.rx); + txhigh.read_delay =3D CQSPI_PHY_MAX_RD; + ret =3D cqspi_find_tx_high_ddr(f_pdata, mem, &txhigh); + if (ret) + goto out; + dev_dbg(dev, "Golden txhigh: RX: %d TX: %d RD: %d\n", txhigh.rx, + txhigh.tx, txhigh.read_delay); + + /* If txlow/txhigh at same read_delay, search backup at 3/4 RX window */ + + if (txlow.read_delay =3D=3D txhigh.read_delay) { + /* Backup txlow: Fix RX at 3/4 of RX window */ + + /* + * rx + * 127 ^ + * | + * rxhigh --------->xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * fix rx | xxxxxxx ++++++++++++++++++ + * 3/4 b/w ---------><----->x +++++++++++++++++ + * rxlow and | xxxx|xxxx ++++++++++++++++ + * rxhigh | xxxx|xxxxx +++++++++++++++ + * | xxxx|xxxxxx ++++++++++++++ + * | xxxx|xxxxxxx +++++++++++++ + * | xxxx|xxxxxxxx ++++++++++++ + * | xxxx|xxxxxxxxx +++++++++++ + * | xxxx|xxxxxxxxxx ++++++++++ + * | xxxx|xxxxxxxxxxx +++++++++ + * | xxxx|xxxxxxxxxxxx ++++++++ + * rxlow --------->xxxx|xxxxxxxxxxxxx +++++++ + * | | + * ------------|------------------------------> tx + * 0 | 127 + * search + * txlow + */ + + dev_dbg(dev, "txlow and txhigh at the same read delay.\n"); + backuppoint.rx =3D rxlow.rx + ((tmp * 3) / 4); + dev_dbg(dev, "Searching for Backup txlow on RX =3D %d\n", + backuppoint.rx); + backuppoint.read_delay =3D CQSPI_PHY_INIT_RD; + ret =3D cqspi_find_tx_low_ddr(f_pdata, mem, &backuppoint); + if (ret) + goto out; + dev_dbg(dev, "Backup txlow: RX: %d TX: %d RD: %d\n", + backuppoint.rx, backuppoint.tx, backuppoint.read_delay); + + if (backuppoint.tx < txlow.tx) { + txlow =3D backuppoint; + dev_dbg(dev, "Updating txlow with the one at RX =3D %d\n", + backuppoint.rx); + } + dev_dbg(dev, "Final txlow: RX: %d TX: %d RD: %d\n", txlow.rx, + txlow.tx, txlow.read_delay); + + /* Backup txhigh: Same RX as backup txlow, decrement from max */ + + /* + * rx + * 127 ^ + * | + * rxhigh --------->xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * fix rx | xxxxxxx ++++++++++++++++++ + * 3/4 b/w ------------------------------><-------> + * rxlow and | xxxxxxxxx +++++++++++|++++ + * rxhigh | xxxxxxxxxx ++++++++++|++++ + * | xxxxxxxxxxx +++++++++|++++ + * | xxxxxxxxxxxx ++++++++|++++ + * | xxxxxxxxxxxxx +++++++|++++ + * | xxxxxxxxxxxxxx ++++++|++++ + * | xxxxxxxxxxxxxxx +++++|++++ + * | xxxxxxxxxxxxxxxx ++++|++++ + * | xxxxxxxxxxxxxxxxx +++|++++ + * rxlow --------->xxxxxxxxxxxxxxxxxx ++|++++ + * | | + * ---------------------------------|---------> tx + * 0 | 127 + * search + * txhigh + */ + + dev_dbg(dev, "Searching for Backup txhigh on RX =3D %d\n", + backuppoint.rx); + backuppoint.read_delay =3D CQSPI_PHY_MAX_RD; + ret =3D cqspi_find_tx_high_ddr(f_pdata, mem, &backuppoint); + if (ret) + goto out; + dev_dbg(dev, "Backup txhigh: RX: %d TX: %d RD: %d\n", + backuppoint.rx, backuppoint.tx, backuppoint.read_delay); + + if (backuppoint.tx > txhigh.tx) { + txhigh =3D backuppoint; + dev_dbg(dev, + "Updating txhigh with the one at RX =3D %d\n", + backuppoint.rx); + } + dev_dbg(dev, "Final txhigh: RX: %d TX: %d RD: %d\n", txhigh.rx, + txhigh.tx, txhigh.read_delay); + } + + /* Corner points: Define and verify bottomleft and topright boundaries */ + + /* + * rx + * 127 ^ + * | topright + * | * + * rxhigh -----------xxxxx ++++++++++++++++++++ + * | xxxxxx +++++++++++++++++++ + * | xxxxxxx ++++++++++++++++++ + * | xxxxxxxx +++++++++++++++++ + * | xxxxxxxxx ++++++++++++++++ + * | xxxxxxxxxx +++++++++++++++ + * | xxxxxxxxxxx ++++++++++++++ + * | xxxxxxxxxxxx +++++++++++++ + * | xxxxxxxxxxxxx ++++++++++++ + * | xxxxxxxxxxxxxx +++++++++++ + * | xxxxxxxxxxxxxxx ++++++++++ + * | xxxxxxxxxxxxxxxx +++++++++ + * | xxxxxxxxxxxxxxxxx ++++++++ + * rxlow -----------xxxxxxxxxxxxxxxxxx +++++++ + * | * | + * | bottom|left | + * --------|----------------------------|---> tx + * 0 | | 127 + * | | + * txlow txhigh + * + * Verification: Test point 4 taps inside each corner, adjust + * read_delay =C2=B11 if needed to ensure valid corners for gap search. + */ + + bottomleft.tx =3D txlow.tx; + bottomleft.rx =3D rxlow.rx; + if (txlow.read_delay <=3D rxlow.read_delay) + bottomleft.read_delay =3D txlow.read_delay; + else + bottomleft.read_delay =3D rxlow.read_delay; + + /* Verify bottomleft: Test 4 taps inside, adjust read_delay if needed */ + backupcornerpoint =3D bottomleft; + backupcornerpoint.tx +=3D 4; + backupcornerpoint.rx +=3D 4; + ret =3D cqspi_phy_apply_setting(f_pdata, &backupcornerpoint); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret) { + backupcornerpoint.read_delay--; + ret =3D cqspi_phy_apply_setting(f_pdata, &backupcornerpoint); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + } + + /* TODO: if (ret) - handle case where corner cannot be verified */ + + if (!ret) + bottomleft.read_delay =3D backupcornerpoint.read_delay; + + topright.tx =3D txhigh.tx; + topright.rx =3D rxhigh.rx; + if (txhigh.read_delay >=3D rxhigh.read_delay) + topright.read_delay =3D txhigh.read_delay; + else + topright.read_delay =3D rxhigh.read_delay; + + /* Verify topright: Test 4 taps inside, adjust read_delay if needed */ + backupcornerpoint =3D topright; + backupcornerpoint.tx -=3D 4; + backupcornerpoint.rx -=3D 4; + ret =3D cqspi_phy_apply_setting(f_pdata, &backupcornerpoint); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret) { + backupcornerpoint.read_delay++; + ret =3D cqspi_phy_apply_setting(f_pdata, &backupcornerpoint); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + } + + /* TODO: if (ret) - handle case where corner cannot be verified */ + + if (!ret) + topright.read_delay =3D backupcornerpoint.read_delay; + + dev_dbg(dev, "topright: RX: %d TX: %d RD: %d\n", topright.rx, + topright.tx, topright.read_delay); + dev_dbg(dev, "bottomleft: RX: %d TX: %d RD: %d\n", bottomleft.rx, + bottomleft.tx, bottomleft.read_delay); + ret =3D cqspi_phy_find_gaplow_ddr(f_pdata, mem, &bottomleft, &topright, + &gaplow); + if (ret) + goto out; + dev_dbg(dev, "gaplow: RX: %d TX: %d RD: %d\n", gaplow.rx, gaplow.tx, + gaplow.read_delay); + + /* Final point selection: Handle single vs dual passing regions */ + + if (bottomleft.read_delay =3D=3D topright.read_delay) { + /* + * Single region: Use midpoint with temperature compensation. + * Gaplow approximates upper boundary of valid region. + * + * rx + * 127 ^ + * | gaplow (approx. topright) + * | | + * rxhigh -----------xxxxxxx| failing + * | xxxxxxx| region + * | xxxxxxx| <---------------> + * | xxxxxxx| +++++++++++++++++ + * | xxxxxxxxx ++++++++++++++++ + * | xxxxxxxxxx +++++++++++++++ + * | xxxxxxxxxxx ++++++++++++++ + * | xxxxxxxxxxxx +++++++++++++ + * | xxxxxxxxxxxxx ++++++++++++ + * | xxxxxxxxxxxxxx +++++++++++ + * | xxxxxxxxxxxxxxx ++++++++++ + * | xxxxxxxxxxxxxxxx +++++++++ + * | xxxxxxxxxxxxxxxxx ++++++++ + * rxlow -----------xxxxxxxxxxxxxxxxxx +++++++ + * | * | + * | bottom|left | + * --------|----------------------------|---> tx + * 0 | | 127 + * | | + * txlow txhigh + * (same read_delay) + * + * Temperature compensation: Valid region shifts with temp. + * Offset =3D region_size / (330 / (temp - 87.5=C2=B0C)) + * Factor 330 is empirically determined for this hardware. + */ + + dev_dbg(dev, + "bottomleft and topright at the same read delay.\n"); + + topright =3D gaplow; + searchpoint.read_delay =3D bottomleft.read_delay; + searchpoint.tx =3D + bottomleft.tx + ((topright.tx - bottomleft.tx) / 2); + searchpoint.rx =3D + bottomleft.rx + ((topright.rx - bottomleft.rx) / 2); + + ret =3D cqspi_get_temp(&tmp); + if (ret) { + /* Assume room temperature if sensor unavailable */ + dev_dbg(dev, + "Unable to get temperature. Assuming room temperature\n"); + tmp =3D CQSPI_PHY_DEFAULT_TEMP; + } + + if (tmp < CQSPI_PHY_MIN_TEMP || tmp > CQSPI_PHY_MAX_TEMP) { + dev_err(dev, + "Temperature outside operating range: %dC\n", + tmp); + ret =3D -EINVAL; + goto out; + } + + if (tmp =3D=3D CQSPI_PHY_MID_TEMP) + tmp++; /* Avoid divide-by-zero */ + dev_dbg(dev, "Temperature: %dC\n", tmp); + + /* Apply temperature offset: positive at high temp, negative at low */ + searchpoint.tx +=3D (topright.tx - bottomleft.tx) / + (330 / (tmp - CQSPI_PHY_MID_TEMP)); + searchpoint.rx +=3D (topright.rx - bottomleft.rx) / + (330 / (tmp - CQSPI_PHY_MID_TEMP)); + } else { + /* + * Dual regions: Gap separates two valid regions, choose larger. + * + * rx + * 127 ^ + * | topright + * | * + * rxhigh -----------xxxxx +++++++++++++++++++| + * | xxxxxx ++++++++| + * | xxxxxxx +++++++++++++++++| + * | xxxxxxxx ++++++++++++++++| + * | xxxxxxxxx +++++++++++++++| + * | xxxxxxxxxx ++++++++++++++| + * | failing | + * | region | + * | xxxxxxxxxxxxx +++++++++++| + * | xxxxxxxxxxxxxx ++++++++++| + * | xxxxxxxxxxxxxxx +++++++++| + * | xxxxxxxxxxxxxxxx ++++++++| + * | xxxxxxxxx +++++++| + * rxlow -----------xxxxxxxxxxxxxxxxxx ++++++| + * | * | + * | bottom|left | + * --------|----------------------------|---> tx + * 0 | | 127 + * | | + * txlow txhigh + * + * Strategy: Compare Manhattan distances from gap boundaries to + * corners. Choose corner furthest from gap (larger region). + * Apply 16-tap margin inward, scale RX proportionally. + */ + + ret =3D cqspi_phy_find_gaphigh_ddr(f_pdata, mem, &bottomleft, + &topright, &gaphigh); + if (ret) + goto out; + dev_dbg(dev, "gaphigh: RX: %d TX: %d RD: %d\n", gaphigh.rx, + gaphigh.tx, gaphigh.read_delay); + + /* Compare Manhattan distances: choose corner furthest from gap */ + if ((abs(gaplow.tx - bottomleft.tx) + + abs(gaplow.rx - bottomleft.rx)) < + (abs(gaphigh.tx - topright.tx) + + abs(gaphigh.rx - topright.rx))) { + /* Topright further: Use Region 2, 16 taps inward */ + searchpoint =3D topright; + searchpoint.tx -=3D 16; + searchpoint.rx -=3D (16 * (topright.rx - bottomleft.rx)) / + (topright.tx - bottomleft.tx); + } else { + /* Bottomleft further: Use Region 1, 16 taps inward */ + searchpoint =3D bottomleft; + searchpoint.tx +=3D 16; + searchpoint.rx +=3D (16 * (topright.rx - bottomleft.rx)) / + (topright.tx - bottomleft.tx); + } + } + + /* Apply and verify final tuning point */ + dev_dbg(dev, "Final tuning point: RX: %d TX: %d RD: %d\n", + searchpoint.rx, searchpoint.tx, searchpoint.read_delay); + ret =3D cqspi_phy_apply_setting(f_pdata, &searchpoint); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret) { + dev_err(dev, + "Failed to find pattern at final calibration point\n"); + ret =3D -EINVAL; + goto out; + } + + ret =3D 0; + f_pdata->phy_setting.read_delay =3D searchpoint.read_delay; + f_pdata->phy_setting.rx =3D searchpoint.rx; + f_pdata->phy_setting.tx =3D searchpoint.tx; +out: + if (ret) + f_pdata->use_phy =3D false; + + return ret; } =20 static int cqspi_phy_tuning_sdr(struct cqspi_flash_pdata *f_pdata, struct spi_mem *mem) { - /* Placeholder for SDR mode PHY tuning algorithm */ - return 0; + struct cqspi_st *cqspi =3D f_pdata->cqspi; + struct device *dev =3D &cqspi->pdev->dev; + struct phy_setting rxlow, rxhigh, first, second, final; + u8 window1 =3D 0; + u8 window2 =3D 0; + int ret; + + /* + * SDR tuning: 1D search for optimal RX delay (TX less critical). + * Find two consecutive windows, choose larger, use midpoint. + * + * rx + * 127 ^ + * | |-----window at----------| + * | |-----read_dealy =3D n+1---| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | rxlow(n+1) midpoint rxhigh(n+1) + * | + * | |---window at--------| + * | |---read_dealy =3D n---| + * | |xxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxx| + * | rxlow(n) midpoint rxhigh(n) + * | + * -----------------------------------------> tx + * 0 127 + * read_delay=3Dn read_dealy=3Dn+1 + */ + + f_pdata->use_phy =3D true; + cqspi_phy_reset_setting(&rxlow); + cqspi_phy_reset_setting(&rxhigh); + cqspi_phy_reset_setting(&first); + + /* First window: Find rxlow by incrementing read_delay from 0 */ + + /* + * rx + * 127 ^ + * | |xxxxxxxxxxxxxxxxxxxx| + * search | |xxxxxxxxxxxxxxxxxxxx| + * rxlow | |xxxxxxxxxxxxxxxxxxxx| + * increasing | |xxxxxxxxxxxxxxxxxxxx| + * --------->|xxxxxxxxxxxxxxxxxxxx| + * read_delay | |xxxxxxxxxxxxxxxxxxx| + * until found | |xxxxxxxxxxxxxxxxxxx| + * | rxlow + * -----------------------------------------> tx + * 0 tx fixed at 127 + */ + + do { + ret =3D cqspi_find_rx_low_sdr(f_pdata, mem, &rxlow); + + if (ret) + rxlow.read_delay++; + } while (ret && rxlow.read_delay <=3D CQSPI_PHY_MAX_RD); + + /* Find rxhigh: Decrement from RX=3D127 at same read_delay */ + + /* + * rx + * 127 ^ search rxhigh + * | (decrement from + * | 127 until found) + * | | + * | | + * | v + * | |------------------------| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | rxlow rxhigh + * -----------------------------------------> tx + * 0 tx fixed at 127 + */ + + rxhigh.read_delay =3D rxlow.read_delay; + ret =3D cqspi_find_rx_high_sdr(f_pdata, mem, &rxhigh, rxlow.rx); + if (ret) + goto out; + + /* Calculate first window midpoint for max margin */ + + /* + * rx + * 127 ^ + * | |--------window1---------| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxx * xxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | rxlow ^ rxhigh + * ----------------------|------------------> tx + * 0 | tx fixed at 127 + * window1/2 + */ + + first.read_delay =3D rxlow.read_delay; + window1 =3D rxhigh.rx - rxlow.rx; + first.rx =3D rxlow.rx + (window1 / 2); + + dev_dbg(dev, "First tuning point: RX: %d TX: %d RD: %d\n", first.rx, + first.tx, first.read_delay); + ret =3D cqspi_phy_apply_setting(f_pdata, &first); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret || first.read_delay > CQSPI_PHY_MAX_RD) + goto out; + + /* Second window: Search at read_delay+1, may differ in size */ + + /* + * rx + * 127 ^ + * | |-------| + * | |xxxxxxx| + * | |xxxxxxx| + * | |xxxxxxx| + * | |xxxxxxx| + * | |xxxxxxx| + * | rxlow rxhigh + * -----------------------------------------> tx + * 0 + * read_delay =3D n (smaller window) + * + * rx + * 127 ^ + * | |-----------------| + * | |xxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxx| + * | rxlow rxhigh + * -----------------------------------------> tx + * 0 + * read_delay =3D n+! (larger window - better) + */ + + cqspi_phy_reset_setting(&rxlow); + cqspi_phy_reset_setting(&rxhigh); + cqspi_phy_reset_setting(&second); + + rxlow.read_delay =3D first.read_delay + 1; + if (rxlow.read_delay > CQSPI_PHY_MAX_RD) + goto compare; + + ret =3D cqspi_find_rx_low_sdr(f_pdata, mem, &rxlow); + if (ret) + goto compare; + + rxhigh.read_delay =3D rxlow.read_delay; + ret =3D cqspi_find_rx_high_sdr(f_pdata, mem, &rxhigh, rxlow.rx); + if (ret) + goto compare; + + /* Calculate second window midpoint */ + + /* + * rx + * 127 ^ + * | |--------window2---------| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxx * xxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | |xxxxxxxxxxxxxxxxxxxxxxxx| + * | rxlow ^ rxhigh + * ----------------------|------------------> tx + * 0 | tx fixed at 127 + * window1/2 + * read_delay =3D n+1 + */ + + window2 =3D rxhigh.rx - rxlow.rx; + second.rx =3D rxlow.rx + (window2 / 2); + second.read_delay =3D rxlow.read_delay; + + dev_dbg(dev, "Second tuning point: RX: %d TX: %d RD: %d\n", second.rx, + second.tx, second.read_delay); + ret =3D cqspi_phy_apply_setting(f_pdata, &second); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret || second.read_delay > CQSPI_PHY_MAX_RD) + window2 =3D 0; + + /* Window comparison: Choose larger window for better margin */ + +compare: + cqspi_phy_reset_setting(&final); + if (window2 > window1) { + final.rx =3D second.rx; + final.read_delay =3D second.read_delay; + } else { + final.rx =3D first.rx; + final.read_delay =3D first.read_delay; + } + + /* Apply and verify final tuning point */ + + dev_dbg(dev, "Final tuning point: RX: %d TX: %d RD: %d\n", final.rx, + final.tx, final.read_delay); + ret =3D cqspi_phy_apply_setting(f_pdata, &final); + if (!ret) + ret =3D cqspi_phy_check_pattern(f_pdata, mem); + + if (ret) { + ret =3D -EINVAL; + goto out; + } + + f_pdata->phy_setting.read_delay =3D final.read_delay; + f_pdata->phy_setting.rx =3D final.rx; + f_pdata->phy_setting.tx =3D final.tx; + +out: + if (ret) + f_pdata->use_phy =3D false; + + return ret; } =20 static int cqspi_am654_ospi_execute_tuning(struct spi_mem *mem, --=20 2.34.1 From nobody Sun Feb 8 11:40:22 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013051.outbound.protection.outlook.com [40.93.201.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCA8C29617D; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:18:00.0618 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6743ed80-9efe-4ed3-79d4-08de52ae8e7f X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR10MB5726 Content-Type: text/plain; charset="utf-8" PHY tuning calibrates timing delays for specific read and write commands at high frequency. Using this frequency for uncalibrated operations causes timing violations. Apply PHY frequency only to operations that were tuned. All other operations use the lower non-PHY frequency. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 33 ++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 930ea094f6d8..3669936ae4e1 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1532,13 +1532,44 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata = *f_pdata, return cqspi_indirect_read_execute(f_pdata, buf, from, len); } =20 +/* + * Check if operation exactly matches the tuned operations. + */ +static bool cqspi_op_matches_tuned(const struct spi_mem_op *op, + const struct spi_mem_op *tuned_op) +{ + return op->cmd.opcode =3D=3D tuned_op->cmd.opcode && + op->cmd.buswidth =3D=3D tuned_op->cmd.buswidth && + op->cmd.dtr =3D=3D tuned_op->cmd.dtr && + op->addr.buswidth =3D=3D tuned_op->addr.buswidth && + op->addr.dtr =3D=3D tuned_op->addr.dtr && + op->data.buswidth =3D=3D tuned_op->data.buswidth && + op->data.dtr =3D=3D tuned_op->data.dtr; +} + static int cqspi_mem_process(struct spi_mem *mem, const struct spi_mem_op = *op) { struct cqspi_st *cqspi =3D spi_controller_get_devdata(mem->spi->controlle= r); struct cqspi_flash_pdata *f_pdata; =20 f_pdata =3D &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)]; - cqspi_configure(f_pdata, op->max_freq); + + /* + * PHY tuning allows high-frequency operation only for calibrated + * commands. Uncalibrated operations use safe non-PHY frequency to + * avoid timing violations. + */ + if (cqspi->ddata->execute_tuning && f_pdata->use_phy && + (cqspi_op_matches_tuned(op, &f_pdata->phy_read_op) || + cqspi_op_matches_tuned(op, &f_pdata->phy_write_op))) { + cqspi_configure(f_pdata, op->max_freq); + } else if (cqspi->ddata->execute_tuning) { + /* Use safe frequency for untuned operations */ + cqspi_configure(f_pdata, f_pdata->non_phy_clk_rate); + } else { + /* No tuning support, always use requested frequency */ + cqspi_configure(f_pdata, op->max_freq); + } =20 if (op->data.dir =3D=3D SPI_MEM_DATA_IN && op->data.buf.in) { /* --=20 2.34.1 From nobody Sun Feb 8 11:40:22 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010034.outbound.protection.outlook.com [52.101.85.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FA3B27B353; Tue, 13 Jan 2026 14:18:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 14:18:09.9155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca6933dd-b4f1-4f64-1e84-08de52ae9460 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR10MB7650 Content-Type: text/plain; charset="utf-8" Enable PHY mode for direct memory-mapped reads and large indirect writes (>=3D 1KB) to leverage calibrated RX/TX timing delays for high-frequency operations. PHY mode requires 16-byte alignment. For reads, split unaligned transfers into non-PHY head, PHY-enabled middle, and non-PHY tail. Small transfers use CPU copy to avoid DMA setup overhead. PHY mode requires one less dummy cycle due to improved timing margins. Adjust dummy cycles when toggling PHY mode. Add optimized I/O copy for 8D-8D-8D operations using 4-byte bulk reads for 32-bit platform compatibility. Signed-off-by: Santhosh Kumar K --- drivers/spi/spi-cadence-quadspi.c | 177 ++++++++++++++++++++++++++++-- 1 file changed, 167 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-qu= adspi.c index 3669936ae4e1..8ed6b2f5b573 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -565,6 +565,59 @@ static void cqspi_readdata_capture(struct cqspi_st *cq= spi, const bool bypass, writel(reg, reg_base + CQSPI_REG_READCAPTURE); } =20 +static void cqspi_phy_enable(struct cqspi_flash_pdata *f_pdata, bool enabl= e) +{ + struct cqspi_st *cqspi =3D f_pdata->cqspi; + void __iomem *reg_base =3D cqspi->iobase; + u32 reg; + u8 dummy; + + if (enable) { + cqspi_readdata_capture(cqspi, true, f_pdata->has_dqs, + f_pdata->phy_setting.read_delay); + + reg =3D readl(reg_base + CQSPI_REG_CONFIG); + reg |=3D CQSPI_REG_CONFIG_PHY_EN | CQSPI_REG_CONFIG_PHY_PIPELINE; + writel(reg, reg_base + CQSPI_REG_CONFIG); + + /* PHY mode requires one less dummy cycle */ + reg =3D readl(reg_base + CQSPI_REG_RD_INSTR); + dummy =3D FIELD_GET(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + reg); + dummy--; + reg &=3D ~(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB); + reg |=3D FIELD_PREP(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + dummy); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); + } else { + cqspi_readdata_capture(cqspi, !cqspi->rclk_en, false, + f_pdata->read_delay); + + reg =3D readl(reg_base + CQSPI_REG_CONFIG); + reg &=3D ~(CQSPI_REG_CONFIG_PHY_EN | + CQSPI_REG_CONFIG_PHY_PIPELINE); + writel(reg, reg_base + CQSPI_REG_CONFIG); + + /* Restore original dummy cycle count */ + reg =3D readl(reg_base + CQSPI_REG_RD_INSTR); + dummy =3D FIELD_GET(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + reg); + dummy++; + reg &=3D ~(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB); + reg |=3D FIELD_PREP(CQSPI_REG_RD_INSTR_DUMMY_MASK + << CQSPI_REG_RD_INSTR_DUMMY_LSB, + dummy); + writel(reg, reg_base + CQSPI_REG_RD_INSTR); + } + + cqspi_wait_idle(cqspi); +} + static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) { void __iomem *reg_base =3D cqspi->iobase; @@ -1192,6 +1245,7 @@ static int cqspi_indirect_write_execute(struct cqspi_= flash_pdata *f_pdata, void __iomem *reg_base =3D cqspi->iobase; unsigned int remaining =3D n_tx; unsigned int write_bytes; + bool use_phy_write; int ret; =20 if (!refcount_read(&cqspi->refcount)) @@ -1227,6 +1281,12 @@ static int cqspi_indirect_write_execute(struct cqspi= _flash_pdata *f_pdata, if (cqspi->apb_ahb_hazard) readl(reg_base + CQSPI_REG_INDIRECTWR); =20 + /* Use PHY only for large writes where setup overhead is amortized */ + use_phy_write =3D n_tx >=3D SZ_1K && f_pdata->use_phy; + + if (use_phy_write) + cqspi_phy_enable(f_pdata, true); + while (remaining > 0) { size_t write_words, mod_bytes; =20 @@ -1267,6 +1327,9 @@ static int cqspi_indirect_write_execute(struct cqspi_= flash_pdata *f_pdata, goto failwr; } =20 + if (use_phy_write) + cqspi_phy_enable(f_pdata, false); + /* Disable interrupt. */ writel(0, reg_base + CQSPI_REG_IRQMASK); =20 @@ -1278,6 +1341,9 @@ static int cqspi_indirect_write_execute(struct cqspi_= flash_pdata *f_pdata, return 0; =20 failwr: + if (use_phy_write) + cqspi_phy_enable(f_pdata, false); + /* Disable interrupt. */ writel(0, reg_base + CQSPI_REG_IRQMASK); =20 @@ -1448,8 +1514,17 @@ static void cqspi_rx_dma_callback(void *param) complete(&cqspi->rx_dma_complete); } =20 -static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, - u_char *buf, loff_t from, size_t len) +static bool cqspi_use_phy(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op) +{ + if (!f_pdata->use_phy || op->data.nbytes < 16) + return false; + + return op->max_freq > f_pdata->non_phy_clk_rate; +} + +static int cqspi_direct_read_dma(struct cqspi_flash_pdata *f_pdata, u_char= *buf, + loff_t from, size_t len) { struct cqspi_st *cqspi =3D f_pdata->cqspi; struct device *dev =3D &cqspi->pdev->dev; @@ -1461,19 +1536,14 @@ static int cqspi_direct_read_execute(struct cqspi_f= lash_pdata *f_pdata, dma_addr_t dma_dst; struct device *ddev; =20 - if (!cqspi->rx_chan || !virt_addr_valid(buf)) { - memcpy_fromio(buf, cqspi->ahb_base + from, len); - return 0; - } - ddev =3D cqspi->rx_chan->device->dev; dma_dst =3D dma_map_single(ddev, buf, len, DMA_FROM_DEVICE); if (dma_mapping_error(ddev, dma_dst)) { dev_err(dev, "dma mapping failed\n"); return -ENOMEM; } - tx =3D dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, - len, flags); + tx =3D dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, len, + flags); if (!tx) { dev_err(dev, "device_prep_dma_memcpy error\n"); ret =3D -EIO; @@ -1507,6 +1577,93 @@ static int cqspi_direct_read_execute(struct cqspi_fl= ash_pdata *f_pdata, return ret; } =20 +static void cqspi_memcpy_fromio(const struct spi_mem_op *op, void *to, + const void __iomem *from, size_t count) +{ + if (op->data.buswidth =3D=3D 8 && op->data.dtr) { + unsigned long from_addr =3D (unsigned long)from; + + /* Handle unaligned start with 2-byte read */ + if (count && !IS_ALIGNED(from_addr, 4)) { + *(u16 *)to =3D __raw_readw(from); + from +=3D 2; + to +=3D 2; + count -=3D 2; + } + + /* Use 4-byte reads for aligned bulk (no readq for 32-bit) */ + if (count >=3D 4) { + size_t len =3D round_down(count, 4); + + memcpy_fromio(to, from, len); + from +=3D len; + to +=3D len; + count -=3D len; + } + + /* Handle remaining 2 bytes */ + if (count) + *(u16 *)to =3D __raw_readw(from); + + return; + } + + memcpy_fromio(to, from, count); +} + +static int cqspi_direct_read_execute(struct cqspi_flash_pdata *f_pdata, + const struct spi_mem_op *op) +{ + struct cqspi_st *cqspi =3D f_pdata->cqspi; + loff_t from =3D op->addr.val; + loff_t from_aligned, to_aligned; + size_t len =3D op->data.nbytes; + size_t len_aligned; + u_char *buf =3D op->data.buf.in; + int ret; + + if (!cqspi->rx_chan || !virt_addr_valid(buf) || len <=3D 16) { + cqspi_memcpy_fromio(op, buf, cqspi->ahb_base + from, len); + return 0; + } + + if (!cqspi_use_phy(f_pdata, op)) + return cqspi_direct_read_dma(f_pdata, buf, from, len); + + /* Split into unaligned head, aligned middle, unaligned tail */ + from_aligned =3D ALIGN(from, 16); + to_aligned =3D ALIGN_DOWN(from + len, 16); + len_aligned =3D to_aligned - from_aligned; + + if (from !=3D from_aligned) { + ret =3D cqspi_direct_read_dma(f_pdata, buf, from, + from_aligned - from); + if (ret) + return ret; + buf +=3D from_aligned - from; + } + + if (len_aligned) { + cqspi_phy_enable(f_pdata, true); + ret =3D cqspi_direct_read_dma(f_pdata, buf, from_aligned, + len_aligned); + cqspi_phy_enable(f_pdata, false); + if (ret) + return ret; + buf +=3D len_aligned; + } + + if (to_aligned !=3D (from + len)) { + ret =3D cqspi_direct_read_dma(f_pdata, buf, to_aligned, + (from + len) - to_aligned); + if (ret) + return ret; + buf +=3D (from + len) - to_aligned; + } + + return 0; +} + static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, const struct spi_mem_op *op) { @@ -1523,7 +1680,7 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f= _pdata, return ret; =20 if (cqspi->use_direct_mode && ((from + len) <=3D cqspi->ahb_size)) - return cqspi_direct_read_execute(f_pdata, buf, from, len); + return cqspi_direct_read_execute(f_pdata, op); =20 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && virt_addr_valid(buf) && ((dma_align & CQSPI_DMA_UNALIGN) =3D=3D 0)) --=20 2.34.1