From nobody Sun Feb 8 16:34:15 2026 Received: from cvsmtppost04.nm.naver.com (cvsmtppost04.nm.naver.com [114.111.35.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFDE93904F5 for ; Tue, 13 Jan 2026 13:48:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.111.35.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768312135; cv=none; b=eXIjT5tG9/PZfu0cwEznhPESEJJCCyz2jtim36CnAXiPk9VCBlGA1IklcEP6JrqWbu37iUlkwYLKdAA8x3HNpa9h4K/Gj5x7m+qS0x59H/ftQsUQGd02mTiRQXQmTnYko4hQYR15pe8QG6sMUVaMl5grL/r4XAsdpQXnpltmLQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768312135; c=relaxed/simple; bh=ddDmhaouarvXwMVBvnX89f4wLPTRj5iUM6KsiUA/Lp0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mVG1a4Jsv+70blZVdHBtguSYZ1vCITw44ELFX2HPbAiisZMGZEicdSwm9G8eiSiGQQh5xD+1KsnrfAVS1X8q9klYQeOHVetiEKOwg/lNQBD4+wB2cCBWXpKt+BxqmzY/UcaySYdtD3IJA5WnquBmsY0J+cLH6ps60LLsSGWK4jM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=naver.com; spf=pass smtp.mailfrom=naver.com; dkim=pass (2048-bit key) header.d=naver.com header.i=@naver.com header.b=TaQpIloZ; arc=none smtp.client-ip=114.111.35.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=naver.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=naver.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=naver.com header.i=@naver.com header.b="TaQpIloZ" Received: from cvsendbo004.nm ([10.112.24.36]) by cvsmtppost04.nm.naver.com with ESMTP id HHW3UDQ0QqeOoinYjjxkaQ for ; Tue, 13 Jan 2026 13:38:45 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=naver.com; s=s20171208; t=1768311525; bh=ddDmhaouarvXwMVBvnX89f4wLPTRj5iUM6KsiUA/Lp0=; h=From:To:Subject:Date:Message-ID:From:Subject:Feedback-ID: X-Works-Security; b=TaQpIloZTkZ5iDFX8+Qc6YhdtlNKkfTbW0N79tJHulae3yqZ7vr8a33BmoTNA5Q/J phBmysf6APqgHjmTCBDmLq9BwzaJpp8xqTkK1eqFW1Prn0k/bka63GSIyIp48dt1cH OGDirMoA+Ae9OmjYPuWbujdvn7B0Z6ncesey2wFxxJxflSQfeMs6Th/MCCGUObZuAw q6iN4kjFsHUQ+QINiz5IJlWkWY7oD4fADRPn3yA8f8LHPa2XuapT16nXoEw2MyMfeo DQnDPRVxSDxejaqlnZrm87CGHUQtdKXI84cRUaxavcOWaVVt88P81SnxINrOxJySu0 hCQZQYAwDkBZg== X-Session-ID: jPQjYJIoTmusI7Jqqh6YuA X-Works-Send-Opt: 6/Y9jAJYjHmwKo2qKqJYFquqFNwkx0eFjAJYKg== X-Works-Smtp-Source: fqbXKo2rFqJZ+Hm9Koul+6E= Received: from JMW-Ubuntu.. ([14.38.141.199]) by cvnsmtp008.nm.naver.com with ESMTP id jPQjYJIoTmusI7Jqqh6YuA for (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Tue, 13 Jan 2026 13:38:45 -0000 From: Minu Jin To: gregkh@linuxfoundation.org Cc: ovidiu.panait.oss@gmail.com, gshahrouzi@gmail.com, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, Minu Jin Subject: [PATCH 1/2] staging: axis-fifo: introduce helper functions for register access Date: Tue, 13 Jan 2026 22:38:30 +0900 Message-ID: <20260113133831.3422480-2-s9430939@naver.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260113133831.3422480-1-s9430939@naver.com> References: <20260113133831.3422480-1-s9430939@naver.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch introduces axis_fifo_read_reg(), axis_fifo_write_reg() to wrap raw ioread32, iowrite32 calls. Using these helper functions improves code readability and provides a cleaner abstraction for hardware register access. All existing single register I/O calls updated to use these new helpers. This refactoring also ensures a consistent access pattern and makes future maintenance easier. Signed-off-by: Minu Jin --- drivers/staging/axis-fifo/axis-fifo.c | 45 ++++++++++++++++----------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-f= ifo/axis-fifo.c index 509d620d6ce7..525156583c4a 100644 --- a/drivers/staging/axis-fifo/axis-fifo.c +++ b/drivers/staging/axis-fifo/axis-fifo.c @@ -145,16 +145,26 @@ struct axis_fifo_debug_reg { * ---------------------------- */ =20 +static inline u32 axis_fifo_read_reg(struct axis_fifo *fifo, int offset) +{ + return ioread32(fifo->base_addr + offset); +} + +static inline void axis_fifo_write_reg(struct axis_fifo *fifo, int offset,= u32 val) +{ + iowrite32(val, fifo->base_addr + offset); +} + static void reset_ip_core(struct axis_fifo *fifo) { - iowrite32(XLLF_SRR_RESET_MASK, fifo->base_addr + XLLF_SRR_OFFSET); - iowrite32(XLLF_TDFR_RESET_MASK, fifo->base_addr + XLLF_TDFR_OFFSET); - iowrite32(XLLF_RDFR_RESET_MASK, fifo->base_addr + XLLF_RDFR_OFFSET); - iowrite32(XLLF_INT_TC_MASK | XLLF_INT_RC_MASK | XLLF_INT_RPURE_MASK | + axis_fifo_write_reg(fifo, XLLF_SRR_OFFSET, XLLF_SRR_RESET_MASK); + axis_fifo_write_reg(fifo, XLLF_TDFR_OFFSET, XLLF_TDFR_RESET_MASK); + axis_fifo_write_reg(fifo, XLLF_RDFR_OFFSET, XLLF_RDFR_RESET_MASK); + axis_fifo_write_reg(fifo, XLLF_IER_OFFSET, XLLF_INT_TC_MASK | + XLLF_INT_RC_MASK | XLLF_INT_RPURE_MASK | XLLF_INT_RPORE_MASK | XLLF_INT_RPUE_MASK | - XLLF_INT_TPOE_MASK | XLLF_INT_TSE_MASK, - fifo->base_addr + XLLF_IER_OFFSET); - iowrite32(XLLF_INT_CLEAR_ALL, fifo->base_addr + XLLF_ISR_OFFSET); + XLLF_INT_TPOE_MASK | XLLF_INT_TSE_MASK); + axis_fifo_write_reg(fifo, XLLF_ISR_OFFSET, XLLF_INT_CLEAR_ALL); } =20 /** @@ -192,7 +202,7 @@ static ssize_t axis_fifo_read(struct file *f, char __us= er *buf, if (!mutex_trylock(&fifo->read_lock)) return -EAGAIN; =20 - if (!ioread32(fifo->base_addr + XLLF_RDFO_OFFSET)) { + if (!axis_fifo_read_reg(fifo, XLLF_RDFO_OFFSET)) { ret =3D -EAGAIN; goto end_unlock; } @@ -203,7 +213,7 @@ static ssize_t axis_fifo_read(struct file *f, char __us= er *buf, */ mutex_lock(&fifo->read_lock); ret =3D wait_event_interruptible_timeout(fifo->read_queue, - ioread32(fifo->base_addr + XLLF_RDFO_OFFSET), + axis_fifo_read_reg(fifo, XLLF_RDFO_OFFSET), read_timeout); =20 if (ret <=3D 0) { @@ -218,7 +228,7 @@ static ssize_t axis_fifo_read(struct file *f, char __us= er *buf, } } =20 - bytes_available =3D ioread32(fifo->base_addr + XLLF_RLR_OFFSET); + bytes_available =3D axis_fifo_read_reg(fifo, XLLF_RLR_OFFSET); words_available =3D bytes_available / sizeof(u32); if (!bytes_available) { dev_err(fifo->dt_device, "received a packet of length 0\n"); @@ -334,8 +344,7 @@ static ssize_t axis_fifo_write(struct file *f, const ch= ar __user *buf, if (!mutex_trylock(&fifo->write_lock)) return -EAGAIN; =20 - if (words_to_write > ioread32(fifo->base_addr + - XLLF_TDFV_OFFSET)) { + if (words_to_write > axis_fifo_read_reg(fifo, XLLF_TDFV_OFFSET)) { ret =3D -EAGAIN; goto end_unlock; } @@ -347,7 +356,7 @@ static ssize_t axis_fifo_write(struct file *f, const ch= ar __user *buf, */ mutex_lock(&fifo->write_lock); ret =3D wait_event_interruptible_timeout(fifo->write_queue, - ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) + axis_fifo_read_reg(fifo, XLLF_TDFV_OFFSET) >=3D words_to_write, write_timeout); =20 @@ -373,7 +382,7 @@ static ssize_t axis_fifo_write(struct file *f, const ch= ar __user *buf, iowrite32(txbuf[i], fifo->base_addr + XLLF_TDFD_OFFSET); =20 /* write packet size to fifo */ - iowrite32(len, fifo->base_addr + XLLF_TLR_OFFSET); + axis_fifo_write_reg(fifo, XLLF_TLR_OFFSET, len); =20 ret =3D len; kvfree(txbuf); @@ -388,8 +397,8 @@ static irqreturn_t axis_fifo_irq(int irq, void *dw) struct axis_fifo *fifo =3D dw; u32 isr, ier, intr; =20 - ier =3D ioread32(fifo->base_addr + XLLF_IER_OFFSET); - isr =3D ioread32(fifo->base_addr + XLLF_ISR_OFFSET); + ier =3D axis_fifo_read_reg(fifo, XLLF_IER_OFFSET); + isr =3D axis_fifo_read_reg(fifo, XLLF_ISR_OFFSET); intr =3D ier & isr; =20 if (intr & XLLF_INT_RC_MASK) @@ -414,7 +423,7 @@ static irqreturn_t axis_fifo_irq(int irq, void *dw) dev_err(fifo->dt_device, "transmit length mismatch error interrupt\n"); =20 - iowrite32(XLLF_INT_CLEAR_ALL, fifo->base_addr + XLLF_ISR_OFFSET); + axis_fifo_write_reg(fifo, XLLF_ISR_OFFSET, XLLF_INT_CLEAR_ALL); =20 return IRQ_HANDLED; } @@ -464,7 +473,7 @@ static int axis_fifo_debugfs_regs_show(struct seq_file = *m, void *p) struct axis_fifo *fifo =3D m->private; =20 for (reg =3D regs; reg->name; ++reg) { - u32 val =3D ioread32(fifo->base_addr + reg->offset); + u32 val =3D axis_fifo_read_reg(fifo, reg->offset); =20 seq_printf(m, "%*s: 0x%08x\n", AXIS_FIFO_DEBUG_REG_NAME_MAX_LEN, reg->name, val); --=20 2.43.0 From nobody Sun Feb 8 16:34:15 2026 Received: from cvsmtppost20.nm.naver.com (cvsmtppost20.nm.naver.com [114.111.35.236]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B896339280A for ; Tue, 13 Jan 2026 13:48:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.111.35.236 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768312137; cv=none; b=q49+R2PQNEfoCPR34MUsYtomGqZD3C0pKEKPHN501AM6S5Wx3v3cxPKR9vXBtYCLJ1pen0YTyR8OEvopbfgqoON2ndxJ5hcffM+fenj/Qo6+qPkc2Mqmgc176I7otgB2V9Nkzyo6vRttGDdk/fdV1orFX/qCYzWwd6jThAfmIc8= ARC-Message-Signature: i=1; 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([14.38.141.199]) by cvnsmtp008.nm.naver.com with ESMTP id wCFF+3gDR-CZX8m31Z4vCA for (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Tue, 13 Jan 2026 13:38:46 -0000 From: Minu Jin To: gregkh@linuxfoundation.org Cc: ovidiu.panait.oss@gmail.com, gshahrouzi@gmail.com, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org, Minu Jin Subject: [PATCH 2/2] staging: axis-fifo: Use bulk I/O accessors for data transfers Date: Tue, 13 Jan 2026 22:38:31 +0900 Message-ID: <20260113133831.3422480-3-s9430939@naver.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260113133831.3422480-1-s9430939@naver.com> References: <20260113133831.3422480-1-s9430939@naver.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace manual for loops with ioread32_rep/iowrite32_rep. Add axis_fifo_read_data() and axis_fifo_write_data() wrappers to encapsulate these block-transfer operations. No functional changes intended Signed-off-by: Minu Jin --- drivers/staging/axis-fifo/axis-fifo.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/staging/axis-fifo/axis-fifo.c b/drivers/staging/axis-f= ifo/axis-fifo.c index 525156583c4a..9663d2efd411 100644 --- a/drivers/staging/axis-fifo/axis-fifo.c +++ b/drivers/staging/axis-fifo/axis-fifo.c @@ -150,11 +150,21 @@ static inline u32 axis_fifo_read_reg(struct axis_fifo= *fifo, int offset) return ioread32(fifo->base_addr + offset); } =20 +static inline void axis_fifo_read_data(struct axis_fifo *fifo, void *buf, = int count) +{ + ioread32_rep(fifo->base_addr + XLLF_RDFD_OFFSET, buf, count); +} + static inline void axis_fifo_write_reg(struct axis_fifo *fifo, int offset,= u32 val) { iowrite32(val, fifo->base_addr + offset); } =20 +static inline void axis_fifo_write_data(struct axis_fifo *fifo, const void= *buf, int count) +{ + iowrite32_rep(fifo->base_addr + XLLF_TDFD_OFFSET, buf, count); +} + static void reset_ip_core(struct axis_fifo *fifo) { axis_fifo_write_reg(fifo, XLLF_SRR_OFFSET, XLLF_SRR_RESET_MASK); @@ -259,10 +269,8 @@ static ssize_t axis_fifo_read(struct file *f, char __u= ser *buf, while (words_available > 0) { copy =3D min(words_available, READ_BUF_SIZE); =20 - for (i =3D 0; i < copy; i++) { - tmp_buf[i] =3D ioread32(fifo->base_addr + - XLLF_RDFD_OFFSET); - } + axis_fifo_read_data(fifo, tmp_buf, copy); + words_available -=3D copy; =20 if (copy_to_user(buf + copied * sizeof(u32), tmp_buf, @@ -378,8 +386,7 @@ static ssize_t axis_fifo_write(struct file *f, const ch= ar __user *buf, goto end_unlock; } =20 - for (int i =3D 0; i < words_to_write; ++i) - iowrite32(txbuf[i], fifo->base_addr + XLLF_TDFD_OFFSET); + axis_fifo_write_data(fifo, txbuf, words_to_write); =20 /* write packet size to fifo */ axis_fifo_write_reg(fifo, XLLF_TLR_OFFSET, len); --=20 2.43.0