From nobody Tue Feb 10 11:13:09 2026 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69A5738F923 for ; Tue, 13 Jan 2026 12:53:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768308802; cv=none; b=aOZIDSoO/EJqhXa5w3lQ4kqaHqWjrO8ZvX2kxdkM1DpAX8uactBDYxlW6py681AZwF0E9vlywenM8czXnZ3KkdIdgje7pXCuJoU/FXwPAYXienDt8PPbzkvE6KeopAM5eyWv53zIHXMXFbDP/H128CtL6g2k6FYWlg0PtlkSOes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768308802; c=relaxed/simple; bh=BJHKSCr1cxM21LVV4FRlibkavTra9iuDs50eQLBusbk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bqoMgCKR5xUkYHTxxWybyaXyUONjPPN6jRzdcArPesu3APr2YIhjlYRZxmQdfgwSSUQXx8H2xJJYqf/YZ1wX9EO/PhKvXr1GDU0WRmvqZKXM2bQYtFMlh/+9+Zo3ao2ZI2guxPQf9Zlm7/SDVmY50wmN/hQv4HCff+UiD23w08Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=TsvRq+6q; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="TsvRq+6q" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-47d6a1f08bbso30905955e9.2 for ; Tue, 13 Jan 2026 04:53:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768308799; x=1768913599; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XmjdiHpcgU48p4SZ15MSIb4LpXv8J6V5sUNbWmqB/8I=; b=TsvRq+6qOO8RZ6/lwld0HidAMtEgPFfZKe4LhxNxoFsSyE1TYbyyPwxzOX/YW3tCqF UbBTw49xI7wdzZzf4+j0mus+IRxFsw4hy4MF+06AAvWCWcfoVL7WHhEDzs+EuhKbemJo xLBcIWHnYVO9glUo5D3kdxJk+gr6vIBn2u15lXtZyXNcr9JVzHY2Q52TzEttx1krTOmT C0Z1WdCbuJLKnedkrcX3cIU+0KpN5TJwgYAPsOzLcXSzbTprKfZtCF3ZDgvFU7qTcBnJ QYG1XH1mYJoVHzBVPF6XwMNUf1vlWie+JMn6oUvBXRFq+wAVm3u/wEzroq41wXDdUlfw rs5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768308799; x=1768913599; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=XmjdiHpcgU48p4SZ15MSIb4LpXv8J6V5sUNbWmqB/8I=; b=ss53iH8qkL2/dFMO0jCZATqq1DFKVd3v2ilfSO4KNl5NDQfMosA6YuFsp/oQkGMp9T +lWwEi+wS8pFG7aO+am7zDPXcugnRq9zZSNNt57mzTZ3lEeCa3+s3vW3oI6yJiplkAWp HCrybKp6+hvqSJhEIYAsriccUDn7c+5pk34/cZVWxrNYgM7Mi6FYqJf/xUfjKrS9ce4G 7WesvVv5ALcINb9ULVKFziqSX7+9hpWM15H+rF4e2qIJDKdKoGNjx2/+hfX3unSVe/sz 6VYcAO3Nea2zM8EFR/8/AgUrS4ynZEgpjaUMhzew7uJ/5J1zbF932yHiVbXWzOcXgozJ pSeQ== X-Forwarded-Encrypted: i=1; AJvYcCVQptH4GOVvh8ciH8wuMj7BzyFY589zMQLEGMwNlqV6yX60vfMziNvmLbMgBmxRZN43w7MUy200B7VO3K4=@vger.kernel.org X-Gm-Message-State: AOJu0YyIO4EgkNPbXYymjVCPhRj6IV08hOKNyK2zTpJkuZIywn6AXKzb wMGsmNVWjkuf5ZcLpkv1sa4StCfSKmoomRvKp3zKYKWmSwUK8LSsIxYbsWZYtQ== X-Gm-Gg: AY/fxX7nJphNHi+QQCKD6hl9jz+fNopHS1M4qjXsLPU1ebfRKjbQ3k5BoJ3xVQ/pAA5 oZMkUF5SKmce9vipbXf3/V2vP/siD4BCg8c7Ierd6zn8ubba3Lzkxl6krqp+WhceavguSu/MUTx uV1XHBrIIZk3p4dbpdqB/EDPyY3ZElR7Wkj4yTp8E7PVtURUtAIs1PwOjrQWPrVEttmfrwSx7Tc dRUmSlSJkSjaW7up2vBHvhQtup3M6lW1rIHwNasc2UnCYbzgPfciUBvq8fg/+0r0+Tx66bOH9CB MOoL+u3oQ9Oq2dCRpYOZVnI26lggngiY0to6Iirt/vuvVFmd738bNCzJ/c2NRffhCINQIkKkYJK fVSi684iMZQY15aUijQf4FruI3I6e0ozZO4t+7+R7UHB8nzJI6eNwh0MikJAy4mad0v3zGu9NPW yuhqyPh9sLtHs1zre0wAKgKr2Yy+hQ X-Google-Smtp-Source: AGHT+IEbp6d2tVBHhgEBtCZ/Co7ID0xGMeGJvIcgxk7z7WpLK0gkB0XoRrHE6BtcliG3xv+Ye4uJUA== X-Received: by 2002:a05:600c:a48:b0:47a:829a:ebb with SMTP id 5b1f17b1804b1-47d84b36a2amr228341215e9.19.1768308798714; Tue, 13 Jan 2026 04:53:18 -0800 (PST) Received: from biju.lan ([2a00:23c4:a758:8a01:6e35:f12b:dc2b:8e25]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d7f4184cbsm423744265e9.6.2026.01.13.04.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jan 2026 04:53:18 -0800 (PST) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , Fabrizio Castro , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 2/2] irqchip/renesas-rzv2h: Add suspend/resume support Date: Tue, 13 Jan 2026 12:53:12 +0000 Message-ID: <20260113125315.359967-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260113125315.359967-1-biju.das.jz@bp.renesas.com> References: <20260113125315.359967-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das On RZ/G3E using PSCI, s2ram powers down the SoC. Add suspend/resume callbacks to restore IRQ type for NMI, TINT and external IRQ interrupts. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzv2h.c | 60 +++++++++++++++++++++++++++-- 1 file changed, 57 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-rene= sas-rzv2h.c index 9b4565375e83..6fc9e96d3169 100644 --- a/drivers/irqchip/irq-renesas-rzv2h.c +++ b/drivers/irqchip/irq-renesas-rzv2h.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 /* DT "interrupts" indexes */ #define ICU_IRQ_START 1 @@ -89,6 +90,18 @@ #define ICU_RZG3E_TSSEL_MAX_VAL 0x8c #define ICU_RZV2H_TSSEL_MAX_VAL 0x55 =20 +/** + * struct rzv2h_irqc_reg_cache - registers cache (necessary for suspend/re= sume) + * @nitsr: ICU_NITSR register + * @iitsr: ICU_IITSR register + * @titsr: ICU_TITSR registers + */ +struct rzv2h_irqc_reg_cache { + u32 nitsr; + u32 iitsr; + u32 titsr[2]; +}; + /** * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info = structure. * @tssel_lut: TINT lookup table @@ -118,13 +131,15 @@ struct rzv2h_hw_info { * @fwspec: IRQ firmware specific data * @lock: Lock to serialize access to hardware registers * @info: Pointer to struct rzv2h_hw_info + * @cache: Registers cache for suspend/resume */ -struct rzv2h_icu_priv { +static struct rzv2h_icu_priv { void __iomem *base; struct irq_fwspec fwspec[ICU_NUM_IRQ]; raw_spinlock_t lock; const struct rzv2h_hw_info *info; -}; + struct rzv2h_irqc_reg_cache cache; +} *rzv2h_icu_data; =20 void rzv2h_icu_register_dma_req(struct platform_device *icu_dev, u8 dmac_i= ndex, u8 dmac_channel, u16 req_no) @@ -419,6 +434,44 @@ static int rzv2h_icu_set_type(struct irq_data *d, unsi= gned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 +static int rzv2h_irqc_irq_suspend(void *data) +{ + struct rzv2h_irqc_reg_cache *cache =3D &rzv2h_icu_data->cache; + void __iomem *base =3D rzv2h_icu_data->base; + + cache->nitsr =3D readl_relaxed(base + ICU_NITSR); + cache->iitsr =3D readl_relaxed(base + ICU_IITSR); + for (u8 i =3D 0; i < 2; i++) + cache->titsr[i] =3D readl_relaxed(base + rzv2h_icu_data->info->t_offs + = ICU_TITSR(i)); + + return 0; +} + +static void rzv2h_irqc_irq_resume(void *data) +{ + struct rzv2h_irqc_reg_cache *cache =3D &rzv2h_icu_data->cache; + void __iomem *base =3D rzv2h_icu_data->base; + + /* + * Restore only interrupt type. TSSRx will be restored at the + * request of pin controller to avoid spurious interrupts due + * to invalid PIN states. + */ + for (u8 i =3D 0; i < 2; i++) + writel_relaxed(cache->titsr[i], base + rzv2h_icu_data->info->t_offs + IC= U_TITSR(i)); + writel_relaxed(cache->iitsr, base + ICU_IITSR); + writel_relaxed(cache->nitsr, base + ICU_NITSR); +} + +static const struct syscore_ops rzv2h_irqc_syscore_ops =3D { + .suspend =3D rzv2h_irqc_irq_suspend, + .resume =3D rzv2h_irqc_irq_resume, +}; + +static struct syscore rzv2h_irqc_syscore =3D { + .ops =3D &rzv2h_irqc_syscore_ops, +}; + static const struct irq_chip rzv2h_icu_chip =3D { .name =3D "rzv2h-icu", .irq_eoi =3D rzv2h_icu_eoi, @@ -502,7 +555,6 @@ static int rzv2h_icu_probe_common(struct platform_devic= e *pdev, struct device_no { struct irq_domain *irq_domain, *parent_domain; struct device_node *node =3D pdev->dev.of_node; - struct rzv2h_icu_priv *rzv2h_icu_data; struct reset_control *resetn; int ret; =20 @@ -560,6 +612,8 @@ static int rzv2h_icu_probe_common(struct platform_devic= e *pdev, struct device_no =20 rzv2h_icu_data->info =3D hw_info; =20 + register_syscore(&rzv2h_irqc_syscore); + /* * coccicheck complains about a missing put_device call before returning,= but it's a false * positive. We still need &pdev->dev after successfully returning from t= his function. --=20 2.43.0