From nobody Sun Feb 8 04:12:05 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBF943921FD for ; Tue, 13 Jan 2026 12:43:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768308200; cv=none; b=m7HJuS6zY+LYu2pPW1eGNN2qzF4elSDIgDzHKFmBn0bWd+pKkGCSHP40Frb7iByRBrxpv1V30N4anPk0dI/rXVXBziNxvhOxcimRVUQB4ddAoWhH7l9nHbsdMIdTD8Be8/ve9SwCcFQdKboJ8S1d5FkPp4oWYJT1yeuaWBHK3oI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768308200; c=relaxed/simple; bh=uVtGUyIWHyjoUK8L0H3DB3EX/vfhDouF0fbHo6dDlXk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bRaLKc/Sodgsh78ww17cWsEuRpnya5PKPzshHlfxI8/a4gFnLjjJsDW+9LWKBk7lGM9CP/JpEcw6DhWRu5N3d9uv7RV2o/vYOco1cHgMgkGtIAkQv0eBc1L8/kifj4wK6f12mW6jtruFoDJkVTEtYo7YzCXZVOZuH0Eg0eVnHKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lEefDc4Z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lEefDc4Z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D97B0C2BC86; Tue, 13 Jan 2026 12:43:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768308200; bh=uVtGUyIWHyjoUK8L0H3DB3EX/vfhDouF0fbHo6dDlXk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lEefDc4ZMT1K6SasPRUSeFTJQq1vgaHpTZQxxl61W2ga8c/33ual9q6qDBFuBXtJH 6JtbR3fTxvP6zAEzzC3J/qXE7SRbE5kHbTba/g7Hyu5omNjM1F9mvOc6ISNysLP2fr FwmgVjaWiKZ4RUm6l6GnUFvzLIa+kLI3+KVO6geE9TLx9LjKFcqNX4ddQLS3f70M+O x8xYQ9ChMzNTl4vO/RA+az/2Xg0zgygRp13k9oAOgyC+tlkXMZaw+SPj0+PYjl00uD Ar9o4vZtRCOvjQZJ+LHA6jY9Oigu95NFwiIEmjkpw8UsqJ8dcb6pZY8GxuCI+WbliG WefgteHpR+7jw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] riscv: word-at-a-time: improve find_zero() for Zbb Date: Tue, 13 Jan 2026 20:24:57 +0800 Message-ID: <20260113122457.27507-4-jszhang@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260113122457.27507-1-jszhang@kernel.org> References: <20260113122457.27507-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In commit f915a3e5b018 ("arm64: word-at-a-time: improve byte count calculations for LE"), Linus improved the find_zero() for arm64 LE. Do the same optimization as he did: "do __ffs() on the intermediate value that found whether there is a zero byte, before we've actually computed the final byte mask.", so that we share the similar improvements: "The difference between the old and the new implementation is that "count_zero()" ends up scheduling better because it is being done on a value that is available earlier (before the final mask). But more importantly, it can be implemented without the insane semantics of the standard bit finding helpers that have the off-by-one issue and have to special-case the zero mask situation." Before the patch: 0000000000000000 : 0: c909 beqz a0,12 <.L1> 2: 60051793 clz a5,a0 6: 03f00513 li a0,63 a: 8d1d sub a0,a0,a5 c: 2505 addiw a0,a0,1 e: 4035551b sraiw a0,a0,0x3 0000000000000012 <.L1>: 12: 8082 ret After the patch: 0000000000000000 : 0: 60151513 ctz a0,a0 4: 810d srli a0,a0,0x3 6: 8082 ret 7 instructions vs 3 instructions! As can be seen, on RV64 w/ Zbb, the new "find_zero()" ends up just "ctz" plus the shift right that then ends up being subsumed by the "add to final length". But I have no HW platform which supports Zbb, so I can't get the performance improvement numbers by the last patch, only built and tested the patch on QEMU. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/word-at-a-time.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/word-at-a-time.h b/arch/riscv/include/a= sm/word-at-a-time.h index ca3d30741ed1..8c5ac6a72f7f 100644 --- a/arch/riscv/include/asm/word-at-a-time.h +++ b/arch/riscv/include/asm/word-at-a-time.h @@ -38,6 +38,9 @@ static inline unsigned long prep_zero_mask(unsigned long = val, =20 static inline unsigned long create_zero_mask(unsigned long bits) { + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return bits; + bits =3D (bits - 1) & ~bits; return bits >> 7; } @@ -69,13 +72,19 @@ static inline long count_masked_bytes(long mask) static inline unsigned long find_zero(unsigned long mask) { if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) - return !mask ? 0 : ((__fls(mask) + 1) >> 3); + return __ffs(mask) >> 3; =20 return count_masked_bytes(mask); } =20 -/* The mask we created is directly usable as a bytemask */ -#define zero_bytemask(mask) (mask) +static inline unsigned long zero_bytemask(unsigned long bits) +{ + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) + return bits; + + bits =3D (bits - 1) & ~bits; + return bits >> 7; +} =20 #endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_= ZBB)) */ =20 --=20 2.51.0