From nobody Tue Feb 10 23:53:17 2026 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B62D346E74; Tue, 13 Jan 2026 11:23:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768303437; cv=none; b=YB8NqMwth27YspWj0mO5Z1JJ2c1vqVZyAY8El21/4/GGNqWfSmC9rTI+B3lgM3fzakw/QeL+qn0krMkVNCDaODXveAcC5rrUrbuIqwMod76aGlX+8dUPZMUBp4HV/TANPHVcAipHHn1dLZBKlCHfbQ1UeyqANK0lN6Mt93+1llc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768303437; c=relaxed/simple; bh=bn0GKbXiD0UoKuFr9Kz3PC4ggLMiHmzoM0G5awfjywU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=heF01/X7DAYJGXAiakIjjTmohBuEk3UCFgfG7Uia5dUmVk/mVQdRUi4Xx20mmEUi4DPLczy/asfGbadQu+zys8ssDCROp39KnVyBunoGDk42vdxSYwoiGarEaNkh+S7lc+4uqg+JEeo/LDM4MYE1JbkAdg+L4f+K9L+a44a9mQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=rx98Vh1v; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="rx98Vh1v" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 60DBNZHw82915421, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1768303415; bh=32hb2hvKcE41tTV/KRUvX4QRb1aZTEb05Nbz8JrpK78=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=rx98Vh1vARUSRjxyfqHVXqb6GYRZV4u2r9Q5Z/yiykbjz4C6ssa3yS4s8igJmT6E8 stzcyLfUGWP2+dcYR6mxY3awgiYMyV5qDofGccozfZ3J/j4JDhZbcKUgOCjR4U5akR 1ev5aLo1+MlIdJb8Z9YJZB1dewqTi4BRYUpTC1hUj7i453ucRrl2bG6iQu5hIWop14 2DgdMylFx63sBnmfo6TMeKzVt/NzQugGxAbwIZotOUVb4IO5k+L3FdNGry7oZOhMSU cm+hve6hr8LNBwVMKdWnCiVBkQ0wnPx/xp0arSLknRKcdHR1Sxf1fS2G3hIcG7FRdt 6bZjGMVKny+og== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.21/5.94) with ESMTPS id 60DBNZHw82915421 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 13 Jan 2026 19:23:35 +0800 Received: from RTKEXHMBS04.realtek.com.tw (10.21.1.54) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 13 Jan 2026 19:23:35 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS04.realtek.com.tw (10.21.1.54) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 13 Jan 2026 19:23:35 +0800 From: Yu-Chun Lin To: , , , , , , , CC: , , , , , , Subject: [PATCH v2 9/9] clk: realtek: Add RTD1625-ISO clock controller driver Date: Tue, 13 Jan 2026 19:23:32 +0800 Message-ID: <20260113112333.821-10-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260113112333.821-1-eleanor.lin@realtek.com> References: <20260113112333.821-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng-Yu Lee Add support for the ISO (Isolation) domain clock controller on the Realtek RTD1625 SoC. This controller manages clocks in the always-on power domain, ensuring essential services remain functional even when the main system power is gated. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v2: - Added missing Co-developed-by tag. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-rtd1625-iso.c | 153 ++++++++++++++++++++++++++ 2 files changed, 154 insertions(+) create mode 100644 drivers/clk/realtek/clk-rtd1625-iso.c diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 3cda1e600172..e90fce42a85e 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -11,3 +11,4 @@ clk-rtk-y +=3D reset.o =20 clk-rtk-$(CONFIG_RTK_CLK_PLL_MMC) +=3D clk-pll-mmc.o obj-$(CONFIG_COMMON_CLK_RTD1625) +=3D clk-rtd1625-crt.o +obj-$(CONFIG_COMMON_CLK_RTD1625) +=3D clk-rtd1625-iso.o diff --git a/drivers/clk/realtek/clk-rtd1625-iso.c b/drivers/clk/realtek/cl= k-rtd1625-iso.c new file mode 100644 index 000000000000..1aadd48d7bea --- /dev/null +++ b/drivers/clk/realtek/clk-rtd1625-iso.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2024 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include +#include +#include "clk-regmap-gate.h" + +#define RTD1625_ISO_CLK_MAX 19 +#define RTD1625_ISO_S_CLK_MAX 5 + +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_p4, 0, 0x08c, 0, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_p3, 0, 0x08c, 1, 0); +static CLK_REGMAP_GATE(clk_en_misc_cec0, "clk_en_misc", 0, 0x08c, 2, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbusrx_sys, 0, 0x08c, 3, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbustx_sys, 0, 0x08c, 4, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbus_sys, 0, 0x08c, 5, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_cbus_osc, 0, 0x08c, 6, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_i2c0, 0, 0x08c, 9, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_i2c1, 0, 0x08c, 10, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_etn_250m, 0, 0x08c, 11, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_etn_sys, 0, 0x08c, 12, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_drd, 0, 0x08c, 13, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_host, 0, 0x08c, 14, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb_u3_host, 0, 0x08c, 15, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_usb, 0, 0x08c, 16, 0); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_vtc, 0, 0x08c, 17, 0); +static CLK_REGMAP_GATE(clk_en_misc_vfd, "clk_en_misc", 0, 0x08c, 18, 0); + +static struct clk_regmap *rtd1625_clk_regmap_list[] =3D { + &clk_en_usb_p4.clkr, + &clk_en_usb_p3.clkr, + &clk_en_misc_cec0.clkr, + &clk_en_cbusrx_sys.clkr, + &clk_en_cbustx_sys.clkr, + &clk_en_cbus_sys.clkr, + &clk_en_cbus_osc.clkr, + &clk_en_i2c0.clkr, + &clk_en_i2c1.clkr, + &clk_en_etn_250m.clkr, + &clk_en_etn_sys.clkr, + &clk_en_usb_drd.clkr, + &clk_en_usb_host.clkr, + &clk_en_usb_u3_host.clkr, + &clk_en_usb.clkr, + &clk_en_vtc.clkr, + &clk_en_misc_vfd.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_iso_clk_data =3D { + .num =3D RTD1625_ISO_CLK_MAX, + .hws =3D { + [RTD1625_ISO_CLK_EN_USB_P4] =3D &__clk_regmap_gate_hw(&clk_en_usb_p= 4), + [RTD1625_ISO_CLK_EN_USB_P3] =3D &__clk_regmap_gate_hw(&clk_en_usb_p= 3), + [RTD1625_ISO_CLK_EN_MISC_CEC0] =3D &__clk_regmap_gate_hw(&clk_en_misc_= cec0), + [RTD1625_ISO_CLK_EN_CBUSRX_SYS] =3D &__clk_regmap_gate_hw(&clk_en_cbusr= x_sys), + [RTD1625_ISO_CLK_EN_CBUSTX_SYS] =3D &__clk_regmap_gate_hw(&clk_en_cbust= x_sys), + [RTD1625_ISO_CLK_EN_CBUS_SYS] =3D &__clk_regmap_gate_hw(&clk_en_cbus_= sys), + [RTD1625_ISO_CLK_EN_CBUS_OSC] =3D &__clk_regmap_gate_hw(&clk_en_cbus_= osc), + [RTD1625_ISO_CLK_EN_I2C0] =3D &__clk_regmap_gate_hw(&clk_en_i2c0), + [RTD1625_ISO_CLK_EN_I2C1] =3D &__clk_regmap_gate_hw(&clk_en_i2c1), + [RTD1625_ISO_CLK_EN_ETN_250M] =3D &__clk_regmap_gate_hw(&clk_en_etn_2= 50m), + [RTD1625_ISO_CLK_EN_ETN_SYS] =3D &__clk_regmap_gate_hw(&clk_en_etn_s= ys), + [RTD1625_ISO_CLK_EN_USB_DRD] =3D &__clk_regmap_gate_hw(&clk_en_usb_d= rd), + [RTD1625_ISO_CLK_EN_USB_HOST] =3D &__clk_regmap_gate_hw(&clk_en_usb_h= ost), + [RTD1625_ISO_CLK_EN_USB_U3_HOST] =3D &__clk_regmap_gate_hw(&clk_en_usb_u= 3_host), + [RTD1625_ISO_CLK_EN_USB] =3D &__clk_regmap_gate_hw(&clk_en_usb), + [RTD1625_ISO_CLK_EN_VTC] =3D &__clk_regmap_gate_hw(&clk_en_vtc), + [RTD1625_ISO_CLK_EN_MISC_VFD] =3D &__clk_regmap_gate_hw(&clk_en_misc_= vfd), + [RTD1625_ISO_CLK_MAX] =3D NULL, + }, +}; + +static struct rtk_reset_bank rtd1625_iso_reset_banks[] =3D { + {.ofs =3D 0x88,}, +}; + +static const struct rtk_clk_desc rtd1625_iso_desc =3D { + .clk_data =3D &rtd1625_iso_clk_data, + .clks =3D rtd1625_clk_regmap_list, + .num_clks =3D ARRAY_SIZE(rtd1625_clk_regmap_list), + .reset_banks =3D rtd1625_iso_reset_banks, + .num_reset_banks =3D ARRAY_SIZE(rtd1625_iso_reset_banks), +}; + +static CLK_REGMAP_GATE_NO_PARENT(clk_en_irda, 0, 0x314, 6, 1); +static CLK_REGMAP_GATE_NO_PARENT(clk_en_ur10, 0, 0x314, 8, 1); + +static struct clk_regmap *rtd1625_iso_s_clk_regmap_list[] =3D { + &clk_en_irda.clkr, + &clk_en_ur10.clkr, +}; + +static struct clk_hw_onecell_data rtd1625_iso_s_clk_data =3D { + .num =3D RTD1625_ISO_S_CLK_MAX, + .hws =3D { + [RTD1625_ISO_S_CLK_EN_IRDA] =3D &__clk_regmap_gate_hw(&clk_en_irda), + [RTD1625_ISO_S_CLK_EN_UR10] =3D &__clk_regmap_gate_hw(&clk_en_ur10), + [RTD1625_ISO_S_CLK_MAX] =3D NULL, + }, +}; + +static struct rtk_reset_bank rtd1625_iso_s_reset_banks[] =3D { + {.ofs =3D 0x310, .write_en =3D 1,}, +}; + +static const struct rtk_clk_desc rtd1625_iso_s_desc =3D { + .clk_data =3D &rtd1625_iso_s_clk_data, + .clks =3D rtd1625_iso_s_clk_regmap_list, + .num_clks =3D ARRAY_SIZE(rtd1625_iso_s_clk_regmap_list), + .reset_banks =3D rtd1625_iso_s_reset_banks, + .num_reset_banks =3D ARRAY_SIZE(rtd1625_iso_s_reset_banks), +}; + +static int rtd1625_iso_probe(struct platform_device *pdev) +{ + const struct rtk_clk_desc *desc; + + desc =3D of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + return rtk_clk_probe(pdev, desc); +} + +static const struct of_device_id rtd1625_iso_match[] =3D { + {.compatible =3D "realtek,rtd1625-iso-clk", .data =3D &rtd1625_iso_desc}, + {.compatible =3D "realtek,rtd1625-iso-s-clk", .data =3D &rtd1625_iso_s_de= sc}, + {/* sentinel */} +}; + +static struct platform_driver rtd1625_iso_driver =3D { + .probe =3D rtd1625_iso_probe, + .driver =3D { + .name =3D "rtk-rtd1625-iso-clk", + .of_match_table =3D rtd1625_iso_match, + }, +}; + +static int __init rtd1625_iso_init(void) +{ + return platform_driver_register(&rtd1625_iso_driver); +} +subsys_initcall(rtd1625_iso_init); + +MODULE_DESCRIPTION("Realtek RTD1625 ISO Controller Driver"); +MODULE_AUTHOR("Cheng-Yu Lee "); +MODULE_LICENSE("GPL"); --=20 2.34.1