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Tue, 13 Jan 2026 01:23:23 -0800 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v8 4/5] rust: pci: add config space read/write support Date: Tue, 13 Jan 2026 11:22:51 +0200 Message-ID: <20260113092253.220346-5-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260113092253.220346-1-zhiw@nvidia.com> References: <20260113092253.220346-1-zhiw@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|DS4PR12MB9562:EE_ X-MS-Office365-Filtering-Correlation-Id: 209f8fad-a206-4a06-4df3-08de52857447 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 09:23:46.6900 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 209f8fad-a206-4a06-4df3-08de52857447 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9562 Drivers might need to access PCI config space for querying capability structures and access the registers inside the structures. For Rust drivers need to access PCI config space, the Rust PCI abstraction needs to support it in a way that upholds Rust's safety principles. Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe accessors for PCI config space. The new type implements the `Io` trait to share offset validation and bound-checking logic with others. Cc: Alexandre Courbot Cc: Danilo Krummrich Cc: Joel Fernandes Signed-off-by: Zhi Wang --- rust/kernel/pci.rs | 43 ++++++++++++++- rust/kernel/pci/io.rs | 118 +++++++++++++++++++++++++++++++++++++++++- 2 files changed, 159 insertions(+), 2 deletions(-) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index 82e128431f08..f373413e8a84 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -40,7 +40,10 @@ ClassMask, Vendor, // }; -pub use self::io::Bar; +pub use self::io::{ + Bar, + ConfigSpace, // +}; pub use self::irq::{ IrqType, IrqTypes, @@ -331,6 +334,30 @@ fn as_raw(&self) -> *mut bindings::pci_dev { } } =20 +/// Represents the size of a PCI configuration space. +/// +/// PCI devices can have either a *normal* (legacy) configuration space of= 256 bytes, +/// or an *extended* configuration space of 4096 bytes as defined in the P= CI Express +/// specification. +#[repr(usize)] +pub enum ConfigSpaceSize { + /// 256-byte legacy PCI configuration space. + Normal =3D 256, + + /// 4096-byte PCIe extended configuration space. + Extended =3D 4096, +} + +impl ConfigSpaceSize { + /// Get the raw value of this enum. + #[inline(always)] + pub const fn as_raw(self) -> usize { + // CAST: PCI configuration space size is at most 4096 bytes, so th= e value always fits + // within `usize` without truncation or sign change. + self as usize + } +} + impl Device { /// Returns the PCI vendor ID as [`Vendor`]. /// @@ -427,6 +454,20 @@ pub fn pci_class(&self) -> Class { // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class }) } + + /// Returns the size of configuration space. + fn cfg_size(&self) -> Result { + // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`. + let size =3D unsafe { (*self.as_raw()).cfg_size }; + match size { + 256 =3D> Ok(ConfigSpaceSize::Normal), + 4096 =3D> Ok(ConfigSpaceSize::Extended), + _ =3D> { + debug_assert!(false); + Err(EINVAL) + } + } + } } =20 impl Device { diff --git a/rust/kernel/pci/io.rs b/rust/kernel/pci/io.rs index e3377397666e..c8741f0080ec 100644 --- a/rust/kernel/pci/io.rs +++ b/rust/kernel/pci/io.rs @@ -2,12 +2,19 @@ =20 //! PCI memory-mapped I/O infrastructure. =20 -use super::Device; +use super::{ + ConfigSpaceSize, + Device, // +}; use crate::{ bindings, device, devres::Devres, io::{ + define_read, + define_write, + IoBase, + IoKnownSize, Mmio, MmioRaw, // }, @@ -16,6 +23,101 @@ }; use core::ops::Deref; =20 +/// The PCI configuration space of a device. +/// +/// Provides typed read and write accessors for configuration registers +/// using the standard `pci_read_config_*` and `pci_write_config_*` helper= s. +/// +/// The generic const parameter `SIZE` can be used to indicate the +/// maximum size of the configuration space (e.g. 256 bytes for legacy, +/// 4096 bytes for extended config space). +pub struct ConfigSpace<'a, const SIZE: usize =3D { ConfigSpaceSize::Extend= ed as usize }> { + pub(crate) pdev: &'a Device, +} + +/// Internal helper macros used to invoke C PCI configuration space read f= unctions. +/// +/// This macro is intended to be used by higher-level PCI configuration sp= ace access macros +/// (define_read) and provides a unified expansion for infallible vs. fall= ible read semantics. It +/// emits a direct call into the corresponding C helper and performs the r= equired cast to the Rust +/// return type. +/// +/// # Parameters +/// +/// * `$c_fn` =E2=80=93 The C function performing the PCI configuration sp= ace write. +/// * `$self` =E2=80=93 The I/O backend object. +/// * `$ty` =E2=80=93 The type of the value to read. +/// * `$addr` =E2=80=93 The PCI configuration space offset to read. +/// +/// This macro does not perform any validation; all invariants must be uph= eld by the higher-level +/// abstraction invoking it. +macro_rules! call_config_read { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =3D> {{ + let mut val: $ty =3D 0; + // SAFETY: By the type invariant `$self.pdev` is a valid address. + // CAST: The offset is cast to `i32` because the C functions expec= t a 32-bit signed offset + // parameter. PCI configuration space size is at most 4096 bytes, = so the value always fits + // within `i32` without truncation or sign change. + // Return value from C function is ignored in infallible accessors. + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, &mut val) }; + val + }}; +} + +/// Internal helper macros used to invoke C PCI configuration space write = functions. +/// +/// This macro is intended to be used by higher-level PCI configuration sp= ace access macros +/// (define_write) and provides a unified expansion for infallible vs. fal= lible read semantics. It +/// emits a direct call into the corresponding C helper and performs the r= equired cast to the Rust +/// return type. +/// +/// # Parameters +/// +/// * `$c_fn` =E2=80=93 The C function performing the PCI configuration sp= ace write. +/// * `$self` =E2=80=93 The I/O backend object. +/// * `$ty` =E2=80=93 The type of the written value. +/// * `$addr` =E2=80=93 The configuration space offset to write. +/// * `$value` =E2=80=93 The value to write. +/// +/// This macro does not perform any validation; all invariants must be uph= eld by the higher-level +/// abstraction invoking it. +macro_rules! call_config_write { + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr= ) =3D> { + // SAFETY: By the type invariant `$self.pdev` is a valid address. + // CAST: The offset is cast to `i32` because the C functions expec= t a 32-bit signed offset + // parameter. PCI configuration space size is at most 4096 bytes, = so the value always fits + // within `i32` without truncation or sign change. + // Return value from C function is ignored in infallible accessors. + let _ret =3D unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr a= s i32, $value) }; + }; +} + +impl<'a, const SIZE: usize> IoBase for ConfigSpace<'a, SIZE> { + const MIN_SIZE: usize =3D SIZE; + + /// Returns the base address of the I/O region. It is always 0 for con= figuration space. + #[inline] + fn addr(&self) -> usize { + 0 + } + + /// Returns the maximum size of the configuration space. + #[inline] + fn maxsize(&self) -> usize { + self.pdev.cfg_size().map_or(0, |v| v as usize) + } +} + +impl<'a, const SIZE: usize> IoKnownSize for ConfigSpace<'a, SIZE> { + define_read!(infallible, read8, call_config_read(pci_read_config_byte)= -> u8); + define_read!(infallible, read16, call_config_read(pci_read_config_word= ) -> u16); + define_read!(infallible, read32, call_config_read(pci_read_config_dwor= d) -> u32); + + define_write!(infallible, write8, call_config_write(pci_write_config_b= yte) <- u8); + define_write!(infallible, write16, call_config_write(pci_write_config_= word) <- u16); + define_write!(infallible, write32, call_config_write(pci_write_config_= dword) <- u32); +} + /// A PCI BAR to perform I/O-Operations on. /// /// I/O backend assumes that the device is little-endian and will automati= cally @@ -144,4 +246,18 @@ pub fn iomap_region<'a>( ) -> impl PinInit, Error> + 'a { self.iomap_region_sized::<0>(bar, name) } + + /// Return an initialized config space object. + pub fn config_space<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } + + /// Return an initialized config space object. + pub fn config_space_extended<'a>( + &'a self, + ) -> Result> { + Ok(ConfigSpace { pdev: self }) + } } --=20 2.51.0