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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a3e3cc794asm196314945ad.70.2026.01.13.01.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jan 2026 01:20:39 -0800 (PST) From: Varadarajan Narayanan To: andersson@kernel.org, mathieu.poirier@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, quic_mmanikan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vignesh Viswanathan , Gokul Sriram Palanisamy , George Moussalem , Varadarajan Narayanan Subject: [PATCH v10 3/6] remoteproc: qcom: add hexagon based WCSS secure PIL driver Date: Tue, 13 Jan 2026 14:50:18 +0530 Message-Id: <20260113092021.1887980-4-varadarajan.narayanan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260113092021.1887980-1-varadarajan.narayanan@oss.qualcomm.com> References: <20260113092021.1887980-1-varadarajan.narayanan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: NUQggxtGXnWTJb34OS8_rhVsjzYWsgZ_ X-Proofpoint-GUID: NUQggxtGXnWTJb34OS8_rhVsjzYWsgZ_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEzMDA3OCBTYWx0ZWRfXxc42rveHRgkP kpDqCSZ/7xgFBT+mWzELNQuSv1VRqTX9wnDtBvZEG7N4TltruaU+Lg7SBuCRMfw9DbsqQ/4GiYJ dnipUKvTsEqsR9gY2BQ1l40ytc80f4hZwqI62HNbJZw87dasEGLejmaXM6CcXBs1j9nDrbryi3o 7NImCFz/cjROJU2PtmUibEWuTwefz+z6l5neLlZXNITXrNN3WzIh69hh6d6upOuhzE0sEe0cIgb 97HoGe4sj+WJjEdTWwuSw5aWtNAqUIVyNz1RUNxG30nuNmbe+TDWS/0IO2bijn0V9Qf/fkQ5Px/ aF9Mftx5EGMi6MUQemRwWUWTc3fOTnoqT78Sp0QKJOD40PdBwdGOoKzTwX/+QatJ0mGgYSB5Jed u1w6hiwzaive1asaiSgzj7wzd/5MzerJxQUbzDUl//c2tFf6HIlbfzdup6z0gdkGpE8I7sMDgH5 C0NAIsiKcr3s0KHzagg== X-Authority-Analysis: v=2.4 cv=PvSergM3 c=1 sm=1 tr=0 ts=69660e6a cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=UqCG9HQmAAAA:8 a=2haS3Ga0fGOBmvNocw8A:9 a=324X-CrmTo6CU4MGRt3R:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-13_01,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601130078 Content-Type: text/plain; charset="utf-8" From: Vignesh Viswanathan Add support to bring up hexagon based WCSS using secure PIL. All IPQxxxx SoCs support secure Peripheral Image Loading (PIL). Secure PIL image is signed firmware image which only trusted software such as TrustZone (TZ) can authenticate and load. Linux kernel will send a Peripheral Authentication Service (PAS) request to TZ to authenticate and load the PIL images. In order to avoid overloading the existing WCSS driver or PAS driver, we came up with this new PAS based IPQ WCSS driver. Signed-off-by: Vignesh Viswanathan Signed-off-by: Manikanta Mylavarapu Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: George Moussalem [ Dropped ipq5424 support ] Signed-off-by: Varadarajan Narayanan --- v10: Remove unused members from 'struct wcss_sec' Remove glink and ssr subdevices if wcss_sec_probe() fails v8: Dropped ipq5424 support. The comments related to 'use_tmelcom' in [1] not applicable [1] https://lore.kernel.org/linux-arm-msm/72f0d4f7-8d8a-4fc5-bac2-8094e= 971a0e3@oss.qualcomm.com/ Changed copyright for drivers/remoteproc/qcom_q6v5_wcss_sec.c --- drivers/remoteproc/Kconfig | 19 ++ drivers/remoteproc/Makefile | 1 + drivers/remoteproc/qcom_q6v5_wcss_sec.c | 325 ++++++++++++++++++++++++ include/linux/remoteproc.h | 2 + 4 files changed, 347 insertions(+) create mode 100644 drivers/remoteproc/qcom_q6v5_wcss_sec.c diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 48a0d3a69ed0..eaa427e4e9ec 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -254,6 +254,25 @@ config QCOM_Q6V5_WCSS Hexagon V5 based WCSS remote processors on e.g. IPQ8074. This is a non-TrustZone wireless subsystem. =20 +config QCOM_Q6V5_WCSS_SEC + tristate "Qualcomm Hexagon based WCSS Secure Peripheral Image Loader" + depends on OF && ARCH_QCOM + depends on QCOM_SMEM + depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=3Dn + depends on RPMSG_QCOM_GLINK || RPMSG_QCOM_GLINK=3Dn + select QCOM_MDT_LOADER + select QCOM_PIL_INFO + select QCOM_Q6V5_COMMON + select QCOM_RPROC_COMMON + select QCOM_SCM + help + Say y here to support the Qualcomm Secure Peripheral Image Loader + for the Hexagon based remote processors on e.g. IPQ5332. + + This is TrustZone wireless subsystem. The firmware is + verified and booted with the help of the Peripheral Authentication + System (PAS) in TrustZone. + config QCOM_SYSMON tristate "Qualcomm sysmon driver" depends on RPMSG diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 1c7598b8475d..08705ef62bce 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_QCOM_Q6V5_ADSP) +=3D qcom_q6v5_adsp.o obj-$(CONFIG_QCOM_Q6V5_MSS) +=3D qcom_q6v5_mss.o obj-$(CONFIG_QCOM_Q6V5_PAS) +=3D qcom_q6v5_pas.o obj-$(CONFIG_QCOM_Q6V5_WCSS) +=3D qcom_q6v5_wcss.o +obj-$(CONFIG_QCOM_Q6V5_WCSS_SEC) +=3D qcom_q6v5_wcss_sec.o obj-$(CONFIG_QCOM_SYSMON) +=3D qcom_sysmon.o obj-$(CONFIG_QCOM_WCNSS_PIL) +=3D qcom_wcnss_pil.o qcom_wcnss_pil-y +=3D qcom_wcnss.o diff --git a/drivers/remoteproc/qcom_q6v5_wcss_sec.c b/drivers/remoteproc/q= com_q6v5_wcss_sec.c new file mode 100644 index 000000000000..10a69fcd20f0 --- /dev/null +++ b/drivers/remoteproc/qcom_q6v5_wcss_sec.c @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include + +#include "qcom_common.h" +#include "qcom_q6v5.h" +#include "qcom_pil_info.h" + +#define WCSS_CRASH_REASON 421 + +#define WCSS_PAS_ID 0x6 +#define MPD_WCSS_PAS_ID 0xd + +#define Q6_WAIT_TIMEOUT (5 * HZ) + +struct wcss_sec { + struct device *dev; + struct qcom_rproc_glink glink_subdev; + struct qcom_rproc_ssr ssr_subdev; + struct qcom_q6v5 q6; + phys_addr_t mem_phys; + phys_addr_t mem_reloc; + void *mem_region; + size_t mem_size; + const struct wcss_data *desc; +}; + +struct wcss_data { + u32 pasid; + const char *ss_name; + bool auto_boot; +}; + +static int wcss_sec_start(struct rproc *rproc) +{ + struct wcss_sec *wcss =3D rproc->priv; + struct device *dev =3D wcss->dev; + int ret; + + ret =3D qcom_q6v5_prepare(&wcss->q6); + if (ret) + return ret; + + ret =3D qcom_scm_pas_auth_and_reset(wcss->desc->pasid); + if (ret) { + dev_err(dev, "wcss_reset failed\n"); + goto unprepare; + } + + ret =3D qcom_q6v5_wait_for_start(&wcss->q6, Q6_WAIT_TIMEOUT); + if (ret =3D=3D -ETIMEDOUT) + dev_err(dev, "start timed out\n"); + +unprepare: + qcom_q6v5_unprepare(&wcss->q6); + + return ret; +} + +static int wcss_sec_stop(struct rproc *rproc) +{ + struct wcss_sec *wcss =3D rproc->priv; + struct device *dev =3D wcss->dev; + int ret; + + ret =3D qcom_scm_pas_shutdown(wcss->desc->pasid); + if (ret) { + dev_err(dev, "not able to shutdown\n"); + return ret; + } + + qcom_q6v5_unprepare(&wcss->q6); + + return 0; +} + +static void *wcss_sec_da_to_va(struct rproc *rproc, u64 da, size_t len, + bool *is_iomem) +{ + struct wcss_sec *wcss =3D rproc->priv; + int offset; + + offset =3D da - wcss->mem_reloc; + if (offset < 0 || offset + len > wcss->mem_size) + return NULL; + + return wcss->mem_region + offset; +} + +static int wcss_sec_load(struct rproc *rproc, const struct firmware *fw) +{ + struct wcss_sec *wcss =3D rproc->priv; + struct device *dev =3D wcss->dev; + int ret; + + ret =3D qcom_mdt_load(dev, fw, rproc->firmware, wcss->desc->pasid, wcss->= mem_region, + wcss->mem_phys, wcss->mem_size, &wcss->mem_reloc); + if (ret) + return ret; + + qcom_pil_info_store("wcss", wcss->mem_phys, wcss->mem_size); + + return 0; +} + +static unsigned long wcss_sec_panic(struct rproc *rproc) +{ + struct wcss_sec *wcss =3D rproc->priv; + + return qcom_q6v5_panic(&wcss->q6); +} + +static void wcss_sec_copy_segment(struct rproc *rproc, + struct rproc_dump_segment *segment, + void *dest, size_t offset, size_t size) +{ + struct wcss_sec *wcss =3D rproc->priv; + struct device *dev =3D wcss->dev; + + if (!segment->io_ptr) + segment->io_ptr =3D ioremap_wc(segment->da, segment->size); + + if (!segment->io_ptr) { + dev_err(dev, "Failed to ioremap segment %pad size 0x%zx\n", + &segment->da, segment->size); + return; + } + + if (offset + size < segment->size) { + memcpy(dest, segment->io_ptr + offset, size); + } else { + iounmap(segment->io_ptr); + segment->io_ptr =3D NULL; + } +} + +static int wcss_sec_dump_segments(struct rproc *rproc, + const struct firmware *fw) +{ + struct device *dev =3D rproc->dev.parent; + struct reserved_mem *rmem =3D NULL; + struct device_node *node; + int num_segs, index; + int ret; + + /* + * Parse through additional reserved memory regions for the rproc + * and add them to the coredump segments + */ + num_segs =3D of_count_phandle_with_args(dev->of_node, + "memory-region", NULL); + for (index =3D 0; index < num_segs; index++) { + node =3D of_parse_phandle(dev->of_node, + "memory-region", index); + if (!node) + return -EINVAL; + + rmem =3D of_reserved_mem_lookup(node); + of_node_put(node); + if (!rmem) { + dev_err(dev, "unable to acquire memory-region index %d num_segs %d\n", + index, num_segs); + return -EINVAL; + } + + dev_dbg(dev, "Adding segment 0x%pa size 0x%pa", + &rmem->base, &rmem->size); + ret =3D rproc_coredump_add_custom_segment(rproc, + rmem->base, + rmem->size, + wcss_sec_copy_segment, + NULL); + if (ret) + return ret; + } + + return 0; +} + +static const struct rproc_ops wcss_sec_ops =3D { + .start =3D wcss_sec_start, + .stop =3D wcss_sec_stop, + .da_to_va =3D wcss_sec_da_to_va, + .load =3D wcss_sec_load, + .get_boot_addr =3D rproc_elf_get_boot_addr, + .panic =3D wcss_sec_panic, + .parse_fw =3D wcss_sec_dump_segments, +}; + +static int wcss_sec_alloc_memory_region(struct wcss_sec *wcss) +{ + struct device *dev =3D wcss->dev; + struct resource res; + int ret; + + ret =3D of_reserved_mem_region_to_resource(dev->of_node, 0, &res); + if (ret) { + dev_err(dev, "unable to acquire memory-region resource\n"); + return ret; + } + + wcss->mem_phys =3D res.start; + wcss->mem_reloc =3D res.start; + wcss->mem_size =3D resource_size(&res); + wcss->mem_region =3D devm_ioremap_resource_wc(dev, &res); + if (!wcss->mem_region) { + dev_err(dev, "unable to map memory region: %pR\n", &res); + return -ENOMEM; + } + + return 0; +} + +static int wcss_sec_probe(struct platform_device *pdev) +{ + const struct wcss_data *desc =3D of_device_get_match_data(&pdev->dev); + const char *fw_name =3D NULL; + struct wcss_sec *wcss; + struct clk *sleep_clk; + struct clk *int_clk; + struct rproc *rproc; + int ret; + + ret =3D of_property_read_string(pdev->dev.of_node, "firmware-name", + &fw_name); + if (ret < 0) + return ret; + + rproc =3D devm_rproc_alloc(&pdev->dev, desc->ss_name, &wcss_sec_ops, + fw_name, sizeof(*wcss)); + if (!rproc) { + dev_err(&pdev->dev, "failed to allocate rproc\n"); + return -ENOMEM; + } + + wcss =3D rproc->priv; + wcss->dev =3D &pdev->dev; + wcss->desc =3D desc; + + ret =3D wcss_sec_alloc_memory_region(wcss); + if (ret) + return ret; + + sleep_clk =3D devm_clk_get_optional_enabled(&pdev->dev, "sleep"); + if (IS_ERR(sleep_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(sleep_clk), + "Failed to get sleep clock\n"); + + int_clk =3D devm_clk_get_optional_enabled(&pdev->dev, "interconnect"); + if (IS_ERR(int_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(int_clk), + "Failed to get interconnect clock\n"); + + ret =3D qcom_q6v5_init(&wcss->q6, pdev, rproc, + WCSS_CRASH_REASON, NULL, NULL); + if (ret) + return ret; + + qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ss_name); + qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ss_name); + + rproc->auto_boot =3D false; + rproc->dump_conf =3D RPROC_COREDUMP_INLINE; + rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); + + ret =3D devm_rproc_add(&pdev->dev, rproc); + if (ret) { + qcom_remove_glink_subdev(rproc, &wcss->glink_subdev); + qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev); + return ret; + } + + platform_set_drvdata(pdev, rproc); + + return 0; +} + +static void wcss_sec_remove(struct platform_device *pdev) +{ + struct rproc *rproc =3D platform_get_drvdata(pdev); + struct wcss_sec *wcss =3D rproc->priv; + + qcom_remove_glink_subdev(rproc, &wcss->glink_subdev); + qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev); + qcom_q6v5_deinit(&wcss->q6); +} + +static const struct wcss_data wcss_sec_ipq5332_res_init =3D { + .pasid =3D MPD_WCSS_PAS_ID, + .ss_name =3D "q6wcss", +}; + +static const struct wcss_data wcss_sec_ipq9574_res_init =3D { + .pasid =3D WCSS_PAS_ID, + .ss_name =3D "q6wcss", +}; + +static const struct of_device_id wcss_sec_of_match[] =3D { + { .compatible =3D "qcom,ipq5018-wcss-sec-pil", .data =3D &wcss_sec_ipq533= 2_res_init }, + { .compatible =3D "qcom,ipq5332-wcss-sec-pil", .data =3D &wcss_sec_ipq533= 2_res_init }, + { .compatible =3D "qcom,ipq9574-wcss-sec-pil", .data =3D &wcss_sec_ipq957= 4_res_init }, + { }, +}; +MODULE_DEVICE_TABLE(of, wcss_sec_of_match); + +static struct platform_driver wcss_sec_driver =3D { + .probe =3D wcss_sec_probe, + .remove =3D wcss_sec_remove, + .driver =3D { + .name =3D "qcom-wcss-secure-pil", + .of_match_table =3D wcss_sec_of_match, + }, +}; +module_platform_driver(wcss_sec_driver); + +MODULE_DESCRIPTION("Hexagon WCSS Secure Peripheral Image Loader"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index b4795698d8c2..7b2159853345 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -472,6 +472,7 @@ enum rproc_dump_mechanism { * @node: list node related to the rproc segment list * @da: device address of the segment * @size: size of the segment + * @io_ptr: ptr to store the ioremapped dump segment * @priv: private data associated with the dump_segment * @dump: custom dump function to fill device memory segment associated * with coredump @@ -483,6 +484,7 @@ struct rproc_dump_segment { dma_addr_t da; size_t size; =20 + void *io_ptr; void *priv; void (*dump)(struct rproc *rproc, struct rproc_dump_segment *segment, void *dest, size_t offset, size_t size); --=20 2.34.1