From nobody Mon Feb 9 08:41:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C599E3806CE; Tue, 13 Jan 2026 09:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294837; cv=none; b=BLhF+ZZ+YZwm0WlJzMYJKg5RoePGLL3I5DtlvMnbPx7Os2/32J0RGtB3J62d9Vi7j8u38CDiTHOU7P1GCc6hqyIX8IbN1J/NZSENLIFbiRqQg11LIxqyzHIKRrIUok99U5r0gzPYSEi2b0c2UuVfnlAAz3YBHOlCZfdi1cPN8/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294837; c=relaxed/simple; bh=q0CZF+CNg4Eo07tB77hWIOdhlAl3OZt8QEIqL+xObvQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d+1GhhNaWL5C6WAY2EWgWX6ZLVXExJ/v7QkMEjrka0AcJMpZVlYMMhOiOnVQHlH6ESVl4U7/rDeXGqR61fWT3JOtvAZWu/lC4mG7NbiSnTqXYgHyz3u0tNyFu9OQj6E+PdHBNeeeROHfVnjzCehYTexMEy1i5OQLtLQnV0xu/WQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id D825BC19424; Tue, 13 Jan 2026 09:00:35 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V3 1/7] irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 13 Jan 2026 16:59:34 +0800 Message-ID: <20260113085940.3344837-2-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260113085940.3344837-1-chenhuacai@loongson.cn> References: <20260113085940.3344837-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" csr_read64() is only available on 64BIT LoongArch platform, so use recently added adaptive csr_read() instead, so as to make the driver work on both 32BIT and 64BIT platform. BTW, make avecintc_enable() be a no-op since it is only needed by 64BIT platform. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongarch-avec.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-loongarch-avec.c b/drivers/irqchip/irq-loo= ngarch-avec.c index ba556c008cf3..fb8efde95393 100644 --- a/drivers/irqchip/irq-loongarch-avec.c +++ b/drivers/irqchip/irq-loongarch-avec.c @@ -58,11 +58,13 @@ struct avecintc_data { =20 static inline void avecintc_enable(void) { +#ifdef CONFIG_MACH_LOONGSON64 u64 value; =20 value =3D iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC); value |=3D IOCSR_MISC_FUNC_AVEC_EN; iocsr_write64(value, LOONGARCH_IOCSR_MISC_FUNC); +#endif } =20 static inline void avecintc_ack_irq(struct irq_data *d) @@ -167,7 +169,7 @@ void complete_irq_moving(void) struct pending_list *plist =3D this_cpu_ptr(&pending_list); struct avecintc_data *adata, *tdata; int cpu, vector, bias; - uint64_t isr; + unsigned long isr; =20 guard(raw_spinlock)(&loongarch_avec.lock); =20 @@ -177,16 +179,16 @@ void complete_irq_moving(void) bias =3D vector / VECTORS_PER_REG; switch (bias) { case 0: - isr =3D csr_read64(LOONGARCH_CSR_ISR0); + isr =3D csr_read(LOONGARCH_CSR_ISR0); break; case 1: - isr =3D csr_read64(LOONGARCH_CSR_ISR1); + isr =3D csr_read(LOONGARCH_CSR_ISR1); break; case 2: - isr =3D csr_read64(LOONGARCH_CSR_ISR2); + isr =3D csr_read(LOONGARCH_CSR_ISR2); break; case 3: - isr =3D csr_read64(LOONGARCH_CSR_ISR3); + isr =3D csr_read(LOONGARCH_CSR_ISR3); break; } =20 @@ -234,7 +236,7 @@ static void avecintc_irq_dispatch(struct irq_desc *desc) chained_irq_enter(chip, desc); =20 while (true) { - unsigned long vector =3D csr_read64(LOONGARCH_CSR_IRR); + unsigned long vector =3D csr_read(LOONGARCH_CSR_IRR); if (vector & IRR_INVALID_MASK) break; =20 --=20 2.47.3 From nobody Mon Feb 9 08:41:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FDB83806BA; Tue, 13 Jan 2026 09:01:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294873; cv=none; b=LY+HMLS79P860Ls3IHbSZXECXjId4JJc956eb07ZEYIJZdBZzWa0+sNBQbp8m6g5Qu5hu6OSa5d0PKZIZdrAsysH2fOiwEi2Ypz31eJWRLBKLTpauOcYv92gmzKCNBpupX3IIM/HpC12EYSeCvX6hqp3Oqlh/uS5zCO9/WIajfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294873; c=relaxed/simple; bh=dXK5xc/0Iy/RjvinuAmJfA4hXGDZuFREYUPikq+i30c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XQpCf81zy7+MFldIynAYDudHfKv17ValVoEj+4VD256Mre79re3Kc2LBd80oZmbqY9kWzlxFPW5avmFyJNgsN9BfYpXOx66XNp2m8Ws3hpEISH9u4OuELOFhZhl/NtrwjDkor6uIPExMznBf7eJI7snCtUDsgc2gHLDTge/Kd4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39F63C116C6; Tue, 13 Jan 2026 09:01:11 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V3 2/7] irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 13 Jan 2026 16:59:35 +0800 Message-ID: <20260113085940.3344837-3-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260113085940.3344837-1-chenhuacai@loongson.cn> References: <20260113085940.3344837-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_liointc->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-liointc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-l= oongson-liointc.c index 0033c2188abc..f001a34878ba 100644 --- a/drivers/irqchip/irq-loongson-liointc.c +++ b/drivers/irqchip/irq-loongson-liointc.c @@ -394,8 +394,9 @@ static int __init acpi_cascade_irqdomain_init(void) =20 int __init liointc_acpi_init(struct irq_domain *parent, struct acpi_madt_l= io_pic *acpi_liointc) { - int ret; + phys_addr_t addr =3D acpi_liointc->address; struct fwnode_handle *domain_handle; + int ret; =20 parent_int_map[0] =3D acpi_liointc->cascade_map[0]; parent_int_map[1] =3D acpi_liointc->cascade_map[1]; @@ -403,7 +404,7 @@ int __init liointc_acpi_init(struct irq_domain *parent,= struct acpi_madt_lio_pic parent_irq[0] =3D irq_create_mapping(parent, acpi_liointc->cascade[0]); parent_irq[1] =3D irq_create_mapping(parent, acpi_liointc->cascade[1]); =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_liointc->address); + domain_handle =3D irq_domain_alloc_fwnode(&addr); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM; --=20 2.47.3 From nobody Mon Feb 9 08:41:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 176933806D9; Tue, 13 Jan 2026 09:01:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294888; cv=none; b=G7yNZztPH00OhUN+ALCebLfPgs0fuYQSNw7Kjbi1cgCjRztsZ+/nO0Um0EYYdmgO7uIwRD61ZsDBeYcs8GZv5Nm/pnGEL5c4j3JOvqiWA5Se+IgYUW9AUnD6taDeOqgZzkwhm+ZRtYoxC30qFSFwPfFjDeQ3RIXu3WDWYiD+Kak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294888; c=relaxed/simple; bh=K1HSh2b2YWuH/M7VDjlzy1cWKmRgdJ3MLy3doy1wBaI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X9MJoZIAanTYKe6aCpEkQRJ0rTgky491iov0t7/WHKRyJG87Q0IFwOzH7zVr71aDVU2ItiE2zdqdyxWFKPdtIrJVmbOd/KDphVXoWXLhomb84KQ2Ra0qART5uubBt6d9WtnL6MfT81jxydhGb0RIonIpZvxmSdAaJDGxgIhryqk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED6DBC116C6; Tue, 13 Jan 2026 09:01:25 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V3 3/7] irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 13 Jan 2026 16:59:36 +0800 Message-ID: <20260113085940.3344837-4-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260113085940.3344837-1-chenhuacai@loongson.cn> References: <20260113085940.3344837-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" iocsr_read64()/iocsr_write64() are only available on 64BIT LoongArch platform, so add and use a pair of helpers, i.e. read_isr()/write_isr() instead, so as to make the driver work on both 32BIT and 64BIT platform. BTW, make eiointc_enable() be a no-op since it is only needed by 64BIT platform. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-eiointc.c | 36 +++++++++++++++++++++----- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-l= oongson-eiointc.c index ad2105685b48..e2eb4cd27f78 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -37,9 +37,9 @@ #define EXTIOI_ENABLE_INT_ENCODE BIT(2) #define EXTIOI_ENABLE_CPU_ENCODE BIT(3) =20 -#define VEC_REG_COUNT 4 -#define VEC_COUNT_PER_REG 64 -#define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG) +#define VEC_COUNT 256 +#define VEC_COUNT_PER_REG BITS_PER_LONG +#define VEC_REG_COUNT (VEC_COUNT / BITS_PER_LONG) #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG) #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG) #define EIOINTC_ALL_ENABLE 0xffffffff @@ -85,11 +85,13 @@ static struct eiointc_priv *eiointc_priv[MAX_IO_PICS]; =20 static void eiointc_enable(void) { +#ifdef CONFIG_MACH_LOONGSON64 uint64_t misc; =20 misc =3D iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC); misc |=3D IOCSR_MISC_FUNC_EXT_IOI_EN; iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC); +#endif } =20 static int cpu_to_eio_node(int cpu) @@ -281,12 +283,34 @@ static int eiointc_router_init(unsigned int cpu) return 0; } =20 +#if VEC_COUNT_PER_REG =3D=3D 32 +static unsigned long read_isr(int i) +{ + return iocsr_read32(EIOINTC_REG_ISR + (i << 2)); +} + +static void write_isr(int i, unsigned long val) +{ + iocsr_write32(val, EIOINTC_REG_ISR + (i << 2)); +} +#else +static unsigned long read_isr(int i) +{ + return iocsr_read64(EIOINTC_REG_ISR + (i << 3)); +} + +static void write_isr(int i, unsigned long val) +{ + iocsr_write64(val, EIOINTC_REG_ISR + (i << 3)); +} +#endif + static void eiointc_irq_dispatch(struct irq_desc *desc) { struct eiointc_ip_route *info =3D irq_desc_get_handler_data(desc); struct irq_chip *chip =3D irq_desc_get_chip(desc); bool handled =3D false; - u64 pending; + unsigned long pending; int i; =20 chained_irq_enter(chip, desc); @@ -299,14 +323,14 @@ static void eiointc_irq_dispatch(struct irq_desc *des= c) * read ISR for these 64 interrupt vectors rather than all vectors */ for (i =3D info->start; i < info->end; i++) { - pending =3D iocsr_read64(EIOINTC_REG_ISR + (i << 3)); + pending =3D read_isr(i); =20 /* Skip handling if pending bitmap is zero */ if (!pending) continue; =20 /* Clear the IRQs */ - iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3)); + write_isr(i, pending); while (pending) { int bit =3D __ffs(pending); int irq =3D bit + VEC_COUNT_PER_REG * i; --=20 2.47.3 From nobody Mon Feb 9 08:41:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 479B23815C7; Tue, 13 Jan 2026 09:01:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294911; cv=none; b=jHBaVIZCWbiL0iFweKVcAb63AFsfCKQ1aQ7ebEXeQrfDyBDAWkC3klJMNCke4At0oD6jwCk+cTgbmyw3rvqPr60SYRTl6wSSeyD0tfCO1AV6XuAi+JyGk7miDWU/iiJqN1SZ6NIWV3g7m1z8fyqSpne2Epl/SAsDqv9EmE8tRrY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294911; c=relaxed/simple; bh=YPsKWla8G5Acl7rRSlbGKMRcCpoedfItddAu4Gdzf/0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=csktxgd/z4niA5/xMR6NM4JfKzKUqL6LuXqCDLpAzJCP7OMDhDCj5bhi9uns2lL+w/w0/I/0CTsyFD9mtyNkGO4a3nG1vTz0fxSpn4j9UZoosy8ot9C94FLctGP2vibzW+zikLJzPBYucPB6ymdenyb3ohRll6N4OxcoXdzaOyc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 11136C116C6; Tue, 13 Jan 2026 09:01:48 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V3 4/7] irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 13 Jan 2026 16:59:37 +0800 Message-ID: <20260113085940.3344837-5-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260113085940.3344837-1-chenhuacai@loongson.cn> References: <20260113085940.3344837-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_htvec->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-htvec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loo= ngson-htvec.c index d2be8e954e92..03c3992b39c8 100644 --- a/drivers/irqchip/irq-loongson-htvec.c +++ b/drivers/irqchip/irq-loongson-htvec.c @@ -298,8 +298,8 @@ static int __init acpi_cascade_irqdomain_init(void) int __init htvec_acpi_init(struct irq_domain *parent, struct acpi_madt_ht_pic *acpi_htvec) { - int i, ret; - int num_parents, parent_irq[8]; + int i, ret, num_parents, parent_irq[8]; + phys_addr_t addr =3D acpi_htvec->address; struct fwnode_handle *domain_handle; =20 if (!acpi_htvec) @@ -307,7 +307,7 @@ int __init htvec_acpi_init(struct irq_domain *parent, =20 num_parents =3D HTVEC_MAX_PARENT_IRQ; =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_htvec->address); + domain_handle =3D irq_domain_alloc_fwnode(&addr); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM; --=20 2.47.3 From nobody Mon Feb 9 08:41:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 409AF3815C6; Tue, 13 Jan 2026 09:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294924; cv=none; b=rDSjwgM0Ddu9/QVT/epTblnbV7ufZqdFxWisXdSWhoqPRHCDvcrmwRoUjmSkR5PyYHtL3GCj5d+6Hk4Q6NLh3iEs165tOtt7iIr3JygGVQNTZ/EhiZxRWtepryIgfOoTz6dV0n6pkX623RE0CtVbiOHcl6yGdOLNJOFqq1Z0Y9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294924; c=relaxed/simple; bh=n0dxeLOCRes34IqYA6NMAtNQXEQIidRUp094thweXPE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fDj1LDVbrpZ3XEoLTGJ2YtjQn76R93EEFx74oJvi0hP3kfq/WU1hi0zSgta9HBayH6CH6WiQB6zXwrczNTd9x56woUSFHUV+yibHQPnPR7aSTTHzcsQKgllxI73ohH6+DdDmYFUMv6TorlU8dlFLzXylpqyVuurb91iPPPi84iI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 114C1C19422; Tue, 13 Jan 2026 09:02:01 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V3 5/7] irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 13 Jan 2026 16:59:38 +0800 Message-ID: <20260113085940.3344837-6-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260113085940.3344837-1-chenhuacai@loongson.cn> References: <20260113085940.3344837-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_pchmsi->msg_address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-msi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-msi.c b/drivers/irqchip/irq-l= oongson-pch-msi.c index 4aedc9b90ff7..8500662bdb33 100644 --- a/drivers/irqchip/irq-loongson-pch-msi.c +++ b/drivers/irqchip/irq-loongson-pch-msi.c @@ -263,11 +263,12 @@ struct fwnode_handle *get_pch_msi_handle(int pci_segm= ent) =20 int __init pch_msi_acpi_init(struct irq_domain *parent, struct acpi_madt_m= si_pic *acpi_pchmsi) { - int ret; + phys_addr_t msg_address =3D acpi_pchmsi->msg_address; struct fwnode_handle *domain_handle; + int ret; =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_pchmsi->msg_address); - ret =3D pch_msi_init(acpi_pchmsi->msg_address, acpi_pchmsi->start, + domain_handle =3D irq_domain_alloc_fwnode(&msg_address); + ret =3D pch_msi_init(msg_address, acpi_pchmsi->start, acpi_pchmsi->count, parent, domain_handle); if (ret < 0) irq_domain_free_fwnode(domain_handle); --=20 2.47.3 From nobody Mon Feb 9 08:41:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FC0A3816F3; Tue, 13 Jan 2026 09:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294936; cv=none; b=PrqKDXEf8SrWy9HSs6VP852gkgX/5OpUBumCa41bwTevBdj763U424ffQaKjrUCy9EEqKLkGZyMhAPFU1NkBSfNQL69m1oLzAzfmIPxPennprWDSxZhdaBLgYrcsFAvbs4O+6z2Ay59lyPgT+OHF0ylkiUJhkAY4swct+fyujnU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294936; c=relaxed/simple; bh=sYoFKOzueta7oShUuE+v4VS+babWzv033PSihn5ipl4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=paKMrXzxULt5Fmdb0oTmybMa4reDi+xMxZNiaK34bs01OHiCSaZuUlN9EjiZhRsuuspn9tQRlFoNJtTwn6J88gN/35wxyFTP9LtMlh281kEk1GZ8/pP2KdhWKq6gYNgiTZSyK52G5RYjp/353qr/zCATE+m+tSbA09qijYiNDT8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4ADDAC19423; Tue, 13 Jan 2026 09:02:14 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V3 6/7] irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT Date: Tue, 13 Jan 2026 16:59:39 +0800 Message-ID: <20260113085940.3344837-7-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260113085940.3344837-1-chenhuacai@loongson.cn> References: <20260113085940.3344837-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" irq_domain_alloc_fwnode() takes a parameter with the phys_addr_t type. Currently we pass acpi_pchpic->address to it. This can only work on 64BIT platform because its type is u64, so cast it to phys_addr_t and then the driver works on both 32BIT and 64BIT platform. BTW, use readl() to get vec_count because readq() is only available on 64BIT platform. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-pic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-l= oongson-pch-pic.c index c6b369a974a7..2ac7e3245b72 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -343,7 +343,7 @@ static int pch_pic_init(phys_addr_t addr, unsigned long= size, int vec_base, priv->table[i] =3D PIC_UNDEF_VECTOR; =20 priv->ht_vec_base =3D vec_base; - priv->vec_count =3D ((readq(priv->base) >> 48) & 0xff) + 1; + priv->vec_count =3D ((readl(priv->base + 4) >> 16) & 0xff) + 1; priv->gsi_base =3D gsi_base; =20 priv->pic_domain =3D irq_domain_create_hierarchy(parent_domain, 0, @@ -449,13 +449,14 @@ static int __init acpi_cascade_irqdomain_init(void) int __init pch_pic_acpi_init(struct irq_domain *parent, struct acpi_madt_bio_pic *acpi_pchpic) { - int ret; + phys_addr_t addr =3D acpi_pchpic->address; struct fwnode_handle *domain_handle; + int ret; =20 if (find_pch_pic(acpi_pchpic->gsi_base) >=3D 0) return 0; =20 - domain_handle =3D irq_domain_alloc_fwnode(&acpi_pchpic->address); + domain_handle =3D irq_domain_alloc_fwnode(&addr); if (!domain_handle) { pr_err("Unable to allocate domain handle\n"); return -ENOMEM; --=20 2.47.3 From nobody Mon Feb 9 08:41:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 071DF3815C2; Tue, 13 Jan 2026 09:02:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294951; cv=none; b=eE25JRXueCcHsEmzlRgicjx99+7PgsMlv8uI63/j4bgGY1p1d6sVNhNpEKc1rnVGsypJ3mIFnLTisj2Op+SdwL/zq5DCb+ZRyKgQJ+0DpIrkuQBOWn2aEXDD7D8+ajUSn73n9DVYQSwYPkndmYxL9+Fl9xIDWQJAPrxxh3TXE2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768294951; c=relaxed/simple; bh=JSiPb2RnLtMPL21l8Qk+GasrgfOQb4XXLrGb5p1UAdc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nfOi+NgoWT3BzL7Ny0hApD8IdoCq5Bps7ryVTZT9VF0JyOo0s0TAwtcGWWabwwIEBFH5AhC0lGV1xzs6O97O+unFsahKY6zNVvXhF8ziHBvlneaAt+8Fy3rb0Ys3mCgb05cBHY6rWBFrNXZUlltqPLKlANcFmbPF6p4Ba+LB7fU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA448C116C6; Tue, 13 Jan 2026 09:02:28 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH V3 7/7] irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT Date: Tue, 13 Jan 2026 16:59:40 +0800 Message-ID: <20260113085940.3344837-8-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260113085940.3344837-1-chenhuacai@loongson.cn> References: <20260113085940.3344837-1-chenhuacai@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All LoongArch irqchip drivers are adjusted, allow them be built on both 32BIT and 64BIT platforms. Co-developed-by: Jiaxun Yang Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen --- drivers/irqchip/Kconfig | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f334f49c9791..270f1c4783e3 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -698,7 +698,7 @@ config IRQ_LOONGARCH_CPU =20 config LOONGSON_LIOINTC bool "Loongson Local I/O Interrupt Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default y select IRQ_DOMAIN select GENERIC_IRQ_CHIP @@ -708,7 +708,6 @@ config LOONGSON_LIOINTC config LOONGSON_EIOINTC bool "Loongson Extend I/O Interrupt Controller" depends on LOONGARCH - depends on MACH_LOONGSON64 default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY select GENERIC_IRQ_CHIP @@ -726,7 +725,7 @@ config LOONGSON_HTPIC =20 config LOONGSON_HTVEC bool "Loongson HyperTransport Interrupt Vector Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY help @@ -734,7 +733,7 @@ config LOONGSON_HTVEC =20 config LOONGSON_PCH_PIC bool "Loongson PCH PIC Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY select IRQ_FASTEOI_HIERARCHY_HANDLERS @@ -743,7 +742,7 @@ config LOONGSON_PCH_PIC =20 config LOONGSON_PCH_MSI bool "Loongson PCH MSI Controller" - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH depends on PCI default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY @@ -755,7 +754,7 @@ config LOONGSON_PCH_MSI config LOONGSON_PCH_LPC bool "Loongson PCH LPC Controller" depends on LOONGARCH - depends on MACH_LOONGSON64 + depends on MACH_LOONGSON64 || LOONGARCH default MACH_LOONGSON64 select IRQ_DOMAIN_HIERARCHY help --=20 2.47.3