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Mon, 12 Jan 2026 21:49:38 -0800 From: Ashish Mhetre To: , , , , , , CC: , , , , , , , , , Ashish Mhetre Subject: [PATCH V8 2/4] iommu/arm-smmu-v3: Add device-tree support for CMDQV driver Date: Tue, 13 Jan 2026 05:49:33 +0000 Message-ID: <20260113054935.1945785-3-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260113054935.1945785-1-amhetre@nvidia.com> References: <20260113054935.1945785-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE34:EE_|MN2PR12MB4438:EE_ X-MS-Office365-Filtering-Correlation-Id: 4c778492-5dc4-430f-9547-08de52679234 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2026 05:49:52.0170 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c778492-5dc4-430f-9547-08de52679234 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE34.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4438 Content-Type: text/plain; charset="utf-8" Add device tree support to the CMDQV driver to enable usage on Tegra264 SoCs. The implementation parses the nvidia,cmdqv phandle from the SMMU device tree node to associate each SMMU with its corresponding CMDQV instance based on compatible string. Reviewed-by: Nicolin Chen Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 32 +++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index dad3c0cb800b..8653c52977d7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4530,6 +4530,35 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_= device *smmu) return 0; } =20 +#ifdef CONFIG_TEGRA241_CMDQV +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node, + struct arm_smmu_device *smmu) +{ + struct platform_device *pdev; + struct device_node *np; + + np =3D of_parse_phandle(smmu_node, "nvidia,cmdqv", 0); + if (!np) + return; + + /* Tegra241 CMDQV driver is responsible for put_device() */ + pdev =3D of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return; + + smmu->impl_dev =3D &pdev->dev; + smmu->options |=3D ARM_SMMU_OPT_TEGRA241_CMDQV; + dev_dbg(smmu->dev, "found companion CMDQV device: %s\n", + dev_name(smmu->impl_dev)); +} +#else +static void tegra_cmdqv_dt_probe(struct device_node *smmu_node, + struct arm_smmu_device *smmu) +{ +} +#endif + #ifdef CONFIG_ACPI #ifdef CONFIG_TEGRA241_CMDQV static void acpi_smmu_dsdt_probe_tegra241_cmdqv(struct acpi_iort_node *nod= e, @@ -4635,6 +4664,9 @@ static int arm_smmu_device_dt_probe(struct platform_d= evice *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |=3D ARM_SMMU_FEAT_COHERENCY; =20 + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + tegra_cmdqv_dt_probe(dev->of_node, smmu); + return ret; } =20 --=20 2.25.1