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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f23b798asm21162429c88.0.2026.01.13.02.28.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jan 2026 02:28:33 -0800 (PST) From: Hangxiang Ma Date: Tue, 13 Jan 2026 02:28:30 -0800 Subject: [PATCH v2 4/5] media: qcom: camss: csid: Add support for CSID 980 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260113-sm8750-camss-v2-4-e5487b98eada@oss.qualcomm.com> References: <20260113-sm8750-camss-v2-0-e5487b98eada@oss.qualcomm.com> In-Reply-To: <20260113-sm8750-camss-v2-0-e5487b98eada@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=BYXVE7t2 c=1 sm=1 tr=0 ts=69661e54 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=63CfXtnvIBONjkcrFHoA:9 a=Z-sH2BZsVlbqz-yA:21 a=QEXdDO2ut3YA:10 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-ORIG-GUID: hF2sAdwOoJIF5ck0Au2lDAal2UU-HFSf X-Proofpoint-GUID: hF2sAdwOoJIF5ck0Au2lDAal2UU-HFSf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEzMDA4OCBTYWx0ZWRfXw2ws/TDKyaUs Ctv7rKOWMk0ujv0CVm7rO0QmuU3WnAh0+cGGqm6jeD6ZUEsAvYB1nx6Ur5R5pNAbx9uG2xCihTW 0wcti+y42rTBlG6Sm47TqxsBCduTCUPxi08LxOov0djQe7/q/Ln1Ig7WVccY9o/+wivleKmL/fu GcbLxDPPN/ikQDHBgA7Jq3QacK/mAeuBBkFKHSej7J7qkMwwkqmIBunsK6AUqIR3ji+nVBwujOP Wchq+2XaCZ7JpwpCtPXTpUG5p2c5rpsxZCe5VkVgK08rRQSHp8zl6i/eCVk4WMy/4c/Bx0dAbzQ zxb3NttMxdOPnOxKI6GTa+ssNp6tTvZ6O0vW+fr5+aW+ujFPoGLtvN/LPhMx4Q4QG7l+X7rqPsh +TokS7l5XZAX7/Py6JpVI32PRWkrINSJsPBATafwVrZFPgvw0iEnxBJ0G8W63yyrtcSKRIt6F9f Woc3YbavqJZEP3FTn8w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-13_02,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601130088 Add more detailed resource information for CSID devices along with the driver for CSID 980 that is responsible for CSID register configuration, module reset and IRQ handling for BUF_DONE events. In SM8750, RUP and AUP updates for the CSID Full modules are split into two registers along with a SET register. However, CSID Lite modules still use a single register to update RUP and AUP without the additional SET register. Handled such differences in the driver. Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + drivers/media/platform/qcom/camss/camss-csid-980.c | 442 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss-csid.h | 1 + drivers/media/platform/qcom/camss/camss.c | 75 ++++ 4 files changed, 519 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index ed8001ef90a6..45fd7fee59ba 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -8,6 +8,7 @@ qcom-camss-objs +=3D \ camss-csid-4-7.o \ camss-csid-340.o \ camss-csid-680.o \ + camss-csid-980.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ camss-csid-gen4.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-980.c b/drivers/m= edia/platform/qcom/camss/camss-csid-980.c new file mode 100644 index 000000000000..87d26a18081d --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-980.c @@ -0,0 +1,442 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-980.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0xC +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10 +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x14 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x18 +#define CSID_AUP_CMD 0x1C +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x20 +#define RUP_SET BIT(0) +#define MUP BIT(4) + +#define CSID_LITE_RUP_AUP_CMD 0x18 +#define CSID_LITE_RUP_RDI(rdi) (BIT(4) << (rdi)) +#define CSID_LITE_AUP_RDI(rdi) (BIT(20) << (rdi)) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS (csid_is_lite(csid) ? 0x7C : 0x84) +#define CSID_TOP_IRQ_MASK (csid_is_lite(csid) ? 0x80 : 0x88) +#define CSID_TOP_IRQ_CLEAR (csid_is_lite(csid) ? 0x84 : 0x8C) +#define CSID_TOP_IRQ_SET (csid_is_lite(csid) ? 0x88 : 0x90) +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(csid_is_lite(csid) ? 13 : 3) + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS (csid_is_lite(csid) ? 0x8C : 0xA4) +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET (csid_is_lite(csid) ? 1 : 16) +#define CSID_BUF_DONE_IRQ_MASK (csid_is_lite(csid) ? 0x90 : 0xA8) +#define CSID_BUF_DONE_IRQ_CLEAR (csid_is_lite(csid) ? 0x94 : 0xAC) +#define CSID_BUF_DONE_IRQ_SET (csid_is_lite(csid) ? 0x98 : 0xB0) + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS (csid_is_lite(csid) ? 0x9C : 0xB4) +#define CSID_CSI2_RX_IRQ_MASK (csid_is_lite(csid) ? 0xA0 : 0xB8) +#define CSID_CSI2_RX_IRQ_CLEAR (csid_is_lite(csid) ? 0xA4 : 0xBC) +#define CSID_CSI2_RX_IRQ_SET (csid_is_lite(csid) ? 0xA8 : 0xC0) + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 (csid_is_lite(csid) ? 0x200 : 0x400) +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSID_CSI2_RX_CFG1 (csid_is_lite(csid) ? 0x204 : 0x404) +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_980 (csid_is_lite(csid) ? 4 : 5) + +#define CSID_RDI_CFG0(rdi) \ + ({ \ + __typeof__(rdi) _rdi =3D (rdi); \ + csid_is_lite(csid) ? 0x500 + 0x100 * _rdi : \ + 0xE00 + 0x200 * _rdi; \ + }) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_DT_ID 27 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) \ + ({ \ + __typeof__(rdi) _rdi =3D (rdi); \ + csid_is_lite(csid) ? 0x504 + 0x100 * _rdi : \ + 0xE04 + 0x200 * _rdi; \ + }) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) \ + ({ \ + __typeof__(rdi) _rdi =3D (rdi); \ + csid_is_lite(csid) ? 0x510 + 0x100 * _rdi : \ + 0xE10 + 0x200 * _rdi; \ + }) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0xE14 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) \ + (csid_is_lite(csid) ? 0xEC : 0x114 + 0x10 * (rdi)) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) \ + (csid_is_lite(csid) ? 0xF4 : 0x11C + 0x10 * (rdi)) +#define INFO_RUP_DONE BIT(23) + +static void __csid_full_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_aup_update(struct csid_device *csid, int port_id) +{ + if (csid_is_lite(csid)) { + /* CSID Lites in v980 follow the legacy way of a combined RUP + * and AUP commands without an explicit SET register. + */ + csid->reg_update |=3D CSID_LITE_AUP_RDI(port_id); + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD); + } else { + csid->aup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + /* CSID Fulls in v980 split AUP and RUP commands, which requires + * additional SET operation to make registers modification take + * effect. + */ + __csid_full_aup_rup_trigger(csid); + } +} + +static void __csid_rup_update(struct csid_device *csid, int port_id) +{ + if (csid_is_lite(csid)) { + /* CSID Lites in v980 follow the legacy way of a combined RUP + * and AUP commands without an explicit SET register. + */ + csid->reg_update |=3D CSID_LITE_RUP_RDI(port_id); + writel(csid->reg_update, csid->base + CSID_LITE_RUP_AUP_CMD); + } else { + csid->rup_update |=3D CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + /* CSID Fulls in v980 split AUP and RUP commands, which requires + * additional SET operation to make registers modification take + * effect. + */ + __csid_full_aup_rup_trigger(csid); + } +} + +static void __csid_aup_rup_clear(struct csid_device *csid, int port_id) +{ + /* Hardware clears the registers upon consuming the settings */ + if (csid_is_lite(csid)) { + csid->reg_update &=3D ~CSID_LITE_RUP_RDI(port_id); + csid->reg_update &=3D ~CSID_LITE_AUP_RDI(port_id); + } else { + csid->aup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + csid->rup_update &=3D ~CSID_RUP_AUP_RDI(port_id); + } +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + int val; + + val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val =3D readl(csid->base + CSID_CSI2_RX_CFG1); + val |=3D CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val =3D 0; + u32 rdi_ctrl_offset =3D CSID_RDI_CTRL(rdi); + + if (enable) + val =3D RDI_CTRL_START_CMD; + + writel(val, csid->base + rdi_ctrl_offset); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rd= i) +{ + u32 val; + + /* Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=3D4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val =3D (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enabl= e, u8 vc) +{ + u32 val; + u8 lane_cnt =3D csid->phy.lane_cnt; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format =3D &csid->fmt[MSM_CSID_PAD_FIRST= _SRC + vc]; + const struct csid_format_info *format =3D csid_get_fmt_entry(csid->res->f= ormats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt =3D 4; + + /* + * DT_ID is a two bit bitfield that is concatenated with + * the four least significant bits of the five bit VC + * bitfield to generate an internal CID value. + * + * CSID_RDI_CFG0(vc) + * DT_ID : 28:27 + * VC : 26:22 + * DT : 21:16 + * + * CID : VC 3:0 << 2 | DT_ID 1:0 + */ + u8 dt_id =3D vc & 0x03; + u32 rdi_cfg0_offset =3D CSID_RDI_CFG0(vc); + u32 rdi_cfg1_offset =3D CSID_RDI_CFG1(vc); + u32 rdi_ctrl_offset =3D CSID_RDI_CTRL(vc); + + val =3D RDI_CFG0_TIMESTAMP_EN; + val |=3D RDI_CFG0_TIMESTAMP_STB_SEL; + val |=3D RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |=3D DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |=3D vc << RDI_CFG0_VC; + val |=3D format->data_type << RDI_CFG0_DT; + val |=3D dt_id << RDI_CFG0_DT_ID; + writel(val, csid->base + rdi_cfg0_offset); + + val =3D RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + rdi_cfg1_offset); + + /* Configure pixel store using dedicated register in 980 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, vc); + + val =3D 0; + writel(val, csid->base + rdi_ctrl_offset); + + val =3D readl(csid->base + rdi_cfg0_offset); + + if (enable) + val |=3D RDI_CFG0_EN; + + writel(val, csid->base + rdi_cfg0_offset); +} + +static void csid_configure_stream_980(struct csid_device *csid, u8 enable) +{ + u8 vc, i; + + __csid_configure_rx(csid, &csid->phy); + + for (vc =3D 0; vc < MSM_CSID_MAX_SRC_STREAMS_980; vc++) { + if (csid->phy.en_vc & BIT(vc)) { + __csid_configure_rdi_stream(csid, enable, vc); + __csid_configure_rx_vc(csid, vc); + + for (i =3D 0; i < CAMSS_INIT_BUF_COUNT; i++) { + __csid_aup_update(csid, vc); + __csid_rup_update(csid, vc); + } + + __csid_ctrl_rdi(csid, enable, vc); + } + } +} + +static int csid_configure_testgen_pattern_980(struct csid_device *csid, + s32 val) +{ + return 0; +} + +static void csid_subdev_reg_update_980(struct csid_device *csid, int port_= id, + bool clear) +{ + if (clear) + __csid_aup_rup_clear(csid, port_id); + else + __csid_aup_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr_980(int irq, void *dev) +{ + struct csid_device *csid =3D dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val =3D readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done =3D val & INFO_RST_DONE; + + buf_done_val =3D readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { + if (csid->phy.en_vc & BIT(i)) { + val =3D readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) + csid_subdev_reg_update_980(csid, i, true); + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset_980(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val =3D INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val =3D 0; + for (i =3D 0; i < MSM_CSID_MAX_SRC_STREAMS_980; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |=3D BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val =3D IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val =3D RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val =3D SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time =3D wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void csid_subdev_init_980(struct csid_device *csid) +{ + csid->testgen.nmodes =3D CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_980 =3D { + .configure_stream =3D csid_configure_stream_980, + .configure_testgen_pattern =3D csid_configure_testgen_pattern_980, + .hw_version =3D csid_hw_version, + .isr =3D csid_isr_980, + .reset =3D csid_reset_980, + .src_pad_code =3D csid_src_pad_code, + .subdev_init =3D csid_subdev_init_980, + .reg_update =3D csid_subdev_reg_update_980, +}; + diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media= /platform/qcom/camss/camss-csid.h index 75a113050eb1..7a3de10a2a88 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -223,6 +223,7 @@ extern const struct csid_hw_ops csid_ops_4_1; extern const struct csid_hw_ops csid_ops_4_7; extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; +extern const struct csid_hw_ops csid_ops_980; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; extern const struct csid_hw_ops csid_ops_gen4; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 1f9a91178002..c52e6f7b6294 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4189,6 +4189,79 @@ static const struct camss_subdev_resources csiphy_re= s_8750[] =3D { }, }; =20 +static const struct camss_subdev_resources csid_res_8750[] =3D { + /* CSID0 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid0" }, + .interrupt =3D { "csid0" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid1" }, + .interrupt =3D { "csid1" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .clock =3D { "csid", "csid_csiphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid2" }, + .interrupt =3D { "csid2" }, + .csid =3D { + .is_lite =3D false, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite0" }, + .interrupt =3D { "csid_lite0" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .clock =3D { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg =3D { "csid_lite1" }, + .interrupt =3D { "csid_lite1" }, + .csid =3D { + .is_lite =3D true, + .parent_dev_ops =3D &vfe_parent_dev_ops, + .hw_ops =3D &csid_ops_980, + .formats =3D &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_sm8750[] =3D { { .name =3D "cam_ahb", @@ -5628,8 +5701,10 @@ static const struct camss_resources sm8750_resources= =3D { .version =3D CAMSS_8750, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8750, + .csid_res =3D csid_res_8750, .icc_res =3D icc_res_sm8750, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8750), + .csid_num =3D ARRAY_SIZE(csid_res_8750), .icc_path_num =3D ARRAY_SIZE(icc_res_sm8750), }; =20 --=20 2.34.1