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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121f23b798asm21162429c88.0.2026.01.13.02.28.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jan 2026 02:28:32 -0800 (PST) From: Hangxiang Ma Date: Tue, 13 Jan 2026 02:28:29 -0800 Subject: [PATCH v2 3/5] media: qcom: camss: csiphy: Add support for v2.3.0 two-phase CSIPHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260113-sm8750-camss-v2-3-e5487b98eada@oss.qualcomm.com> References: <20260113-sm8750-camss-v2-0-e5487b98eada@oss.qualcomm.com> In-Reply-To: <20260113-sm8750-camss-v2-0-e5487b98eada@oss.qualcomm.com> To: Robert Foss , Todor Tomov , Vladimir Zapolskiy , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.14.3 X-Authority-Analysis: v=2.4 cv=BYXVE7t2 c=1 sm=1 tr=0 ts=69661e53 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=UiSUrLz6K6kVaq6zp58A:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: vt1cfW0-HrHzEOAKB__tRpQpPugHspsg X-Proofpoint-GUID: vt1cfW0-HrHzEOAKB__tRpQpPugHspsg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTEzMDA4OCBTYWx0ZWRfX36ilWTCN/ffn 9aWYOO82PBl1j7yIHCp55WcLOqsd0huehzIukN8ZOBqVsFIOETGVDMPv5opqMNOQJmVW0mh5OXe 1wNHSf9zZhlhi/u4X3p8kiVDTK4f1VRCLnX3XiMDRXSXhlquSKXl390B1hSTEu5G3HrmR+2/DpY i5rQRKFTXSB7gvSILogdu+YKgxqaottgya7FTItSUStjV2cmMAlZ4jTZVfkwtN3S7NO3XFqS6ou G3YHKt8AUePgZhenUR5oAYqSDhKokZzuR9aHWNm5fyJD1uUrKTLvS2uuMJxngjHBhBeVlGDm8Mg 2Tzr8klK4bXNHxeTIGXiYlZiSwvgASYna4twwNUXFvbWwA82vZcTFO+bRrgh+sjUp2A0YeLCP4Y Oe7tH8Lam9Gn1wjP66HW6CIHzkGhixzs1M85VXHMbtX8QFltN2oPODa9pxKutUX7nQjas6+QovP wdqO535KmZmaLWPv9aw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-13_02,2026-01-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601130088 Add more detailed resource information for CSIPHY devices in the camss driver along with the support for v2.3.0 in the 2 phase CSIPHY driver that is responsible for the PHY lane register configuration, module reset and interrupt handling. Additionally, generalize the struct name for the lane configuration that had been added for Kaanapali and use it for SM8750 as well as they share the settings. Signed-off-by: Hangxiang Ma --- .../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 5 +- drivers/media/platform/qcom/camss/camss.c | 125 +++++++++++++++++= ++++ 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/dri= vers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index bea8c927a2e3..1c95102a72da 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -684,7 +684,7 @@ csiphy_lane_regs lane_regs_sm8650[] =3D { {0x0c10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, }; =20 -/* 3nm 2PH v 2.4.0 2p5Gbps 4 lane DPHY mode */ +/* 3nm 2PH v 2.3.0/2.4.0 2p5Gbps 4 lane DPHY mode */ static const struct csiphy_lane_regs lane_regs_2_4_0[] =3D { /* LN 0 */ @@ -1134,6 +1134,7 @@ static bool csiphy_is_gen2(u32 version) case CAMSS_845: case CAMSS_8550: case CAMSS_8650: + case CAMSS_8750: case CAMSS_8775P: case CAMSS_KAANAPALI: case CAMSS_X1E80100: @@ -1250,7 +1251,9 @@ static int csiphy_init(struct csiphy_device *csiphy) regs->lane_regs =3D &lane_regs_sa8775p[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_sa8775p); break; + case CAMSS_8750: case CAMSS_KAANAPALI: + /* CSPHY v2.4.0 is backward compatible with v2.3.0 settings */ regs->lane_regs =3D &lane_regs_2_4_0[0]; regs->lane_array_size =3D ARRAY_SIZE(lane_regs_2_4_0); regs->offset =3D 0x1000; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 56f20daeca3e..1f9a91178002 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -4066,6 +4066,129 @@ static const struct resources_icc icc_res_sa8775p[]= =3D { }, }; =20 +static const struct camss_subdev_resources csiphy_res_8750[] =3D { + /* CSIPHY0 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy0-0p9", .init_load_uA =3D 148000 }, + { .supply =3D "vdd-csiphy0-1p2", .init_load_uA =3D 14660 } + }, + .clock =3D { "csiphy0", "csiphy0_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy0" }, + .interrupt =3D { "csiphy0" }, + .csiphy =3D { + .id =3D 0, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY1 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy1-0p9", .init_load_uA =3D 148000 }, + { .supply =3D "vdd-csiphy1-1p2", .init_load_uA =3D 14660 } + }, + .clock =3D { "csiphy1", "csiphy1_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy1" }, + .interrupt =3D { "csiphy1" }, + .csiphy =3D { + .id =3D 1, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY2 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy2-0p9", .init_load_uA =3D 148000 }, + { .supply =3D "vdd-csiphy2-1p2", .init_load_uA =3D 14660 } + }, + .clock =3D { "csiphy2", "csiphy2_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy2" }, + .interrupt =3D { "csiphy2" }, + .csiphy =3D { + .id =3D 2, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY3 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy3-0p9", .init_load_uA =3D 148000 }, + { .supply =3D "vdd-csiphy3-1p2", .init_load_uA =3D 14660 } + }, + .clock =3D { "csiphy3", "csiphy3_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy3" }, + .interrupt =3D { "csiphy3" }, + .csiphy =3D { + .id =3D 3, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY4 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy4-0p9", .init_load_uA =3D 148000 }, + { .supply =3D "vdd-csiphy4-1p2", .init_load_uA =3D 14660 } + }, + .clock =3D { "csiphy4", "csiphy4_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy4" }, + .interrupt =3D { "csiphy4" }, + .csiphy =3D { + .id =3D 4, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, + /* CSIPHY5 */ + { + .regulators =3D { + { .supply =3D "vdd-csiphy5-0p9", .init_load_uA =3D 148000 }, + { .supply =3D "vdd-csiphy5-1p2", .init_load_uA =3D 14660 } + }, + .clock =3D { "csiphy5", "csiphy5_timer", + "cpas_ahb", "cpas_fast_ahb" }, + .clock_rate =3D { { 400000000, 480000000 }, + { 400000000 }, + { 0 }, + { 0 } }, + .reg =3D { "csiphy5" }, + .interrupt =3D { "csiphy5" }, + .csiphy =3D { + .id =3D 5, + .hw_ops =3D &csiphy_ops_3ph_1_0, + .formats =3D &csiphy_formats_sdm845 + } + }, +}; + static const struct resources_icc icc_res_sm8750[] =3D { { .name =3D "cam_ahb", @@ -5504,7 +5627,9 @@ static const struct camss_resources sm8650_resources = =3D { static const struct camss_resources sm8750_resources =3D { .version =3D CAMSS_8750, .pd_name =3D "top", + .csiphy_res =3D csiphy_res_8750, .icc_res =3D icc_res_sm8750, + .csiphy_num =3D ARRAY_SIZE(csiphy_res_8750), .icc_path_num =3D ARRAY_SIZE(icc_res_sm8750), }; =20 --=20 2.34.1