From nobody Tue Feb 10 08:01:05 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24A9C2D3A89 for ; Mon, 12 Jan 2026 23:21:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768260065; cv=none; b=V5MBOHCm5th75ZAeHSNsPEufatwT7X50aYoJ+0mHVZxeGLX5ZKg/g3jDQYwxlGRMwl4yliLrWmWI1zsvY0t1O3QInZWfg6iCWpbPSUw/CiT9xRQwXZsbtwLRU9No8L5qpREDB+zseczHcNvvChbzfwmaMBOiZhoqcKC8IfLVPag= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768260065; c=relaxed/simple; bh=N/45R8k7JLAj5M8vEcsZT9PpjiCli8tPJhGoj6rMhzA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UUutQdu9Qy9E3R+ezNO4aTQD8ArsAWzwBlrhd8FhIbgNseikMbLYR5DxxA4WtAzwh7T1YlR7fqzDDT4OyijT0/amfaQtv80DoRiKV0M+IcRLxRoHTVJwomlcDo4uq1Tj8NkP1ujSeCM6FkPOH56pKcQ8DYVh8H+ARO2x+Em2/OM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=EXpz4R2d; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="EXpz4R2d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1768260062; bh=N/45R8k7JLAj5M8vEcsZT9PpjiCli8tPJhGoj6rMhzA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=EXpz4R2dyrIzUBKW0EQ7lrcrQfWJbDh0U/phBPyka3G5lhMc+dpiGf0aqodpDjZcE BoAMlkh/+8ZV3rZbBs54bMnzmxWZjipnbuCu0v+RhZ0Vk0fCiiMGi5xkTZF+N57EwT q7/tUWwuodphuRwh2OjBjhNB7sHBt0pIhQObHwboCaJKPo8sM8euxP5012ocgh+RYd mgA/eJV7f1yzQPm5nIAIloPLp6WGWYOYtF2J9Wu8l8+gsi0Ibvdw1lCbtDX6vvDI5u wSntGgHH/DmrzA1bVO9YH1IIYMRotZizPRMzTSBpX+iZxiSX9lLITbXfYI1owY7fMU mAd/srgBKuy1A== Received: from localhost (unknown [82.79.138.145]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7688117E1513; Tue, 13 Jan 2026 00:21:02 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 13 Jan 2026 01:20:52 +0200 Subject: [PATCH v6 05/11] phy: rockchip: samsung-hdptx: Enable lane output in common helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260113-phy-hdptx-frl-v6-5-8d5f97419c0b@collabora.com> References: <20260113-phy-hdptx-frl-v6-0-8d5f97419c0b@collabora.com> In-Reply-To: <20260113-phy-hdptx-frl-v6-0-8d5f97419c0b@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , Neil Armstrong Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.3 In preparation to support FRL mode, move the PHY lane output enablement from the TMDS specific configuration to the common *_post_enable_lane() helper and make sure it gets turned off in *_phy_disable(). Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 3c6eb6dbadd0..33ebe63cdf1e 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -797,6 +797,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_ph= y *hdptx) HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); + ret =3D regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, (val & HDPTX_O_PHY_RDY) && (val & HDPTX_O_PLL_LOCK_DONE), @@ -850,6 +852,7 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy *h= dptx) usleep_range(20, 30); reset_control_deassert(hdptx->rsts[RST_APB].rstc); =20 + regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0); regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); regmap_write(hdptx->regmap, SB_REG(0110), 0x1); @@ -1027,7 +1030,6 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk_= hdptx_phy *hdptx) } =20 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); - regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); =20 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_lane_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_lane_init_seq); --=20 2.52.0