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So in this case, the interrupt to the Synopsys DesignWare Core is coming from the high-speed PHY, so allow the interrupt to reflect that. Signed-off-by: Abel Vesa Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Do= cumentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml index 7d784a648b7d..f879e2e104c4 100644 --- a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -500,7 +500,7 @@ allOf: - const: pwr_event - const: dp_hs_phy_irq - const: dm_hs_phy_irq - - const: ss_phy_irq + - enum: [hs_phy_irq, ss_phy_irq] =20 - if: properties: --=20 2.48.1 From nobody Mon Feb 9 06:31:09 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFE5838F945 for ; Tue, 13 Jan 2026 12:33:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 6 M31 eUSB2 PHYs. All controllers are SNPS DWC3 based, so describe them as flattened DWC3 QCOM nodes. Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/glymur.dtsi | 663 +++++++++++++++++++++++++++++++= +++- 1 file changed, 658 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index eb042541cfe1..53b8ab7580bd 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -750,11 +750,11 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <0>, - <0>, - <0>, - <0>, - <0>, + <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, + <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, <0>, <0>, <0>, @@ -2224,6 +2224,249 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, }; }; =20 + usb_mp_hsphy0: phy@fa1000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0 0x00fa1000 0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; + + status =3D "disabled"; + }; + + usb_mp_hsphy1: phy@fa2000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0 0x00fa2000 0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_2_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; + + status =3D "disabled"; + }; + + usb_mp_qmpphy0: phy@fa3000 { + compatible =3D "qcom,glymur-qmp-usb3-uni-phy"; + reg =3D <0 0x00fa3000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_0_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; + clock-names =3D "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains =3D <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_MP_SS0_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; + reset-names =3D "phy", + "phy_phy"; + + clock-output-names =3D "usb3_uni_phy_0_pipe_clk_src"; + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb_mp_qmpphy1: phy@fa5000 { + compatible =3D "qcom,glymur-qmp-usb3-uni-phy"; + reg =3D <0 0x00fa5000 0 0x2000>; + + clocks =3D <&gcc GCC_USB3_MP_PHY_AUX_CLK>, + <&tcsr TCSR_USB3_1_CLKREF_EN>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; + clock-names =3D "aux", + "clkref", + "ref", + "com_aux", + "pipe"; + + power-domains =3D <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_MP_SS1_PHY_BCR>, + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; + reset-names =3D "phy", + "phy_phy"; + + clock-output-names =3D "usb3_uni_phy_1_pipe_clk_src"; + + #clock-cells =3D <0>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + usb1_ss0_hsphy: phy@fd3000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0 0x00fd3000 0 0x29c>; + #phy-cells =3D <0>; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status =3D "disabled"; + }; + + usb1_ss0_qmpphy: phy@fd5000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0 0x00fd5000 0 0x8000>; + + clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets =3D <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; + + reset-names =3D "phy", + "common"; + + power-domains =3D <&gcc GCC_USB_0_PHY_GDSC>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb1_ss0_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb1_ss0_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb1_ss0_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb1_ss1_hsphy: phy@fdd000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0 0x00fdd000 0 0x29c>; + #phy-cells =3D <0>; + + resets =3D <&gcc GCC_QUSB2PHY_SEC_BCR>; + + status =3D "disabled"; + }; + + usb1_ss1_qmpphy: phy@fde000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0 0x00fde000 0 0x8000>; + + clocks =3D <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_1_CLKREF_EN>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains =3D <&gcc GCC_USB_1_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_PHY_SEC_BCR>, + <&gcc GCC_USB3PHY_PHY_SEC_BCR>; + reset-names =3D "phy", + "common"; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb1_ss1_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb1_ss1_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb1_ss1_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb1_ss1_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_2_hsphy: phy@fa0000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + reg =3D <0 0x00fa0000 0 0x154>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_1_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; + + status =3D "disabled"; + }; + + cnoc_main: interconnect@1500000 { compatible =3D "qcom,glymur-cnoc-main"; reg =3D <0x0 0x01500000 0x0 0x17080>; @@ -3164,6 +3407,416 @@ lpass_ag_noc: interconnect@7e40000 { #interconnect-cells =3D <2>; }; =20 + usb1_ss2_hsphy: phy@88e0000 { + compatible =3D "qcom,glymur-m31-eusb2-phy", + "qcom,sm8750-m31-eusb2-phy"; + + reg =3D <0 0x088e0000 0 0x29c>; + #phy-cells =3D <0>; + + clocks =3D <&tcsr TCSR_USB2_4_CLKREF_EN>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_TERT_BCR>; + + status =3D "disabled"; + }; + + usb1_ss2_qmpphy: phy@88e1000 { + compatible =3D "qcom,glymur-qmp-usb3-dp-phy"; + reg =3D <0 0x088e1000 0 0x8000>; + + clocks =3D <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>, + <&tcsr TCSR_USB4_2_CLKREF_EN>; + clock-names =3D "aux", + "ref", + "com_aux", + "usb3_pipe", + "clkref"; + + power-domains =3D <&gcc GCC_USB_2_PHY_GDSC>; + + resets =3D <&gcc GCC_USB3_PHY_TERT_BCR>, + <&gcc GCC_USB3PHY_PHY_TERT_BCR>; + reset-names =3D "phy", + "common"; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + mode-switch; + orientation-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb1_ss2_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb1_ss2_qmpphy_usb_ss_in: endpoint { + remote-endpoint =3D <&usb1_ss2_dwc3_ss>; + }; + }; + + port@2 { + reg =3D <2>; + + usb1_ss2_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb1_ss0: usb@a600000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0 0x0a600000 0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 90 IRQ_TYPE_EDGE_BOTH>, + <&pdc 60 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains =3D <&gcc GCC_USB30_PRIM_GDSC>; + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + iommus =3D <&apps_smmu 0x1420 0x0>; + phys =3D <&usb1_ss0_hsphy>, + <&usb1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis_u3_susphy_quirk; + snps,usb2-lpm-disable; + + usb-role-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb1_ss0_dwc3_ss: endpoint { + remote-endpoint =3D <&usb1_ss0_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb1_ss1: usb@a800000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0 0x0a800000 0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 88 IRQ_TYPE_EDGE_BOTH>, + <&pdc 87 IRQ_TYPE_EDGE_BOTH>, + <&pdc 76 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets =3D <&gcc GCC_USB30_SEC_BCR>; + power-domains =3D <&gcc GCC_USB30_SEC_GDSC>; + + iommus =3D <&apps_smmu 0x1460 0x0>; + + phys =3D <&usb1_ss1_hsphy>, + <&usb1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis_u3_susphy_quirk; + snps,usb2-lpm-disable; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb1_ss1_dwc3_ss: endpoint { + remote-endpoint =3D <&usb1_ss1_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb1_ss2: usb@a000000 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0 0x0a000000 0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, + <&gcc GCC_USB30_TERT_SLEEP_CLK>, + <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 89 IRQ_TYPE_EDGE_BOTH>, + <&pdc 81 IRQ_TYPE_EDGE_BOTH>, + <&pdc 75 IRQ_TYPE_EDGE_BOTH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + resets =3D <&gcc GCC_USB30_TERT_BCR>; + power-domains =3D <&gcc GCC_USB30_TERT_GDSC>; + + iommus =3D <&apps_smmu 0x420 0x0>; + + phys =3D <&usb1_ss2_hsphy>, + <&usb1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis_u3_susphy_quirk; + snps,usb2-lpm-disable; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg =3D <1>; + + usb1_ss2_dwc3_ss: endpoint { + remote-endpoint =3D <&usb1_ss2_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + usb_2: usb@a2f8800 { + compatible =3D "qcom,glymur-dwc3", "qcom,snps-dwc3"; + reg =3D <0 0x0a200000 0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + assigned-clocks =3D <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <200000000>; + + interrupts-extended =3D <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 92 IRQ_TYPE_EDGE_BOTH>, + <&pdc 57 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "hs_phy_irq"; + + resets =3D <&gcc GCC_USB20_PRIM_BCR>; + + power-domains =3D <&gcc GCC_USB20_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + iommus =3D <&apps_smmu 0x0ce0 0x0>; + + interconnects =3D <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", + "apps-usb"; + + phys =3D <&usb_2_hsphy>; + phy-names =3D "usb2-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis_enblslpm_quirk; + + dr_mode =3D "host"; + + maximum-speed =3D "high-speed"; + + status =3D "disabled"; + }; + + usb_mp: usb@a400000 { + compatible =3D "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; + reg =3D <0 0x0a400000 0 0xfc100>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, + <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "noc_aggr_north", + "noc_aggr_south"; + + interrupts-extended =3D <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event_1", + "pwr_event_2", + "hs_phy_1", + "hs_phy_2", + "dp_hs_phy_1", + "dm_hs_phy_1", + "dp_hs_phy_2", + "dm_hs_phy_2", + "ss_phy_1", + "ss_phy_2"; + + resets =3D <&gcc GCC_USB30_MP_BCR>; + power-domains =3D <&gcc GCC_USB30_MP_GDSC>; + + iommus =3D <&apps_smmu 0xda0 0x0>; + + phys =3D <&usb_mp_hsphy0>, + <&usb_mp_qmpphy0>, + <&usb_mp_hsphy1>, + <&usb_mp_qmpphy1>; + phy-names =3D "usb2-0", + "usb3-0", + "usb2-1", + "usb3-1"; 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Each of these 3 Type-C ports are connected to one of the USB combo PHYs and one of the M31 eUSB2 PHYs. The Type-A is connected to the USB Multi-port controller via one of the M31 eUSB2 PHYs and one combo PHY. The fingerprint reader is connected to the USB_2 controller. All M31 eUSB2 PHYs have associated eUSB2 to USB 2.0 repeaters, which are either part of SMB2360 PMICs or dedicated NXP PTN3222. So enable all needed controllers, PHYs and repeaters, while describing their supplies. Also describe the PMIC glink graph for Type-C connectors. Signed-off-by: Wesley Cheng Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 283 ++++++++++++++++++++++++++++= ++++ 1 file changed, 283 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 7c168e813f1e..3188bfa27bea 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -56,6 +56,97 @@ key-volume-up { }; }; =20 + pmic-glink { + compatible =3D "qcom,glymur-pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint =3D <&usb1_ss0_qmpphy_out>; + }; + }; + }; + }; + + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in1: endpoint { + remote-endpoint =3D <&usb1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in1: endpoint { + remote-endpoint =3D <&usb1_ss1_qmpphy_out>; + }; + }; + }; + }; + + connector@2 { + compatible =3D "usb-c-connector"; + reg =3D <2>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in2: endpoint { + remote-endpoint =3D <&usb1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss_in2: endpoint { + remote-endpoint =3D <&usb1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + vreg_nvme: regulator-nvme { compatible =3D "regulator-fixed"; =20 @@ -331,6 +422,72 @@ trip1 { }; }; =20 +&i2c5 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + ptn3222_0: redriver@43 { + compatible =3D "nxp,ptn3222"; + reg =3D <0x43>; + + reset-gpios =3D <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd3v3-supply =3D <&vreg_l8b_e0_1p50>; + vdd1v8-supply =3D <&vreg_l15b_e0_1p8>; + + #phy-cells =3D <0>; + }; + + ptn3222_1: redriver@4f { + compatible =3D "nxp,ptn3222"; + reg =3D <0x4f>; + + reset-gpios =3D <&tlmm 184 GPIO_ACTIVE_LOW>; + + vdd3v3-supply =3D <&vreg_l8b_e0_1p50>; + vdd1v8-supply =3D <&vreg_l15b_e0_1p8>; + + #phy-cells =3D <0>; + }; + + ptn3222_2: redriver@47 { + compatible =3D "nxp,ptn3222"; + reg =3D <0x47>; + + reset-gpios =3D <&tlmm 9 GPIO_ACTIVE_LOW>; + + vdd3v3-supply =3D <&vreg_l8b_e0_1p50>; + vdd1v8-supply =3D <&vreg_l15b_e0_1p8>; + + #phy-cells =3D <0>; + }; +}; + +&smb2370_j_e2_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_e0_1p8>; + vdd3-supply =3D <&vreg_l7b_e0_2p79>; +}; + +&smb2370_k_e2_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_e0_1p8>; + vdd3-supply =3D <&vreg_l7b_e0_2p79>; +}; + +&smb2370_l_e2_eusb2_repeater { + vdd18-supply =3D <&vreg_l15b_e0_1p8>; + vdd3-supply =3D <&vreg_l7b_e0_2p79>; +}; + +&usb1_ss0_hsphy { + vdd-supply =3D <&vreg_l3f_e0_0p72>; + vdda12-supply =3D <&vreg_l4h_e0_1p2>; + + phys =3D <&smb2370_j_e2_eusb2_repeater>; + + status =3D "okay"; +}; + &tlmm { gpio-reserved-ranges =3D <4 4>, /* EC TZ Secure I3C */ <10 2>, /* OOB UART */ @@ -858,3 +1015,129 @@ &pcie6_port0 { reset-gpios =3D <&tlmm 149 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 151 GPIO_ACTIVE_LOW>; }; + +&usb1_ss0_qmpphy { + vdda-phy-supply =3D <&vreg_l4h_e0_1p2>; + vdda-pll-supply =3D <&vreg_l3f_e0_0p72>; + refgen-supply =3D <&vreg_l2f_e0_0p82>; + + status =3D "okay"; +}; + +&usb1_ss0_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in>; +}; + +&usb1_ss0_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb1_ss0 { + status =3D "okay"; +}; + +&usb1_ss1_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in1>; +}; + +&usb1_ss1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in1>; +}; + +&usb1_ss1_hsphy { + vdd-supply =3D <&vreg_l3f_e0_0p72>; + vdda12-supply =3D <&vreg_l4h_e0_1p2>; + + phys =3D <&smb2370_k_e2_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb1_ss1_qmpphy { + vdda-phy-supply =3D <&vreg_l4h_e0_1p2>; + vdda-pll-supply =3D <&vreg_l1h_e0_0p89>; + refgen-supply =3D <&vreg_l2f_e0_0p82>; + + status =3D "okay"; +}; + +&usb1_ss1 { + status =3D "okay"; +}; + +&usb1_ss2_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss_in2>; +}; + +&usb1_ss2_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in2>; +}; + +&usb1_ss2_hsphy { + vdd-supply =3D <&vreg_l4c_e1_0p72>; + vdda12-supply =3D <&vreg_l4f_e1_1p08>; + + phys =3D <&smb2370_l_e2_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb1_ss2_qmpphy { + vdda-phy-supply =3D <&vreg_l4f_e1_1p08>; + vdda-pll-supply =3D <&vreg_l4c_e1_0p72>; + refgen-supply =3D <&vreg_l1c_e1_0p82>; + + status =3D "okay"; +}; + +&usb1_ss2 { + status =3D "okay"; +}; + +&usb_2 { + status =3D "okay"; +}; + +&usb_2_hsphy { + phys =3D <&ptn3222_2>; + + status =3D "okay"; +}; + +&usb_mp_hsphy0 { + vdd-supply =3D <&vreg_l2h_e0_0p72>; + vdda12-supply =3D <&vreg_l4h_e0_1p2>; + + phys =3D <&ptn3222_0>; + + status =3D "okay"; +}; + +&usb_mp_hsphy1 { + vdd-supply =3D <&vreg_l2h_e0_0p72>; + vdda12-supply =3D <&vreg_l4h_e0_1p2>; + + phys =3D <&ptn3222_1>; + + status =3D "okay"; +}; + +&usb_mp_qmpphy0 { + vdda-phy-supply =3D <&vreg_l4h_e0_1p2>; + vdda-pll-supply =3D <&vreg_l2h_e0_0p72>; + refgen-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&usb_mp_qmpphy1 { + vdda-phy-supply =3D <&vreg_l4h_e0_1p2>; + vdda-pll-supply =3D <&vreg_l2h_e0_0p72>; + refgen-supply =3D <&vreg_l4f_e1_1p08>; + + status =3D "okay"; +}; + +&usb_mp { + status =3D "okay"; +}; --=20 2.48.1