From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62B3B42AB7; Tue, 13 Jan 2026 00:18:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263488; cv=none; b=jDpvSzf/DeDyoQZrZWDCkLMxa3XxWi8c6W9KRBelr6k9Dfv3rbxpi3PeegX5x3DlRO6exVy1sAatpxPUtkZ5qDjBnEfwD9k0YqzE8TuY7oyAN33d3pWvOLgzSZ8d3MQzTc0kvacgATLGVqgB5bNZ4wBX2ngWc+omcksbr/EFmuM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263488; c=relaxed/simple; bh=TzaBrq441dwgCPKohygquSJC95lAZPeg8uqbVOZSB2Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YVheKv1jvC6yVUg5lRNHLJVSB5mkvDjQYw72ipaPfYOa6aL3S7XjYEhPF3Ll2TSjdVBSDlpZjcflF8GiDLTBYFMjFVubCVEISZJ/MQRS4OJVF7SfHwRMay0coe5G9mKudgu1P68WXK04hJ4qJkRW0Hg+mqz/y2PbrA3aOTLXi34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YIfwnDNF; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YIfwnDNF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263480; x=1799799480; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TzaBrq441dwgCPKohygquSJC95lAZPeg8uqbVOZSB2Q=; b=YIfwnDNFqpfrezORsh9cIQx7A3QtADw5pzNQBwQDj74ZZ6fUiO7VzzTa 6MFHvKwH78sbToJoG/h0W/kW91uHHDSkG2PdOL2kyYlf0Z+xLuWIcsqYd whx5EcCaoL+qVHLYePHQCdT8WAI6Apy1+lwSIBTQQ0O/AJ57gNbXGbyMk Vjen8aPiN9WOoQhMTas3IwQex5YDeVms268nZumT+Ayd9q3Ysi6bL96Od /LowRMoZSmpmUEptDLPbdhAZd7l8doOcXzH3UgV4Dfun8IagyHfuIrZpr 4m7AgDc2L0ml1K5pF/ufsOIdrbSdqp+Nei5iEuXxGsoiRHVew5PNIXM84 Q==; X-CSE-ConnectionGUID: BxsrgYnoR7eNgo1nvc/z+Q== X-CSE-MsgGUID: c5GBz381SV6ND9ziXoqAQA== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264176" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264176" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:00 -0800 X-CSE-ConnectionGUID: raGHT03PT1mKbIluRpOwoA== X-CSE-MsgGUID: Qu0pPiUVRaqg67oqMjsM+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042156" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:00 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 01/16] KVM: x86: Rename register accessors to be GPR-specific Date: Mon, 12 Jan 2026 23:53:53 +0000 Message-ID: <20260112235408.168200-2-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the VCPU register state accessors to make them explicitly GPR-only. The existing register accessors operate on the cached VCPU register state. That cache holds GPRs and RIP. RIP has its own interface already. This renaming clarifies GPR access only. No functional changes intended. Signed-off-by: Chang S. Bae --- arch/x86/kvm/svm/svm.c | 8 ++++---- arch/x86/kvm/vmx/nested.c | 20 ++++++++++---------- arch/x86/kvm/vmx/vmx.c | 12 ++++++------ arch/x86/kvm/x86.c | 10 +++++----- arch/x86/kvm/x86.h | 5 ++--- arch/x86/kvm/xen.c | 2 +- 6 files changed, 28 insertions(+), 29 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 24d59ccfa40d..209faa742e98 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -2474,7 +2474,7 @@ static int cr_interception(struct kvm_vcpu *vcpu) err =3D 0; if (cr >=3D 16) { /* mov to cr */ cr -=3D 16; - val =3D kvm_register_read(vcpu, reg); + val =3D kvm_gpr_read(vcpu, reg); trace_kvm_cr_write(cr, val); switch (cr) { case 0: @@ -2520,7 +2520,7 @@ static int cr_interception(struct kvm_vcpu *vcpu) kvm_queue_exception(vcpu, UD_VECTOR); return 1; } - kvm_register_write(vcpu, reg, val); + kvm_gpr_write(vcpu, reg, val); trace_kvm_cr_read(cr, val); } return kvm_complete_insn_gp(vcpu, err); @@ -2592,9 +2592,9 @@ static int dr_interception(struct kvm_vcpu *vcpu) dr =3D svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0; if (dr >=3D 16) { /* mov to DRn */ dr -=3D 16; - err =3D kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg)); + err =3D kvm_set_dr(vcpu, dr, kvm_gpr_read(vcpu, reg)); } else { - kvm_register_write(vcpu, reg, kvm_get_dr(vcpu, dr)); + kvm_gpr_write(vcpu, reg, kvm_get_dr(vcpu, dr)); } =20 return kvm_complete_insn_gp(vcpu, err); diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 6137e5307d0f..b7d5feb4f5bd 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -5275,9 +5275,9 @@ int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsign= ed long exit_qualification, else if (addr_size =3D=3D 0) off =3D (gva_t)sign_extend64(off, 15); if (base_is_valid) - off +=3D kvm_register_read(vcpu, base_reg); + off +=3D kvm_gpr_read(vcpu, base_reg); if (index_is_valid) - off +=3D kvm_register_read(vcpu, index_reg) << scaling; + off +=3D kvm_gpr_read(vcpu, index_reg) << scaling; vmx_get_segment(vcpu, &s, seg_reg); =20 /* @@ -5669,7 +5669,7 @@ static int handle_vmread(struct kvm_vcpu *vcpu) return 1; =20 /* Decode instruction info and find the field to read */ - field =3D kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf)); + field =3D kvm_gpr_read(vcpu, (((instr_info) >> 28) & 0xf)); =20 if (!nested_vmx_is_evmptr12_valid(vmx)) { /* @@ -5718,7 +5718,7 @@ static int handle_vmread(struct kvm_vcpu *vcpu) * on the guest's mode (32 or 64 bit), not on the given field's length. */ if (instr_info & BIT(10)) { - kvm_register_write(vcpu, (((instr_info) >> 3) & 0xf), value); + kvm_gpr_write(vcpu, (((instr_info) >> 3) & 0xf), value); } else { len =3D is_64_bit_mode(vcpu) ? 8 : 4; if (get_vmx_mem_address(vcpu, exit_qualification, @@ -5792,7 +5792,7 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu) return nested_vmx_failInvalid(vcpu); =20 if (instr_info & BIT(10)) - value =3D kvm_register_read(vcpu, (((instr_info) >> 3) & 0xf)); + value =3D kvm_gpr_read(vcpu, (((instr_info) >> 3) & 0xf)); else { len =3D is_64_bit_mode(vcpu) ? 8 : 4; if (get_vmx_mem_address(vcpu, exit_qualification, @@ -5803,7 +5803,7 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu) return kvm_handle_memory_failure(vcpu, r, &e); } =20 - field =3D kvm_register_read(vcpu, (((instr_info) >> 28) & 0xf)); + field =3D kvm_gpr_read(vcpu, (((instr_info) >> 28) & 0xf)); =20 offset =3D get_vmcs12_field_offset(field); if (offset < 0) @@ -6001,7 +6001,7 @@ static int handle_invept(struct kvm_vcpu *vcpu) =20 vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); gpr_index =3D vmx_get_instr_info_reg2(vmx_instruction_info); - type =3D kvm_register_read(vcpu, gpr_index); + type =3D kvm_gpr_read(vcpu, gpr_index); =20 types =3D (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; =20 @@ -6082,7 +6082,7 @@ static int handle_invvpid(struct kvm_vcpu *vcpu) =20 vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); gpr_index =3D vmx_get_instr_info_reg2(vmx_instruction_info); - type =3D kvm_register_read(vcpu, gpr_index); + type =3D kvm_gpr_read(vcpu, gpr_index); =20 types =3D (vmx->nested.msrs.vpid_caps & VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; @@ -6356,7 +6356,7 @@ static bool nested_vmx_exit_handled_cr(struct kvm_vcp= u *vcpu, switch ((exit_qualification >> 4) & 3) { case 0: /* mov to cr */ reg =3D (exit_qualification >> 8) & 15; - val =3D kvm_register_read(vcpu, reg); + val =3D kvm_gpr_read(vcpu, reg); switch (cr) { case 0: if (vmcs12->cr0_guest_host_mask & @@ -6442,7 +6442,7 @@ static bool nested_vmx_exit_handled_vmcs_access(struc= t kvm_vcpu *vcpu, =20 /* Decode instruction info and find the field to access */ vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); - field =3D kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); + field =3D kvm_gpr_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); =20 /* Out-of-range fields always cause a VM exit from L2 to L1 */ if (field >> 15) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 6b96f7aea20b..4320f61aabc2 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -5591,7 +5591,7 @@ static int handle_cr(struct kvm_vcpu *vcpu) reg =3D (exit_qualification >> 8) & 15; switch ((exit_qualification >> 4) & 3) { case 0: /* mov to cr */ - val =3D kvm_register_read(vcpu, reg); + val =3D kvm_gpr_read(vcpu, reg); trace_kvm_cr_write(cr, val); switch (cr) { case 0: @@ -5633,12 +5633,12 @@ static int handle_cr(struct kvm_vcpu *vcpu) WARN_ON_ONCE(enable_unrestricted_guest); =20 val =3D kvm_read_cr3(vcpu); - kvm_register_write(vcpu, reg, val); + kvm_gpr_write(vcpu, reg, val); trace_kvm_cr_read(cr, val); return kvm_skip_emulated_instruction(vcpu); case 8: val =3D kvm_get_cr8(vcpu); - kvm_register_write(vcpu, reg, val); + kvm_gpr_write(vcpu, reg, val); trace_kvm_cr_read(cr, val); return kvm_skip_emulated_instruction(vcpu); } @@ -5708,10 +5708,10 @@ static int handle_dr(struct kvm_vcpu *vcpu) =20 reg =3D DEBUG_REG_ACCESS_REG(exit_qualification); if (exit_qualification & TYPE_MOV_FROM_DR) { - kvm_register_write(vcpu, reg, kvm_get_dr(vcpu, dr)); + kvm_gpr_write(vcpu, reg, kvm_get_dr(vcpu, dr)); err =3D 0; } else { - err =3D kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg)); + err =3D kvm_set_dr(vcpu, dr, kvm_gpr_read(vcpu, reg)); } =20 out: @@ -6070,7 +6070,7 @@ static int handle_invpcid(struct kvm_vcpu *vcpu) =20 vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); gpr_index =3D vmx_get_instr_info_reg2(vmx_instruction_info); - type =3D kvm_register_read(vcpu, gpr_index); + type =3D kvm_gpr_read(vcpu, gpr_index); =20 /* According to the Intel instruction reference, the memory operand * is read even if it isn't needed (e.g., for type=3D=3Dall) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index ff8812f3a129..3256ad507265 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2080,8 +2080,8 @@ static int complete_fast_rdmsr(struct kvm_vcpu *vcpu) static int complete_fast_rdmsr_imm(struct kvm_vcpu *vcpu) { if (!vcpu->run->msr.error) - kvm_register_write(vcpu, vcpu->arch.cui_rdmsr_imm_reg, - vcpu->run->msr.data); + kvm_gpr_write(vcpu, vcpu->arch.cui_rdmsr_imm_reg, + vcpu->run->msr.data); =20 return complete_fast_msr_access(vcpu); } @@ -2135,7 +2135,7 @@ static int __kvm_emulate_rdmsr(struct kvm_vcpu *vcpu,= u32 msr, int reg, kvm_rax_write(vcpu, data & -1u); kvm_rdx_write(vcpu, (data >> 32) & -1u); } else { - kvm_register_write(vcpu, reg, data); + kvm_gpr_write(vcpu, reg, data); } } else { /* MSR read failed? See if we should ask user space */ @@ -2193,7 +2193,7 @@ EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_emulate_wrmsr); =20 int kvm_emulate_wrmsr_imm(struct kvm_vcpu *vcpu, u32 msr, int reg) { - return __kvm_emulate_wrmsr(vcpu, msr, kvm_register_read(vcpu, reg)); + return __kvm_emulate_wrmsr(vcpu, msr, kvm_gpr_read(vcpu, reg)); } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_emulate_wrmsr_imm); =20 @@ -2297,7 +2297,7 @@ EXPORT_SYMBOL_FOR_KVM_INTERNAL(handle_fastpath_wrmsr); =20 fastpath_t handle_fastpath_wrmsr_imm(struct kvm_vcpu *vcpu, u32 msr, int r= eg) { - return __handle_fastpath_wrmsr(vcpu, msr, kvm_register_read(vcpu, reg)); + return __handle_fastpath_wrmsr(vcpu, msr, kvm_gpr_read(vcpu, reg)); } EXPORT_SYMBOL_FOR_KVM_INTERNAL(handle_fastpath_wrmsr_imm); =20 diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index fdab0ad49098..7d6c1c31539f 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -400,15 +400,14 @@ static inline bool vcpu_match_mmio_gpa(struct kvm_vcp= u *vcpu, gpa_t gpa) return false; } =20 -static inline unsigned long kvm_register_read(struct kvm_vcpu *vcpu, int r= eg) +static inline unsigned long kvm_gpr_read(struct kvm_vcpu *vcpu, int reg) { unsigned long val =3D kvm_register_read_raw(vcpu, reg); =20 return is_64_bit_mode(vcpu) ? val : (u32)val; } =20 -static inline void kvm_register_write(struct kvm_vcpu *vcpu, - int reg, unsigned long val) +static inline void kvm_gpr_write(struct kvm_vcpu *vcpu, int reg, unsigned = long val) { if (!is_64_bit_mode(vcpu)) val =3D (u32)val; diff --git a/arch/x86/kvm/xen.c b/arch/x86/kvm/xen.c index d6b2a665b499..c9700dc88bb1 100644 --- a/arch/x86/kvm/xen.c +++ b/arch/x86/kvm/xen.c @@ -1679,7 +1679,7 @@ int kvm_xen_hypercall(struct kvm_vcpu *vcpu) bool handled =3D false; u8 cpl; =20 - input =3D (u64)kvm_register_read(vcpu, VCPU_REGS_RAX); + input =3D (u64)kvm_gpr_read(vcpu, VCPU_REGS_RAX); =20 /* Hyper-V hypercalls get bit 31 set in EAX */ if ((input & 0x80000000) && --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3471E21CC5C; Tue, 13 Jan 2026 00:18:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263488; cv=none; b=Dm0kFJy0IdOwYpflltAEKD6nH4ovSxZJyEgsEAuBxBg49hpc6XKekM034DShvZgsZOsKuw63yMCfuaVW5+3WKjO332LOg0KniQHvXJS5ZYJ2+HruOuGxX93c2aXKL+fuAPuAR7L2lSNo4iuXhjGg/yl19pJ3SmNIWvjJjcUDwBI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263488; c=relaxed/simple; bh=jfswYib18G9iqzbp5TNF0aK44KVYdgLvSKUmm08NH7I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ryiYPKtWpkjAUY0IyvImq83ZDDSDH9m4CB+pQLM2SLtjJyDzMqQJRbQkQJCmyq8nDhEivYoBYuoL2LSyWepGWnffyQNROg9NNeOAd/ss7QQVUQN7vgGIv+Q3QFH8mTan/DGSszZg3mTv9XwAuVbtHp1shM+BFyU7JN2WFAh6pFA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=hYg1GVvp; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="hYg1GVvp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263487; x=1799799487; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jfswYib18G9iqzbp5TNF0aK44KVYdgLvSKUmm08NH7I=; b=hYg1GVvponVq8Gx20OZYkEVKTLPPe9GUuUo8nImXcjqslpM1mrms9Fkg MzcL7Yz4scJ8BlP8pF5Vg/CanKajxeUToPmcDQ28mWhL1RJPf+wHpZtZ3 wDd+fTKuYmzJdjY78LvnXEL/4P/nKVp2cfVsb+veYVVprMyRZxVfVwUTb yXNNdCBiOsK8mqG7ZRPY2cmiSyn0nlL5qpW4OJtl7Lit1bv89hv2+GUB/ XZUTDIO+m7sm34wFIo/0XC37LPSHnKcRQnzOVAPPeoRZfTrKBSpfAxOcE 8EW2/uNLNeD7bQi9F8HDG0JnMxmbJaMJU+ZDDifw3xiHZ+u+kAASRkT9p A==; X-CSE-ConnectionGUID: 1jEZ6YD1To2SJ8NUVyRbWQ== X-CSE-MsgGUID: eRochI2eSmS4+HZokHX8Dw== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264187" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264187" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:06 -0800 X-CSE-ConnectionGUID: tBImvm6ITSyK3y5PIC4DHA== X-CSE-MsgGUID: QB2kGqNTRZG+ngolEkTY8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042177" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:07 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 02/16] KVM: x86: Refactor GPR accessors to differentiate register access types Date: Mon, 12 Jan 2026 23:53:54 +0000 Message-ID: <20260112235408.168200-3-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the GPR accessors to introduce internal helpers to distinguish between legacy and extended GPRs. Add CONFIG_KVM_APX to selectively enable EGPR support. EGPRs will initially remain unused in the kernel. Thus, the state will not be saved in KVM register cache on every VM exit. Instead, the guest state remains live in hardware registers or is stored in guest fpstate. For now, the EGPR accessors are placeholders to be implemented later. Link: https://lore.kernel.org/7cff2a78-94f3-4746-9833-c2a1bf51eed6@redhat.c= om Suggested-by: Paolo Bonzini Signed-off-by: Chang S. Bae --- V1 -> V2: Move kvm_read_egpr()/kvm_write_egpr() to x86.c (Paolo) --- arch/x86/include/asm/kvm_host.h | 18 ++++++++++++ arch/x86/include/asm/kvm_vcpu_regs.h | 16 +++++++++++ arch/x86/kvm/Kconfig | 4 +++ arch/x86/kvm/x86.c | 41 ++++++++++++++++++++++++++++ arch/x86/kvm/x86.h | 19 +++++++++++-- 5 files changed, 96 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 5a3bfa293e8b..9dedb8d77222 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -212,6 +212,24 @@ enum { VCPU_SREG_GS, VCPU_SREG_TR, VCPU_SREG_LDTR, +#ifdef CONFIG_X86_64 + VCPU_XREG_R16 =3D __VCPU_XREG_R16, + VCPU_XREG_R17 =3D __VCPU_XREG_R17, + VCPU_XREG_R18 =3D __VCPU_XREG_R18, + VCPU_XREG_R19 =3D __VCPU_XREG_R19, + VCPU_XREG_R20 =3D __VCPU_XREG_R20, + VCPU_XREG_R21 =3D __VCPU_XREG_R21, + VCPU_XREG_R22 =3D __VCPU_XREG_R22, + VCPU_XREG_R23 =3D __VCPU_XREG_R23, + VCPU_XREG_R24 =3D __VCPU_XREG_R24, + VCPU_XREG_R25 =3D __VCPU_XREG_R25, + VCPU_XREG_R26 =3D __VCPU_XREG_R26, + VCPU_XREG_R27 =3D __VCPU_XREG_R27, + VCPU_XREG_R28 =3D __VCPU_XREG_R28, + VCPU_XREG_R29 =3D __VCPU_XREG_R29, + VCPU_XREG_R30 =3D __VCPU_XREG_R30, + VCPU_XREG_R31 =3D __VCPU_XREG_R31, +#endif }; =20 enum exit_fastpath_completion { diff --git a/arch/x86/include/asm/kvm_vcpu_regs.h b/arch/x86/include/asm/kv= m_vcpu_regs.h index 1af2cb59233b..dd0cc171f405 100644 --- a/arch/x86/include/asm/kvm_vcpu_regs.h +++ b/arch/x86/include/asm/kvm_vcpu_regs.h @@ -20,6 +20,22 @@ #define __VCPU_REGS_R13 13 #define __VCPU_REGS_R14 14 #define __VCPU_REGS_R15 15 +#define __VCPU_XREG_R16 16 +#define __VCPU_XREG_R17 17 +#define __VCPU_XREG_R18 18 +#define __VCPU_XREG_R19 19 +#define __VCPU_XREG_R20 20 +#define __VCPU_XREG_R21 21 +#define __VCPU_XREG_R22 22 +#define __VCPU_XREG_R23 23 +#define __VCPU_XREG_R24 24 +#define __VCPU_XREG_R25 25 +#define __VCPU_XREG_R26 26 +#define __VCPU_XREG_R27 27 +#define __VCPU_XREG_R28 28 +#define __VCPU_XREG_R29 29 +#define __VCPU_XREG_R30 30 +#define __VCPU_XREG_R31 31 #endif =20 #endif /* _ASM_X86_KVM_VCPU_REGS_H */ diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig index 278f08194ec8..2b2995188e97 100644 --- a/arch/x86/kvm/Kconfig +++ b/arch/x86/kvm/Kconfig @@ -93,10 +93,14 @@ config KVM_SW_PROTECTED_VM =20 If unsure, say "N". =20 +config KVM_APX + bool + config KVM_INTEL tristate "KVM for Intel (and compatible) processors support" depends on KVM && IA32_FEAT_CTL select X86_FRED if X86_64 + select KVM_APX if X86_64 help Provides support for KVM on processors equipped with Intel's VT extensions, a.k.a. Virtual Machine Extensions (VMX). diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 3256ad507265..9857b4d319ed 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1255,6 +1255,47 @@ static inline u64 kvm_guest_supported_xfd(struct kvm= _vcpu *vcpu) } #endif =20 +#ifdef CONFIG_KVM_APX +static unsigned long kvm_read_egpr(int reg) +{ + return 0; +} + +static void kvm_write_egpr(int reg, unsigned long data) +{ +} + +unsigned long kvm_gpr_read_raw(struct kvm_vcpu *vcpu, int reg) +{ + switch (reg) { + case VCPU_REGS_RAX ... VCPU_REGS_R15: + return kvm_register_read_raw(vcpu, reg); + case VCPU_XREG_R16 ... VCPU_XREG_R31: + return kvm_read_egpr(reg); + default: + WARN_ON_ONCE(1); + } + + return 0; +} +EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_gpr_read_raw); + +void kvm_gpr_write_raw(struct kvm_vcpu *vcpu, int reg, unsigned long val) +{ + switch (reg) { + case VCPU_REGS_RAX ... VCPU_REGS_R15: + kvm_register_write_raw(vcpu, reg, val); + break; + case VCPU_XREG_R16 ... VCPU_XREG_R31: + kvm_write_egpr(reg, val); + break; + default: + WARN_ON_ONCE(1); + } +} +EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_gpr_write_raw); +#endif + int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr) { u64 xcr0 =3D xcr; diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 7d6c1c31539f..19183aa92855 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -400,9 +400,24 @@ static inline bool vcpu_match_mmio_gpa(struct kvm_vcpu= *vcpu, gpa_t gpa) return false; } =20 +#ifdef CONFIG_KVM_APX +unsigned long kvm_gpr_read_raw(struct kvm_vcpu *vcpu, int reg); +void kvm_gpr_write_raw(struct kvm_vcpu *vcpu, int reg, unsigned long val); +#else +static inline unsigned long kvm_gpr_read_raw(struct kvm_vcpu *vcpu, int re= g) +{ + return kvm_register_read_raw(vcpu, reg); +} + +static inline void kvm_gpr_write_raw(struct kvm_vcpu *vcpu, int reg, unsig= ned long val) +{ + kvm_register_write_raw(vcpu, reg, val); +} +#endif + static inline unsigned long kvm_gpr_read(struct kvm_vcpu *vcpu, int reg) { - unsigned long val =3D kvm_register_read_raw(vcpu, reg); + unsigned long val =3D kvm_gpr_read_raw(vcpu, reg); =20 return is_64_bit_mode(vcpu) ? val : (u32)val; } @@ -411,7 +426,7 @@ static inline void kvm_gpr_write(struct kvm_vcpu *vcpu,= int reg, unsigned long v { if (!is_64_bit_mode(vcpu)) val =3D (u32)val; - return kvm_register_write_raw(vcpu, reg, val); + kvm_gpr_write_raw(vcpu, reg, val); } =20 static inline bool kvm_check_has_quirk(struct kvm *kvm, u64 quirk) --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A713E42AB7; Tue, 13 Jan 2026 00:18:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263497; cv=none; b=tE+s61swxb0g5xYGFrE4RbQ+buJ93DxL4OFSrAJI16XVzdr7KB1vBfyRBEeACyVoCe/1+/QKD1d9DpuuefwMSdIekMzXerdSNgf8PFnp8iZyLXaOZfsNcYnBcf2gPCQKpea1jcCCPc9tNqzt3BcnJPX5FkGvLxcwzW86TZMkNks= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263497; c=relaxed/simple; bh=UJfTfUgVJma1z/+48v2CwqmAHQqvXi2ak4IRqDvVblU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=N4mDG/cfQMd3L5PUSgFFIvkcoSZ8LJJyq15YjfVn5+V3cHEATz2nYG19frmzktdsnma62QXBWy0bpjWR32phgCZn3gV6nzHGeUZzhKHGggLdCuKv7gfM9KUw2pvfRifKco87K1DYEOCv9KWE5cRMhJ9R1ojrl7qa3HL+/6ocSl8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gu5okEnP; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gu5okEnP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263495; x=1799799495; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UJfTfUgVJma1z/+48v2CwqmAHQqvXi2ak4IRqDvVblU=; b=gu5okEnPRg7DFEH2UaaXacPKuZS0F8DIueBlYGetyBVEAwCSs5HoZz2P 5hfY7kFYM0g7yTHJV2kGpTw21WwsgBqPrS2IQEesBs0EOJXLzPCrLOjje KI8m2M3fTiF6MhpxOx+VUCvvP8eID8X46j+7FJFOc3+tz9DTuTa8jHFMC PZqt8svffykF0oyxa0mAi/b3ICgMf2TS5kon/vWQA/pRMWyoyUzAZuyoJ gUjLpjMIUVKuejfpR3qIB7XQem0WLSwVz4Nhj2vHKc41kcxEw82coiiwA q23uYkaOK517l2rUfVa671Su9Vf/bT3MeTZVcZ8bIDcYCk3i4p2128PnZ A==; X-CSE-ConnectionGUID: aFVqBrYtQLuXWnfQDwSQUw== X-CSE-MsgGUID: JDE5LxDRRqacKAyLNH7tkA== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264198" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264198" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:11 -0800 X-CSE-ConnectionGUID: 0IpEs106SkyHWDO0QSdbOQ== X-CSE-MsgGUID: C8htxSFBTtKjdxvF7ZrtRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042204" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:11 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 03/16] KVM: x86: Implement accessors for extended GPRs Date: Mon, 12 Jan 2026 23:53:55 +0000 Message-ID: <20260112235408.168200-4-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add helpers to directly read and write EGPRs (R16=E2=80=93R31). Unlike legacy GPRs, EGPRs are not cached in vcpu->arch.regs[]. Their contents remain live in hardware. If preempted, the EGPR state is preserved in the guest XSAVE buffer. The Advanced Performance Extensions (APX) feature introduces EGPRs as an XSAVE-managed state component. The new helpers access the registers directly between kvm_fpu_get() and kvm_fpu_put(). Callers should ensure that EGPRs are enabled before using these helpers. Signed-off-by: Chang S. Bae --- V1 -> V2: Move _kvm_read_egpr()/_kvm_write_egpr() to x86.c (Paolo) --- arch/x86/kvm/x86.c | 70 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9857b4d319ed..edac2ec11e2f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1256,13 +1256,81 @@ static inline u64 kvm_guest_supported_xfd(struct kv= m_vcpu *vcpu) #endif =20 #ifdef CONFIG_KVM_APX +/* + * Accessors for extended general-purpose registers. binutils >=3D 2.43 can + * recognize those register symbols. + */ + +static void _kvm_read_egpr(int reg, unsigned long *data) +{ + /* mov %r16..%r31, %rax */ + switch (reg) { + case __VCPU_XREG_R16: asm(".byte 0xd5, 0x48, 0x89, 0xc0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R17: asm(".byte 0xd5, 0x48, 0x89, 0xc8" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R18: asm(".byte 0xd5, 0x48, 0x89, 0xd0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R19: asm(".byte 0xd5, 0x48, 0x89, 0xd8" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R20: asm(".byte 0xd5, 0x48, 0x89, 0xe0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R21: asm(".byte 0xd5, 0x48, 0x89, 0xe8" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R22: asm(".byte 0xd5, 0x48, 0x89, 0xf0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R23: asm(".byte 0xd5, 0x48, 0x89, 0xf8" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R24: asm(".byte 0xd5, 0x4c, 0x89, 0xc0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R25: asm(".byte 0xd5, 0x4c, 0x89, 0xc8" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R26: asm(".byte 0xd5, 0x4c, 0x89, 0xd0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R27: asm(".byte 0xd5, 0x4c, 0x89, 0xd8" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R28: asm(".byte 0xd5, 0x4c, 0x89, 0xe0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R29: asm(".byte 0xd5, 0x4c, 0x89, 0xe8" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R30: asm(".byte 0xd5, 0x4c, 0x89, 0xf0" : "=3Da"(*data))= ; break; + case __VCPU_XREG_R31: asm(".byte 0xd5, 0x4c, 0x89, 0xf8" : "=3Da"(*data))= ; break; + default: BUG(); + } +} + +static void _kvm_write_egpr(int reg, unsigned long *data) +{ + /* mov %rax, %r16...%r31*/ + switch (reg) { + case __VCPU_XREG_R16: asm(".byte 0xd5, 0x18, 0x89, 0xc0" : : "a"(*data));= break; + case __VCPU_XREG_R17: asm(".byte 0xd5, 0x18, 0x89, 0xc1" : : "a"(*data));= break; + case __VCPU_XREG_R18: asm(".byte 0xd5, 0x18, 0x89, 0xc2" : : "a"(*data));= break; + case __VCPU_XREG_R19: asm(".byte 0xd5, 0x18, 0x89, 0xc3" : : "a"(*data));= break; + case __VCPU_XREG_R20: asm(".byte 0xd5, 0x18, 0x89, 0xc4" : : "a"(*data));= break; + case __VCPU_XREG_R21: asm(".byte 0xd5, 0x18, 0x89, 0xc5" : : "a"(*data));= break; + case __VCPU_XREG_R22: asm(".byte 0xd5, 0x18, 0x89, 0xc6" : : "a"(*data));= break; + case __VCPU_XREG_R23: asm(".byte 0xd5, 0x18, 0x89, 0xc7" : : "a"(*data));= break; + case __VCPU_XREG_R24: asm(".byte 0xd5, 0x19, 0x89, 0xc0" : : "a"(*data));= break; + case __VCPU_XREG_R25: asm(".byte 0xd5, 0x19, 0x89, 0xc1" : : "a"(*data));= break; + case __VCPU_XREG_R26: asm(".byte 0xd5, 0x19, 0x89, 0xc2" : : "a"(*data));= break; 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a="80264208" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264208" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:15 -0800 X-CSE-ConnectionGUID: ZYS+w289R2i/2PUDXq5g8w== X-CSE-MsgGUID: vW/e9uVKQzSnYxFyD0baEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042226" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:16 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 04/16] KVM: VMX: Introduce unified instruction info structure Date: Mon, 12 Jan 2026 23:53:56 +0000 Message-ID: <20260112235408.168200-5-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define a unified data structure that can represent both the legacy and extended VMX instruction information formats. VMX provides per-instruction metadata for VM exits to help decode the attributes of the instruction that triggered the exit. The legacy format, however, only supports up to 16 GPRs and thus cannot represent EGPRs. To support these new registers, VMX introduces an extended 64-bit layout. Instead of maintaining separate storage for each format, a single union structure makes the overall handling simple. The field names are consistent across both layouts. While the presence of certain fields depends on the instruction type, the offsets remain fixed within each format. Signed-off-by: Chang S. Bae --- arch/x86/kvm/vmx/vmx.h | 61 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index bc3ed3145d7e..567320115a5a 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -311,6 +311,67 @@ struct kvm_vmx { u64 *pid_table; }; =20 +/* + * 32-bit layout of the legacy instruction information field. This format + * supports the 16 legacy GPRs. + */ +struct base_insn_info { + u32 scale : 2; /* Scaling factor */ + u32 reserved1 : 1; + u32 reg1 : 4; /* First register index */ + u32 asize : 3; /* Address size */ + u32 is_reg : 1; /* 0: memory, 1: register */ + u32 osize : 2; /* Operand size */ + u32 reserved2 : 2; + u32 seg : 3; /* Segment register index */ + u32 index : 4; /* Index register index */ + u32 index_invalid : 1; /* 0: valid, 1: invalid */ + u32 base : 4; /* Base register index */ + u32 base_invalid : 1; /* 0: valid, 1: invalid */ + u32 reg2 : 4; /* Second register index */ +}; + +/* + * 64-bit layout of the extended instruction information field, which + * supports EGPRs. + */ +struct ext_insn_info { + u64 scale : 2; /* Scaling factor */ + u64 asize : 2; /* Address size */ + u64 is_reg : 1; /* 0: memory, 1: register */ + u64 osize : 2; /* Operand size */ + u64 seg : 3; /* Segment register index */ + u64 index_invalid : 1; /* 0: valid, 1: invalid */ + u64 base_invalid : 1; /* 0: valid, 1: invalid */ + u64 reserved1 : 4; + u64 reg1 : 5; /* First register index */ + u64 reserved2 : 3; + u64 index : 5; /* Index register index */ + u64 reserved3 : 3; + u64 base : 5; /* Base register index */ + u64 reserved4 : 3; + u64 reg2 : 5; /* Second register index */ + u64 reserved5 : 19; +}; + +/* Union for accessing either the legacy or extended format. */ +union insn_info { + struct base_insn_info base; + struct ext_insn_info ext; + u32 word; + u64 dword; +}; + +/* + * Wrapper structure combining the instruction info and a flag indicating + * whether the extended layout is in use. + */ +struct vmx_insn_info { + /* true if using the extended layout */ + bool extended; + union insn_info info; +}; + static __always_inline struct vcpu_vt *to_vt(struct kvm_vcpu *vcpu) { return &(container_of(vcpu, struct vcpu_vmx, vcpu)->vt); --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED57D222575; Tue, 13 Jan 2026 00:18:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263505; cv=none; b=am1nJEY9C1k5NvlUm/ce9nQjnpSOK1I/1U26ZiEV9HgQYvaxFetSN8GCt647/iaS+Dohm6fgqg+18QjrjPxCu/I0SldyUtHkbIrTmNApNVvYA+yHrMVAsiM43aCNil3AttxuCWF3+6e14gOMiZqCQiAkfxwlkI2icv6kuLmCBsc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263505; c=relaxed/simple; bh=AxtiZdC1mdnLSNJozf0M74rSveKnMdB55Lw6msYv7os=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oQiSnYjS+f8mkMnMP+2FqoRCn6w8Te066qQ+tilwVlx6UJ8gcK18ZOwDHvHbjZJXGfT71mScCBuy1FbM/ZwzDg8RHgbGc9Y4fuB4C8qmaIvmwCDahaHfYUQq1tv9zhuq58U+NTMCSqgflzBQxX9ylWvi+4AZTV4hUdvPhKmmJmk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mbcZrG9g; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mbcZrG9g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263500; x=1799799500; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AxtiZdC1mdnLSNJozf0M74rSveKnMdB55Lw6msYv7os=; b=mbcZrG9gJdovwCVRAmevNmHFsGGT9ZkGSgxQoLcgfSWeI6POHwooHaC3 zgVbLhiaNKssZGTM51BBcBzzu2YQrU+OWEMCo1nr5RXjg8B8X31x5lb6r pu0nIjBJPiinDE4OWnBfM4McnvrHdGpTeHA43gPOevVJW4AKWpb+TL6MQ 4wYlPXnqNsMGV/lTNrcHSCv0jnqbpj/QKCEQvmAMGSPsmT+3lekayF8C7 J6qaq2ECDu3ifzPajnDEcQdtCaI4V3/JgCQbee5wxKv8wtRmzIzgY5tN0 nenNdEdE2oHRjgiP/Yqlj36N70eJkCS2GKFCEcpuCfkgw/GJu1wg/i/VO w==; X-CSE-ConnectionGUID: DlgKPieCTne9id+iJ0v4HA== X-CSE-MsgGUID: YTuA9pg3SfCmPu63iz1WQg== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264217" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264217" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:19 -0800 X-CSE-ConnectionGUID: LJ/yjpUmTf6ILniLOyVVkA== X-CSE-MsgGUID: PW50k+rJRWGQwycl0g2E7g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042251" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:20 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 05/16] KVM: VMX: Refactor instruction information retrieval Date: Mon, 12 Jan 2026 23:53:57 +0000 Message-ID: <20260112235408.168200-6-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce helpers to convert and extract exited instruction attributes, preparing for EGPR support and deprecating some existing helpers. Previously, VMX exit handlers directly decoded the raw VMCS field, resulting in duplicated logic and assumption tied to the legacy layout. With the unified structure, handlers can convert raw data into a structure form and access each instruction attribute by field name. The helper will later determine the format based on the VCPU configuration. For now, there is no functional change since only the legacy layout is used. Signed-off-by: Chang S. Bae --- V1 -> V2: Remove the unused function argument (Chao) --- arch/x86/kvm/vmx/nested.c | 73 +++++++++++++++++++-------------------- arch/x86/kvm/vmx/nested.h | 2 +- arch/x86/kvm/vmx/vmx.c | 14 ++++---- arch/x86/kvm/vmx/vmx.h | 23 ++++++------ 4 files changed, 57 insertions(+), 55 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index b7d5feb4f5bd..144012dd9599 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -5239,7 +5239,7 @@ static void nested_vmx_triple_fault(struct kvm_vcpu *= vcpu) * #UD, #GP, or #SS. */ int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualific= ation, - u32 vmx_instruction_info, bool wr, int len, gva_t *ret) + struct vmx_insn_info info, bool wr, int len, gva_t *ret) { gva_t off; bool exn; @@ -5253,14 +5253,14 @@ int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsi= gned long exit_qualification, * For how an actual address is calculated from all these components, * refer to Vol. 1, "Operand Addressing". */ - int scaling =3D vmx_instruction_info & 3; - int addr_size =3D (vmx_instruction_info >> 7) & 7; - bool is_reg =3D vmx_instruction_info & (1u << 10); - int seg_reg =3D (vmx_instruction_info >> 15) & 7; - int index_reg =3D (vmx_instruction_info >> 18) & 0xf; - bool index_is_valid =3D !(vmx_instruction_info & (1u << 22)); - int base_reg =3D (vmx_instruction_info >> 23) & 0xf; - bool base_is_valid =3D !(vmx_instruction_info & (1u << 27)); + int scaling =3D insn_attr(info, scale); + int addr_size =3D insn_attr(info, asize); + bool is_reg =3D insn_attr(info, is_reg); + int seg_reg =3D insn_attr(info, seg); + int index_reg =3D insn_attr(info, index); + bool index_is_valid =3D !insn_attr(info, index_invalid); + int base_reg =3D insn_attr(info, base); + bool base_is_valid =3D !insn_attr(info, base_invalid); =20 if (is_reg) { kvm_queue_exception(vcpu, UD_VECTOR); @@ -5371,7 +5371,7 @@ static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu= , gpa_t *vmpointer, int r; =20 if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), - vmcs_read32(VMX_INSTRUCTION_INFO), false, + vmx_get_insn_info(), false, sizeof(*vmpointer), &gva)) { *ret =3D 1; return -EINVAL; @@ -5656,7 +5656,7 @@ static int handle_vmread(struct kvm_vcpu *vcpu) struct vmcs12 *vmcs12 =3D is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) : get_vmcs12(vcpu); unsigned long exit_qualification =3D vmx_get_exit_qual(vcpu); - u32 instr_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); + struct vmx_insn_info info =3D vmx_get_insn_info(); struct vcpu_vmx *vmx =3D to_vmx(vcpu); struct x86_exception e; unsigned long field; @@ -5669,7 +5669,7 @@ static int handle_vmread(struct kvm_vcpu *vcpu) return 1; =20 /* Decode instruction info and find the field to read */ - field =3D kvm_gpr_read(vcpu, (((instr_info) >> 28) & 0xf)); + field =3D kvm_gpr_read(vcpu, insn_attr(info, reg2)); =20 if (!nested_vmx_is_evmptr12_valid(vmx)) { /* @@ -5717,12 +5717,12 @@ static int handle_vmread(struct kvm_vcpu *vcpu) * Note that the number of bits actually copied is 32 or 64 depending * on the guest's mode (32 or 64 bit), not on the given field's length. */ - if (instr_info & BIT(10)) { - kvm_gpr_write(vcpu, (((instr_info) >> 3) & 0xf), value); + if (insn_attr(info, is_reg)) { + kvm_gpr_write(vcpu, insn_attr(info, reg1), value); } else { len =3D is_64_bit_mode(vcpu) ? 8 : 4; if (get_vmx_mem_address(vcpu, exit_qualification, - instr_info, true, len, &gva)) + info, true, len, &gva)) return 1; /* _system ok, nested_vmx_check_permission has verified cpl=3D0 */ r =3D kvm_write_guest_virt_system(vcpu, gva, &value, len, &e); @@ -5762,7 +5762,7 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu) struct vmcs12 *vmcs12 =3D is_guest_mode(vcpu) ? get_shadow_vmcs12(vcpu) : get_vmcs12(vcpu); unsigned long exit_qualification =3D vmx_get_exit_qual(vcpu); - u32 instr_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); + struct vmx_insn_info info =3D vmx_get_insn_info(); struct vcpu_vmx *vmx =3D to_vmx(vcpu); struct x86_exception e; unsigned long field; @@ -5791,19 +5791,19 @@ static int handle_vmwrite(struct kvm_vcpu *vcpu) get_vmcs12(vcpu)->vmcs_link_pointer =3D=3D INVALID_GPA)) return nested_vmx_failInvalid(vcpu); =20 - if (instr_info & BIT(10)) - value =3D kvm_gpr_read(vcpu, (((instr_info) >> 3) & 0xf)); + if (insn_attr(info, is_reg)) + value =3D kvm_gpr_read(vcpu, insn_attr(info, reg1)); else { len =3D is_64_bit_mode(vcpu) ? 8 : 4; if (get_vmx_mem_address(vcpu, exit_qualification, - instr_info, false, len, &gva)) + info, false, len, &gva)) return 1; r =3D kvm_read_guest_virt(vcpu, gva, &value, len, &e); if (r !=3D X86EMUL_CONTINUE) return kvm_handle_memory_failure(vcpu, r, &e); } =20 - field =3D kvm_gpr_read(vcpu, (((instr_info) >> 28) & 0xf)); + field =3D kvm_gpr_read(vcpu, insn_attr(info, reg2)); =20 offset =3D get_vmcs12_field_offset(field); if (offset < 0) @@ -5951,7 +5951,7 @@ static int handle_vmptrld(struct kvm_vcpu *vcpu) static int handle_vmptrst(struct kvm_vcpu *vcpu) { unsigned long exit_qual =3D vmx_get_exit_qual(vcpu); - u32 instr_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); + struct vmx_insn_info info =3D vmx_get_insn_info(); gpa_t current_vmptr =3D to_vmx(vcpu)->nested.current_vmptr; struct x86_exception e; gva_t gva; @@ -5963,7 +5963,7 @@ static int handle_vmptrst(struct kvm_vcpu *vcpu) if (unlikely(nested_vmx_is_evmptr12_valid(to_vmx(vcpu)))) return 1; =20 - if (get_vmx_mem_address(vcpu, exit_qual, instr_info, + if (get_vmx_mem_address(vcpu, exit_qual, info, true, sizeof(gpa_t), &gva)) return 1; /* *_system ok, nested_vmx_check_permission has verified cpl=3D0 */ @@ -5979,15 +5979,16 @@ static int handle_vmptrst(struct kvm_vcpu *vcpu) static int handle_invept(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx =3D to_vmx(vcpu); - u32 vmx_instruction_info, types; unsigned long type, roots_to_free; + struct vmx_insn_info info; struct kvm_mmu *mmu; gva_t gva; struct x86_exception e; struct { u64 eptp, gpa; } operand; - int i, r, gpr_index; + u32 types; + int i, r; =20 if (!(vmx->nested.msrs.secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) || @@ -5999,9 +6000,8 @@ static int handle_invept(struct kvm_vcpu *vcpu) if (!nested_vmx_check_permission(vcpu)) return 1; =20 - vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); - gpr_index =3D vmx_get_instr_info_reg2(vmx_instruction_info); - type =3D kvm_gpr_read(vcpu, gpr_index); + info =3D vmx_get_insn_info(); + type =3D kvm_gpr_read(vcpu, insn_attr(info, reg2)); =20 types =3D (vmx->nested.msrs.ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6; =20 @@ -6012,7 +6012,7 @@ static int handle_invept(struct kvm_vcpu *vcpu) * operand is read even if it isn't needed (e.g., for type=3D=3Dglobal) */ if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), - vmx_instruction_info, false, sizeof(operand), &gva)) + info, false, sizeof(operand), &gva)) return 1; r =3D kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); if (r !=3D X86EMUL_CONTINUE) @@ -6059,7 +6059,7 @@ static int handle_invept(struct kvm_vcpu *vcpu) static int handle_invvpid(struct kvm_vcpu *vcpu) { struct vcpu_vmx *vmx =3D to_vmx(vcpu); - u32 vmx_instruction_info; + struct vmx_insn_info info; unsigned long type, types; gva_t gva; struct x86_exception e; @@ -6068,7 +6068,7 @@ static int handle_invvpid(struct kvm_vcpu *vcpu) u64 gla; } operand; u16 vpid02; - int r, gpr_index; + int r; =20 if (!(vmx->nested.msrs.secondary_ctls_high & SECONDARY_EXEC_ENABLE_VPID) || @@ -6080,9 +6080,8 @@ static int handle_invvpid(struct kvm_vcpu *vcpu) if (!nested_vmx_check_permission(vcpu)) return 1; =20 - vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); - gpr_index =3D vmx_get_instr_info_reg2(vmx_instruction_info); - type =3D kvm_gpr_read(vcpu, gpr_index); + info =3D vmx_get_insn_info(); + type =3D kvm_gpr_read(vcpu, insn_attr(info, reg2)); =20 types =3D (vmx->nested.msrs.vpid_caps & VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8; @@ -6095,7 +6094,7 @@ static int handle_invvpid(struct kvm_vcpu *vcpu) * operand is read even if it isn't needed (e.g., for type=3D=3Dglobal) */ if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), - vmx_instruction_info, false, sizeof(operand), &gva)) + info, false, sizeof(operand), &gva)) return 1; r =3D kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e); if (r !=3D X86EMUL_CONTINUE) @@ -6433,7 +6432,7 @@ static bool nested_vmx_exit_handled_encls(struct kvm_= vcpu *vcpu, static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, gpa_t bitmap) { - u32 vmx_instruction_info; + struct vmx_insn_info info; unsigned long field; u8 b; =20 @@ -6441,8 +6440,8 @@ static bool nested_vmx_exit_handled_vmcs_access(struc= t kvm_vcpu *vcpu, return true; =20 /* Decode instruction info and find the field to access */ - vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); - field =3D kvm_gpr_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf)); + info =3D vmx_get_insn_info(); + field =3D kvm_gpr_read(vcpu, insn_attr(info, reg2)); =20 /* Out-of-range fields always cause a VM exit from L2 to L1 */ if (field >> 15) diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index 983484d42ebf..e54f4e7b3664 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -50,7 +50,7 @@ void nested_sync_vmcs12_to_shadow(struct kvm_vcpu *vcpu); int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data); int vmx_get_vmx_msr(struct nested_vmx_msrs *msrs, u32 msr_index, u64 *pdat= a); int get_vmx_mem_address(struct kvm_vcpu *vcpu, unsigned long exit_qualific= ation, - u32 vmx_instruction_info, bool wr, int len, gva_t *ret); + struct vmx_insn_info info, bool wr, int len, gva_t *ret); void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu *vcpu); bool nested_vmx_check_io_bitmaps(struct kvm_vcpu *vcpu, unsigned int port, int size); diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 4320f61aabc2..10479114fd1c 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -6054,29 +6054,27 @@ static int handle_monitor_trap(struct kvm_vcpu *vcp= u) =20 static int handle_invpcid(struct kvm_vcpu *vcpu) { - u32 vmx_instruction_info; + struct vmx_insn_info info; unsigned long type; gva_t gva; struct { u64 pcid; u64 gla; } operand; - int gpr_index; =20 if (!guest_cpu_cap_has(vcpu, X86_FEATURE_INVPCID)) { kvm_queue_exception(vcpu, UD_VECTOR); return 1; } =20 - vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); - gpr_index =3D vmx_get_instr_info_reg2(vmx_instruction_info); - type =3D kvm_gpr_read(vcpu, gpr_index); + info =3D vmx_get_insn_info(); + type =3D kvm_gpr_read(vcpu, insn_attr(info, reg2)); =20 /* According to the Intel instruction reference, the memory operand * is read even if it isn't needed (e.g., for type=3D=3Dall) */ if (get_vmx_mem_address(vcpu, vmx_get_exit_qual(vcpu), - vmx_instruction_info, false, + info, false, sizeof(operand), &gva)) return 1; =20 @@ -6219,7 +6217,9 @@ static int handle_notify(struct kvm_vcpu *vcpu) =20 static int vmx_get_msr_imm_reg(struct kvm_vcpu *vcpu) { - return vmx_get_instr_info_reg(vmcs_read32(VMX_INSTRUCTION_INFO)); + struct vmx_insn_info info =3D vmx_get_insn_info(); + + return insn_attr(info, reg1); } =20 static int handle_rdmsr_imm(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 567320115a5a..2bb3ac8c5b8b 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -372,6 +372,19 @@ struct vmx_insn_info { union insn_info info; }; =20 +static inline struct vmx_insn_info vmx_get_insn_info(void) +{ + struct vmx_insn_info insn; + + insn.extended =3D false; + insn.info.word =3D vmcs_read32(VMX_INSTRUCTION_INFO); + + return insn; +} + +#define insn_attr(insn, attr) \ + ((insn).extended ? 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Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 06/16] KVM: VMX: Refactor GPR index retrieval from exit qualification Date: Mon, 12 Jan 2026 23:53:58 +0000 Message-ID: <20260112235408.168200-7-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a helper to extract the GPR index from the exit qualification field. VMX exit qualification, in addition to the VMX instruction info field, encodes a GPR index. With the introduction of EGPRs, this field is extended by a previously reserved bit position. This refactoring centralizes the logic so that future updates can handle the extended GPR index without code duplication. Since the VMCS exit qualification is cached in VCPU state, it is safe for the helper to access it directly via the VCPU pointer. This argument will also be used later to determine EGPR availability. No functional change intended. Signed-off-by: Chang S. Bae --- arch/x86/kvm/vmx/nested.c | 2 +- arch/x86/kvm/vmx/vmx.c | 2 +- arch/x86/kvm/vmx/vmx.h | 5 +++++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 144012dd9599..46c12b64e819 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -6354,7 +6354,7 @@ static bool nested_vmx_exit_handled_cr(struct kvm_vcp= u *vcpu, =20 switch ((exit_qualification >> 4) & 3) { case 0: /* mov to cr */ - reg =3D (exit_qualification >> 8) & 15; + reg =3D vmx_get_exit_qual_gpr(vcpu); val =3D kvm_gpr_read(vcpu, reg); switch (cr) { case 0: diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 10479114fd1c..29d588c3b3b1 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -5588,7 +5588,7 @@ static int handle_cr(struct kvm_vcpu *vcpu) =20 exit_qualification =3D vmx_get_exit_qual(vcpu); cr =3D exit_qualification & 15; - reg =3D (exit_qualification >> 8) & 15; + reg =3D vmx_get_exit_qual_gpr(vcpu); switch ((exit_qualification >> 4) & 3) { case 0: /* mov to cr */ val =3D kvm_gpr_read(vcpu, reg); diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 2bb3ac8c5b8b..8d3e0aff2e13 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -411,6 +411,11 @@ static __always_inline unsigned long vmx_get_exit_qual= (struct kvm_vcpu *vcpu) return vt->exit_qualification; } =20 +static inline int vmx_get_exit_qual_gpr(struct kvm_vcpu *vcpu) +{ + return (vmx_get_exit_qual(vcpu) >> 8) & 0xf; +} + static __always_inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu) { struct vcpu_vt *vt =3D to_vt(vcpu); --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFA9C42AB7; Tue, 13 Jan 2026 00:18:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263511; cv=none; b=TxAxcKVWjfIpM3jOkjnLpE5eCuD9Q1eo8At4u8KrbhR3ra9URMsy+6X1XezFgrh7bOycoNIsHkIPWlsJ0lq8YAIhdwHPg5VzWRS+hyopNQbW3q7ewkCeIR5uwogAPRZTggth0S0uYG6zhPPsOBF+97PwEmCtUsFyP3Rk8z2bw9s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263511; c=relaxed/simple; bh=9P+wM6gafHW0wSB7dhCz2sdL6IyN88yEg6n5053amAo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=naNSBtHUeFwxAHZ/IAI9nUICrhBQyBRr4qDbzaeRJi/eiD1NCyTL84FGruAlAL3hzEtWVfxru3p0IMFgOs1KTcjmr1fypxxX6gz1ZCZczAq7Bz0S62u4ll2y1l/U9dDnyE0qLkF5ZeoN+yQojNq18s7h/t3cVdvYD2nZYWeqqBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=M3R/dKik; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="M3R/dKik" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263508; x=1799799508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9P+wM6gafHW0wSB7dhCz2sdL6IyN88yEg6n5053amAo=; b=M3R/dKikKbG9mAMUR3jtD8nMpSLmpjMwKGdcC1oizBXSqdK331aT8cwD VZAheyvuvEjaoPrsYE4GljGQJvhSwrWf1Z0AwDpmXRx0mxp1M7ijb47j0 oarDJVlHCesGUfNepmIcFCi83SqG0viPM4yKI75sm6awWyjFH6Y/DnH0n 25tabt8S+/TZLBYo+0+5+NJ41+5oVFlGu+Cfn41nyj5ASPZ0aox3oFsrs H79giryeVZCG3behlpp9T4Kcbal2Ps/nnCzMRLtA4+5+lUgvB2DdTSzPu erzDuUVt+Gi3IhFAwZEoUDUFwqxVUgqYELYGR3hBcxy2Uaidld8rx6wgP w==; X-CSE-ConnectionGUID: haO1s5v+Q8GNOGbwUjvb0A== X-CSE-MsgGUID: 5WhiK3qsQtijeCuZOLFqzQ== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264235" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264235" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:26 -0800 X-CSE-ConnectionGUID: mnbF3JiBT1eUlwQ/TjGHlg== X-CSE-MsgGUID: AeVjomSZTpGFy/CodFlz4A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042260" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:27 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 07/16] KVM: VMX: Support extended register index in exit handling Date: Mon, 12 Jan 2026 23:53:59 +0000 Message-ID: <20260112235408.168200-8-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define the VMCS field offset for the extended instruction information. Then, support 5-bit register indices retrieval from VMCS fields when APX feature is enumerated. The presence of the extended instruction information field is indicated by APX enumeration, regardless of the XCR0.APX bit setting. With APX enumerated, the previously reserved bit in the exit qualification can be referenced safely now. However, there is no guarantee that older implementations always zeroed this bit. Link: https://lore.kernel.org/7bb14722-c036-4835-8ed9-046b4e67909e@redhat.c= om Suggested-by: Paolo Bonzini Signed-off-by: Chang S. Bae --- V1 -> V2: * Switch the change order; putting this ahead of nVMX changes (Chao) * Subsequently, define the field offset here. --- arch/x86/include/asm/vmx.h | 2 ++ arch/x86/kvm/vmx/vmx.h | 23 ++++++++++++++++++++--- 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index c85c50019523..6170251306db 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -264,6 +264,8 @@ enum vmcs_field { PID_POINTER_TABLE_HIGH =3D 0x00002043, GUEST_PHYSICAL_ADDRESS =3D 0x00002400, GUEST_PHYSICAL_ADDRESS_HIGH =3D 0x00002401, + EXTENDED_INSTRUCTION_INFO =3D 0x00002406, + EXTENDED_INSTRUCTION_INFO_HIGH =3D 0x00002407, VMCS_LINK_POINTER =3D 0x00002800, VMCS_LINK_POINTER_HIGH =3D 0x00002801, GUEST_IA32_DEBUGCTL =3D 0x00002802, diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index 8d3e0aff2e13..a24d87aa4f79 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -372,12 +372,26 @@ struct vmx_insn_info { union insn_info info; }; =20 +/* + * The APX enumeration guarantees the presence of the extended fields. + * The host CPUID bit alone is sufficient to rely on it. + */ +static inline bool vmx_insn_info_extended(void) +{ + return static_cpu_has(X86_FEATURE_APX); +} + static inline struct vmx_insn_info vmx_get_insn_info(void) { struct vmx_insn_info insn; =20 - insn.extended =3D false; - insn.info.word =3D vmcs_read32(VMX_INSTRUCTION_INFO); + if (vmx_insn_info_extended()) { + insn.extended =3D true; + insn.info.dword =3D vmcs_read64(EXTENDED_INSTRUCTION_INFO); + } else { + insn.extended =3D false; + insn.info.word =3D vmcs_read32(VMX_INSTRUCTION_INFO); + } =20 return insn; } @@ -413,7 +427,10 @@ static __always_inline unsigned long vmx_get_exit_qual= (struct kvm_vcpu *vcpu) =20 static inline int vmx_get_exit_qual_gpr(struct kvm_vcpu *vcpu) { - return (vmx_get_exit_qual(vcpu) >> 8) & 0xf; + if (vmx_insn_info_extended()) + return (vmx_get_exit_qual(vcpu) >> 8) & 0x1f; + else + return (vmx_get_exit_qual(vcpu) >> 8) & 0xf; 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X-CSE-ConnectionGUID: exihDauyToSPzYors36mMg== X-CSE-MsgGUID: dQ6AaponTY2bRk1MiSmWKg== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264240" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264240" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:29 -0800 X-CSE-ConnectionGUID: dtJk7QaVRQmTVz2svv6iGg== X-CSE-MsgGUID: VWQ6r6GCQ0O96ANkd8+Obw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042263" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:30 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 08/16] KVM: nVMX: Propagate the extended instruction info field Date: Mon, 12 Jan 2026 23:54:00 +0000 Message-ID: <20260112235408.168200-9-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define a new extended_instruction_info field in struct vmcs12 and propagate it to nested VMX. Gate the propagation on the guest APX enumeration which aligns with VMX behavior. Define the CPUID bit for that. Link: https://lore.kernel.org/CABgObfa-vqWCenVvvTAoB773AQ+9a1OOT9n5hjqT=3Dz= ZBDQbb+Q@mail.gmail.com Suggested-by: Chao Gao Signed-off-by: Chang S. Bae --- V1 -> V2: Fix build error by defining APX CPUID bit here, and refine the changelog --- arch/x86/kvm/reverse_cpuid.h | 2 ++ arch/x86/kvm/vmx/nested.c | 6 ++++++ arch/x86/kvm/vmx/vmcs12.c | 1 + arch/x86/kvm/vmx/vmcs12.h | 3 ++- 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 81b4a7acf72e..e538b5444919 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -35,6 +35,7 @@ #define X86_FEATURE_AVX_VNNI_INT16 KVM_X86_FEATURE(CPUID_7_1_EDX, 10) #define X86_FEATURE_PREFETCHITI KVM_X86_FEATURE(CPUID_7_1_EDX, 14) #define X86_FEATURE_AVX10 KVM_X86_FEATURE(CPUID_7_1_EDX, 19) +#define KVM_X86_FEATURE_APX KVM_X86_FEATURE(CPUID_7_1_EDX, 21) =20 /* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */ #define X86_FEATURE_INTEL_PSFD KVM_X86_FEATURE(CPUID_7_2_EDX, 0) @@ -125,6 +126,7 @@ static __always_inline u32 __feature_translate(int x86_= feature) KVM_X86_TRANSLATE_FEATURE(SGX1); KVM_X86_TRANSLATE_FEATURE(SGX2); KVM_X86_TRANSLATE_FEATURE(SGX_EDECCSSA); + KVM_X86_TRANSLATE_FEATURE(APX); KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC); KVM_X86_TRANSLATE_FEATURE(PERFMON_V2); KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL); diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 46c12b64e819..da17e73d2414 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -4747,6 +4747,12 @@ static void prepare_vmcs12(struct kvm_vcpu *vcpu, st= ruct vmcs12 *vmcs12, vmcs12->vm_exit_intr_info =3D exit_intr_info; vmcs12->vm_exit_instruction_len =3D exit_insn_len; vmcs12->vmx_instruction_info =3D vmcs_read32(VMX_INSTRUCTION_INFO); + /* + * The APX enumeration guarantees the presence of the extended + * fields. This CPUID bit alone is sufficient to rely on it. + */ + if (guest_cpu_cap_has(vcpu, X86_FEATURE_APX)) + vmcs12->extended_instruction_info =3D vmcs_read64(EXTENDED_INSTRUCTION_= INFO); =20 /* * According to spec, there's no need to store the guest's diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c index 4233b5ca9461..ea2b690a419e 100644 --- a/arch/x86/kvm/vmx/vmcs12.c +++ b/arch/x86/kvm/vmx/vmcs12.c @@ -53,6 +53,7 @@ const unsigned short vmcs12_field_offsets[] =3D { FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap), FIELD64(ENCLS_EXITING_BITMAP, encls_exiting_bitmap), FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address), + FIELD64(EXTENDED_INSTRUCTION_INFO, extended_instruction_info), FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer), FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl), FIELD64(GUEST_IA32_PAT, guest_ia32_pat), diff --git a/arch/x86/kvm/vmx/vmcs12.h b/arch/x86/kvm/vmx/vmcs12.h index 4ad6b16525b9..2146e45aaade 100644 --- a/arch/x86/kvm/vmx/vmcs12.h +++ b/arch/x86/kvm/vmx/vmcs12.h @@ -71,7 +71,7 @@ struct __packed vmcs12 { u64 pml_address; u64 encls_exiting_bitmap; u64 tsc_multiplier; - u64 padding64[1]; /* room for future expansion */ + u64 extended_instruction_info; /* * To allow migration of L1 (complete with its L2 guests) between * machines of different natural widths (32 or 64 bit), we cannot have @@ -261,6 +261,7 @@ static inline void vmx_check_vmcs12_offsets(void) CHECK_OFFSET(pml_address, 312); CHECK_OFFSET(encls_exiting_bitmap, 320); CHECK_OFFSET(tsc_multiplier, 328); + CHECK_OFFSET(extended_instruction_info, 336); CHECK_OFFSET(cr0_guest_host_mask, 344); CHECK_OFFSET(cr4_guest_host_mask, 352); CHECK_OFFSET(cr0_read_shadow, 360); --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2158142AB7; Tue, 13 Jan 2026 00:18:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263519; cv=none; b=I1HA70JdAJ5NABVdM0pdvhf+8+gQXW6B+62jFJl1Elgjx4KgTGGwscOxQakQWAbCI6AcJDLiiRfHrfWYhBWH/CvUHm9XxRLmuUArFYCQHtJx6deCiyrlWDwITyGchB/eB3R8SII9vB3+l6JonOyepFuJ2Wk8OL51s+pKhOK2KNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263519; c=relaxed/simple; bh=j9NteoQM1X9ErYC0oA1l11qc0KR8u2v6ZijCHhf7BHU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G0jeXtKJ4BNSWHLzHln4ND6eWVj1Txwt3gYhnQeYCpGZl+dPLh3Bk2ACr8OwTao+98P+s5B5nRiMX0NIAk/bUCOO4+QYvSmgOjpkz4QhnHwkzLHxqbmWIJnihynB3HIxH0cG3AL5xIRlWmkT0UmWZ91/eYifaDphWNlE8YpfjuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Cn0AIoKN; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Cn0AIoKN" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263515; x=1799799515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j9NteoQM1X9ErYC0oA1l11qc0KR8u2v6ZijCHhf7BHU=; b=Cn0AIoKNDrGSoj9cPlweuMQ3RdoMt7nenP6V13DBIfOJysswqW12zkuv 98GdALFkQHq2o1Iwq0H/wjKfO/+NT7/MypNuFIsol2MkVnc7OmL5PcIBA sbENeV2e3ItfMDTL0s+d88e1zPACNiT1PlA4RFCEzjZ5NvuWyIXntL+oh 2qvK6KAGsnb8+1L7TuRA/Rn99gFYk1m4TQEBpyJimMMNplKmsn0z8+anq lUr1kM2ePmrVIt+bnSt76pj7TFEIqDjHyWYR4AFVIL1kX3rKYGhBmWGKD 5jFEzV9e+BlfqePTOldyKp+tDFBEVLuRX3pIXRDyZCQsBBhN4AgeF+Tg+ w==; X-CSE-ConnectionGUID: ks5c+8diTba9NtzOus3U/Q== X-CSE-MsgGUID: LatQ91qtQgayUQpoGQgx6w== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264244" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264244" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:32 -0800 X-CSE-ConnectionGUID: COJBFgOUS8OA4hOHTGTLww== X-CSE-MsgGUID: A4hHAnAHS+Sav8Id8VnPtw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042267" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:33 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 09/16] KVM: emulate: Support EGPR accessing and tracking Date: Mon, 12 Jan 2026 23:54:01 +0000 Message-ID: <20260112235408.168200-10-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the emulator context and GPR accessors to handle EGPRs before adding support for REX2-prefixed instructions. Now the KVM GPR accessors can handle EGPRs. Then, the emulator can uniformly cache and track all GPRs without requiring separate handling. Signed-off-by: Chang S. Bae --- arch/x86/kvm/kvm_emulate.h | 10 +++++----- arch/x86/kvm/x86.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index fb3dab4b5a53..16b35a796a7f 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -105,13 +105,13 @@ struct x86_instruction_info { struct x86_emulate_ops { void (*vm_bugged)(struct x86_emulate_ctxt *ctxt); /* - * read_gpr: read a general purpose register (rax - r15) + * read_gpr: read a general purpose register (rax - r31) * * @reg: gpr number. */ ulong (*read_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg); /* - * write_gpr: write a general purpose register (rax - r15) + * write_gpr: write a general purpose register (rax - r31) * * @reg: gpr number. * @val: value to write. @@ -314,7 +314,7 @@ typedef void (*fastop_t)(struct fastop *); * a ModRM or SIB byte. */ #ifdef CONFIG_X86_64 -#define NR_EMULATOR_GPRS 16 +#define NR_EMULATOR_GPRS 32 #else #define NR_EMULATOR_GPRS 8 #endif @@ -373,9 +373,9 @@ struct x86_emulate_ctxt { u8 lock_prefix; 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a="80264250" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264250" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:35 -0800 X-CSE-ConnectionGUID: PWHo+LuJS/+zT6s8pleEmg== X-CSE-MsgGUID: PcvAAXgGTVC/30URg0NDFg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042278" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:36 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 10/16] KVM: emulate: Handle EGPR index and REX2-incompatible opcodes Date: Mon, 12 Jan 2026 23:54:02 +0000 Message-ID: <20260112235408.168200-11-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the emulator for REX2 handling by introducing the NoRex2 opcode flag and supporting extended register indices. Add a helper to factor out common logic for calculating register indices from a given register identifier and REX bits alone. REX2 does not support three-byte opcodes. Instead, the REX2.M bit selects between one- and two-byte opcode tables, which were previously distinguished by the 0x0F escape byte. Some legacy instructions in those tables never reference extended registers. When prefixed with REX, such instructions are treated as if the prefix were absent. In contrast, a REX2 prefix causes a #UD, which should be handled explicitly. Link: https://lore.kernel.org/1ebf3a23-5671-41c1-8daa-c83f2f105936@redhat.c= om Suggested-by: Paolo Bonzini Signed-off-by: Chang S. Bae --- V1 -> V2: Rename NoRex to NoRex2 (Paolo) --- arch/x86/kvm/emulate.c | 80 +++++++++++++++++++++++--------------- arch/x86/kvm/kvm_emulate.h | 1 + 2 files changed, 50 insertions(+), 31 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index c8e292e9a24d..ef0da1acab5a 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -175,6 +175,7 @@ #define TwoMemOp ((u64)1 << 55) /* Instruction has two memory operand = */ #define IsBranch ((u64)1 << 56) /* Instruction is considered a branch.= */ #define ShadowStack ((u64)1 << 57) /* Instruction affects Shadow Stacks. = */ +#define NoRex2 ((u64)1 << 58) /* Instruction not present in REX2 map= s */ =20 #define DstXacc (DstAccLo | SrcAccHi | SrcWrite) =20 @@ -244,6 +245,7 @@ enum rex_bits { REX_X =3D 2, REX_R =3D 4, REX_W =3D 8, + REX_M =3D 0x80, }; =20 static void writeback_registers(struct x86_emulate_ctxt *ctxt) @@ -1078,6 +1080,15 @@ static int em_fnstsw(struct x86_emulate_ctxt *ctxt) return X86EMUL_CONTINUE; } =20 +static __always_inline int rex_get_rxb(u8 rex, u8 fld) +{ + BUILD_BUG_ON(!__builtin_constant_p(fld)); + BUILD_BUG_ON(fld !=3D REX_B && fld !=3D REX_X && fld !=3D REX_R); + + rex >>=3D ffs(fld) - 1; + return (rex & 1 ? 8 : 0) + (rex & 0x10 ? 16 : 0); +} + static void __decode_register_operand(struct x86_emulate_ctxt *ctxt, struct operand *op, int reg) { @@ -1117,7 +1128,7 @@ static void decode_register_operand(struct x86_emulat= e_ctxt *ctxt, if (ctxt->d & ModRM) reg =3D ctxt->modrm_reg; else - reg =3D (ctxt->b & 7) | (ctxt->rex_bits & REX_B ? 8 : 0); + reg =3D (ctxt->b & 7) | rex_get_rxb(ctxt->rex_bits, REX_B); =20 __decode_register_operand(ctxt, op, reg); } @@ -1136,9 +1147,9 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt, int rc =3D X86EMUL_CONTINUE; ulong modrm_ea =3D 0; =20 - ctxt->modrm_reg =3D (ctxt->rex_bits & REX_R ? 8 : 0); - index_reg =3D (ctxt->rex_bits & REX_X ? 8 : 0); - base_reg =3D (ctxt->rex_bits & REX_B ? 8 : 0); + ctxt->modrm_reg =3D rex_get_rxb(ctxt->rex_bits, REX_R); + index_reg =3D rex_get_rxb(ctxt->rex_bits, REX_X); + base_reg =3D rex_get_rxb(ctxt->rex_bits, REX_B); =20 ctxt->modrm_mod =3D (ctxt->modrm & 0xc0) >> 6; ctxt->modrm_reg |=3D (ctxt->modrm & 0x38) >> 3; @@ -4245,7 +4256,7 @@ static const struct opcode opcode_table[256] =3D { /* 0x38 - 0x3F */ I6ALU(NoWrite, em_cmp), N, N, /* 0x40 - 0x4F */ - X8(I(DstReg, em_inc)), X8(I(DstReg, em_dec)), + X8(I(DstReg | NoRex2, em_inc)), X8(I(DstReg | NoRex2, em_dec)), /* 0x50 - 0x57 */ X8(I(SrcReg | Stack, em_push)), /* 0x58 - 0x5F */ @@ -4263,7 +4274,7 @@ static const struct opcode opcode_table[256] =3D { I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_i= n), /* insb, insw/insd */ I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, o= utsw/outsd */ /* 0x70 - 0x7F */ - X16(D(SrcImmByte | NearBranch | IsBranch)), + X16(D(SrcImmByte | NearBranch | IsBranch | NoRex2)), /* 0x80 - 0x87 */ G(ByteOp | DstMem | SrcImm, group1), G(DstMem | SrcImm, group1), @@ -4287,15 +4298,15 @@ static const struct opcode opcode_table[256] =3D { II(ImplicitOps | Stack, em_popf, popf), I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf), /* 0xA0 - 0xA7 */ - I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov), - I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov), - I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov), - I2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r), + I2bv(DstAcc | SrcMem | Mov | MemAbs | NoRex2, em_mov), + I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable | NoRex2, em_mov), + I2bv(SrcSI | DstDI | Mov | String | TwoMemOp | NoRex2, em_mov), + I2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp | NoRex2, em_cmp_r), /* 0xA8 - 0xAF */ - I2bv(DstAcc | SrcImm | NoWrite, em_test), - I2bv(SrcAcc | DstDI | Mov | String, em_mov), - I2bv(SrcSI | DstAcc | Mov | String, em_mov), - I2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r), + I2bv(DstAcc | SrcImm | NoWrite | NoRex2, em_test), + I2bv(SrcAcc | DstDI | Mov | String | NoRex2, em_mov), + I2bv(SrcSI | DstAcc | Mov | String | NoRex2, em_mov), + I2bv(SrcAcc | DstDI | String | NoWrite | NoRex2, em_cmp_r), /* 0xB0 - 0xB7 */ X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)), /* 0xB8 - 0xBF */ @@ -4325,17 +4336,17 @@ static const struct opcode opcode_table[256] =3D { /* 0xD8 - 0xDF */ N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N, /* 0xE0 - 0xE7 */ - X3(I(SrcImmByte | NearBranch | IsBranch, em_loop)), - I(SrcImmByte | NearBranch | IsBranch, em_jcxz), - I2bvIP(SrcImmUByte | DstAcc, em_in, in, check_perm_in), - I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out), + X3(I(SrcImmByte | NearBranch | IsBranch | NoRex2, em_loop)), + I(SrcImmByte | NearBranch | IsBranch | NoRex2, em_jcxz), + I2bvIP(SrcImmUByte | DstAcc | NoRex2, em_in, in, check_perm_in), + I2bvIP(SrcAcc | DstImmUByte | NoRex2, em_out, out, check_perm_out), /* 0xE8 - 0xEF */ - I(SrcImm | NearBranch | IsBranch | ShadowStack, em_call), - D(SrcImm | ImplicitOps | NearBranch | IsBranch), - I(SrcImmFAddr | No64 | IsBranch, em_jmp_far), - D(SrcImmByte | ImplicitOps | NearBranch | IsBranch), - I2bvIP(SrcDX | DstAcc, em_in, in, check_perm_in), - I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out), + I(SrcImm | NearBranch | IsBranch | ShadowStack | NoRex2, em_call), + D(SrcImm | ImplicitOps | NearBranch | IsBranch | NoRex2), + I(SrcImmFAddr | No64 | IsBranch | NoRex2, em_jmp_far), + D(SrcImmByte | ImplicitOps | NearBranch | IsBranch | NoRex2), + I2bvIP(SrcDX | DstAcc | NoRex2, em_in, in, check_perm_in), + I2bvIP(SrcAcc | DstDX | NoRex2, em_out, out, check_perm_out), /* 0xF0 - 0xF7 */ N, DI(ImplicitOps, icebp), N, N, DI(ImplicitOps | Priv, hlt), D(ImplicitOps), @@ -4376,12 +4387,12 @@ static const struct opcode twobyte_table[256] =3D { N, GP(ModRM | DstMem | SrcReg | Mov | Sse | Avx, &pfx_0f_2b), N, N, N, N, /* 0x30 - 0x3F */ - II(ImplicitOps | Priv, em_wrmsr, wrmsr), - IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc), - II(ImplicitOps | Priv, em_rdmsr, rdmsr), - IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc), - I(ImplicitOps | EmulateOnUD | IsBranch | ShadowStack, em_sysenter), - I(ImplicitOps | Priv | EmulateOnUD | IsBranch | ShadowStack, em_sysexit), + II(ImplicitOps | Priv | NoRex2, em_wrmsr, wrmsr), + IIP(ImplicitOps | NoRex2, em_rdtsc, rdtsc, check_rdtsc), + II(ImplicitOps | Priv | NoRex2, em_rdmsr, rdmsr), + IIP(ImplicitOps | NoRex2, em_rdpmc, rdpmc, check_rdpmc), + I(ImplicitOps | EmulateOnUD | IsBranch | ShadowStack | NoRex2, em_sysente= r), + I(ImplicitOps | Priv | EmulateOnUD | IsBranch | ShadowStack | NoRex2, em_= sysexit), N, N, N, N, N, N, N, N, N, N, /* 0x40 - 0x4F */ @@ -4399,7 +4410,7 @@ static const struct opcode twobyte_table[256] =3D { N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f), /* 0x80 - 0x8F */ - X16(D(SrcImm | NearBranch | IsBranch)), + X16(D(SrcImm | NearBranch | IsBranch | NoRex2)), /* 0x90 - 0x9F */ X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)), /* 0xA0 - 0xA7 */ @@ -4992,6 +5003,13 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, v= oid *insn, int insn_len, int opcode =3D opcode_table[ctxt->b]; } =20 + /* + * Instructions marked with NoRex2 ignore a legacy REX prefix, but + * #UD should be raised when prefixed with REX2. + */ + if (ctxt->d & NoRex2 && ctxt->rex_prefix =3D=3D REX2_PREFIX) + opcode.flags =3D Undefined; + if (opcode.flags & ModRM) ctxt->modrm =3D insn_fetch(u8, ctxt); =20 diff --git a/arch/x86/kvm/kvm_emulate.h b/arch/x86/kvm/kvm_emulate.h index 16b35a796a7f..dd5d1e489db6 100644 --- a/arch/x86/kvm/kvm_emulate.h +++ b/arch/x86/kvm/kvm_emulate.h @@ -325,6 +325,7 @@ typedef void (*fastop_t)(struct fastop *); enum rex_type { REX_NONE, REX_PREFIX, + REX2_PREFIX, }; =20 struct x86_emulate_ctxt { --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B59FA221721; Tue, 13 Jan 2026 00:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263520; cv=none; b=tpm1HuPuRn1dGWv+Rr6ol0Fr/8DZpy/dc3KsHVbH93MIWGRyKBFg14bz7hsbGrszWQRm+TOprEI5Plf8nQ1h/rxg4FVAkyijOBKHASaHy6OxgJiahuLuO4Z90s9iiv+PylPZfafJECNo10hDKtUT5L2AkXATMVS92y078FANc/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263520; c=relaxed/simple; bh=2UDZSf/uCc4ahoJNM9mnReJM05Zh9eEyzJWh1HAGYF0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DJdbf8M6tFrUrzYPfobkCTpV/a+wFZz57INA2urag68zHq8nHaAzymrQZL0dlrTLTdPpuJMAgWRpic6bmrXT1ra7VvUGbrsuu2lNkJUyTc2kTiKxlChiVbs6e4pUXiGPqTdeAZoSL+W4RTQ/X8qiVz/DhnYhYUToybAwwf6xXpw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RxEKoHde; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RxEKoHde" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263518; x=1799799518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2UDZSf/uCc4ahoJNM9mnReJM05Zh9eEyzJWh1HAGYF0=; b=RxEKoHdeeONWs2AfcTq9NmwTjgl79yPV44h8ZNJPI0il05dGrTa1TAsR T4+NCKRIWirx6tfWjoCAjatT82RWW6G6QN5kCxznrIQCiytQqF0QtKlPu U8am+9GUDRLApXOOIxAh3XpT7lJw+bipVbUjeq1x9onFO/BaLW/TpA7JP lh0QnSJ/T1K2Kyl7fOeHt8G6VsMWrSE3FO1QrkVh2J+0TA+JCCk3CgEE2 k45cJO6Ah4lqdVNJEuj2Y5PtTTOf07wDGeVP5CR5WPMSITb2Qq4RimLNe JBcf48zGNtqWINydLRq+uH2XvBlS5JzDfP7rJ6nqtzqm37oj7TwHpwA9q g==; X-CSE-ConnectionGUID: eQs4E9WGQXid7YYJeo5Pqg== X-CSE-MsgGUID: bFlkYmAZSGutLS+Va9Kavg== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264257" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264257" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:38 -0800 X-CSE-ConnectionGUID: 1S0t5tWLSm66hAST5rl/Ow== X-CSE-MsgGUID: pt4uTyosQJup9MaWqhR+Wg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042285" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:38 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 11/16] KVM: emulate: Support REX2-prefixed opcode decode Date: Mon, 12 Jan 2026 23:54:03 +0000 Message-ID: <20260112235408.168200-12-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Extend the instruction decoder to recognize and handle the REX2 prefix, including validation of prefix sequences and correct opcode table selection. REX2 is a terminal prefix: once 0xD5 is encountered, the following byte is the opcode. When REX.M=3D0, most prefix bytes are invalid after REX2, including REX, VEX, EVEX, and another REX2. Also, REX2-prefixed instructions are only valid in 64-bit mode. All of the invalid prefix combinations after REX2 coincide with opcodes that are architecturally invalid in 64-bit mode. Thus, marking such opcodes with No64 in opcode_table[] naturally disallows those illegal prefix sequences. The 0x40=E2=80=930x4F opcode row was missing the No64 flag. While NoRex2 al= ready invalidates REX2 for these opcodes, adding No64 makes opcode attributes explicit and complete. Link: https://lore.kernel.org/CABgObfYYGTvkYpeyqLSr9JgKMDA_STSff2hXBNchLZuK= FU+MMA@mail.gmail.com Suggested-by: Paolo Bonzini Signed-off-by: Chang S. Bae --- arch/x86/kvm/emulate.c | 38 ++++++++++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index ef0da1acab5a..1a565a4e3ff7 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -4256,7 +4256,7 @@ static const struct opcode opcode_table[256] =3D { /* 0x38 - 0x3F */ I6ALU(NoWrite, em_cmp), N, N, /* 0x40 - 0x4F */ - X8(I(DstReg | NoRex2, em_inc)), X8(I(DstReg | NoRex2, em_dec)), + X8(I(DstReg | NoRex2 | No64, em_inc)), X8(I(DstReg | NoRex2 | No64, em_de= c)), /* 0x50 - 0x57 */ X8(I(SrcReg | Stack, em_push)), /* 0x58 - 0x5F */ @@ -4850,6 +4850,17 @@ static int x86_decode_avx(struct x86_emulate_ctxt *c= txt, return rc; } =20 +static inline bool rex2_invalid(struct x86_emulate_ctxt *ctxt) +{ + const struct x86_emulate_ops *ops =3D ctxt->ops; + u64 xcr =3D 0; + + return ctxt->rex_prefix =3D=3D REX_PREFIX || + !(ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE) || + ops->get_xcr(ctxt, 0, &xcr) || + !(xcr & XFEATURE_MASK_APX); +} + int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_le= n, int emulation_type) { int rc =3D X86EMUL_CONTINUE; @@ -4903,7 +4914,7 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, vo= id *insn, int insn_len, int ctxt->op_bytes =3D def_op_bytes; ctxt->ad_bytes =3D def_ad_bytes; =20 - /* Legacy prefixes. */ + /* Legacy and REX/REX2 prefixes. */ for (;;) { switch (ctxt->b =3D insn_fetch(u8, ctxt)) { case 0x66: /* operand-size override */ @@ -4949,6 +4960,17 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, v= oid *insn, int insn_len, int ctxt->rex_prefix =3D REX_PREFIX; ctxt->rex_bits =3D ctxt->b & 0xf; continue; + case 0xd5: /* REX2 */ + if (mode !=3D X86EMUL_MODE_PROT64) + goto done_prefixes; + if (rex2_invalid(ctxt)) { + opcode =3D ud; + goto done_modrm; + } + ctxt->rex_prefix =3D REX2_PREFIX; + ctxt->rex_bits =3D insn_fetch(u8, ctxt); + ctxt->b =3D insn_fetch(u8, ctxt); + goto done_prefixes; case 0xf0: /* LOCK */ ctxt->lock_prefix =3D 1; break; @@ -4971,6 +4993,12 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, v= oid *insn, int insn_len, int if (ctxt->rex_bits & REX_W) ctxt->op_bytes =3D 8; =20 + /* REX2 opcode is one byte unless M-bit selects the two-byte map */ + if (ctxt->rex_bits & REX_M) + goto decode_twobytes; + else if (ctxt->rex_prefix =3D=3D REX2_PREFIX) + goto decode_onebyte; + /* Opcode byte(s). */ if (ctxt->b =3D=3D 0xc4 || ctxt->b =3D=3D 0xc5) { /* VEX or LDS/LES */ @@ -4988,17 +5016,19 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, = void *insn, int insn_len, int goto done; } else if (ctxt->b =3D=3D 0x0f) { /* Two- or three-byte opcode */ - ctxt->opcode_len =3D 2; ctxt->b =3D insn_fetch(u8, ctxt); +decode_twobytes: + ctxt->opcode_len =3D 2; opcode =3D twobyte_table[ctxt->b]; =20 /* 0F_38 opcode map */ - if (ctxt->b =3D=3D 0x38) { + if (ctxt->b =3D=3D 0x38 && ctxt->rex_prefix !=3D REX2_PREFIX) { ctxt->opcode_len =3D 3; ctxt->b =3D insn_fetch(u8, ctxt); opcode =3D opcode_map_0f_38[ctxt->b]; } } else { +decode_onebyte: /* Opcode byte(s). */ opcode =3D opcode_table[ctxt->b]; } --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8B59239E8D; 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a="80264267" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264267" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:40 -0800 X-CSE-ConnectionGUID: 0XxsBxu6QCiI+cjd9k5a7w== X-CSE-MsgGUID: RQPZbfijRVWgBh5uhR5wMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042294" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:41 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 12/16] KVM: emulate: Reject EVEX-prefixed instructions Date: Mon, 12 Jan 2026 23:54:04 +0000 Message-ID: <20260112235408.168200-13-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly mark EVEX-prefixed opcodes (0x62) as unsupported. Signed-off-by: Chang S. Bae --- arch/x86/kvm/emulate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c index 1a565a4e3ff7..c5cb356f1524 100644 --- a/arch/x86/kvm/emulate.c +++ b/arch/x86/kvm/emulate.c @@ -5040,6 +5040,11 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, v= oid *insn, int insn_len, int if (ctxt->d & NoRex2 && ctxt->rex_prefix =3D=3D REX2_PREFIX) opcode.flags =3D Undefined; =20 + /* EVEX-prefixed instructions are not implemented */ + if (ctxt->opcode_len =3D=3D 1 && ctxt->b =3D=3D 0x62 && + (mode =3D=3D X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) =3D=3D 0xc0)) + opcode.flags =3D NotImpl; + if (opcode.flags & ModRM) ctxt->modrm =3D insn_fetch(u8, ctxt); =20 --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AD7B248F66; Tue, 13 Jan 2026 00:18:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263524; cv=none; b=Z8k4CED0+dkbnnIzkp/9vedeTqS3jxYPdwHzwLTwrYAlSugpSGbu2kvYS1QIudCmW8zHtzDRm1kvLl2ruHlJ9W7xTwIz3LViuMsRTOLS9L1R+yQI+i+P12+Gr3iSvnTE2oVYgBq2UOmhU3m9PFr/qjSGM5vPFZP9Xk7YIrLJc/M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263524; c=relaxed/simple; bh=mCDXrYMSyGGejxXWe4/gKpSgUYhATo0cxRE8f7Kzqb8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Fq+JVJ7JADYR0cOg8LmmV6CoIWYtYBuxeXbmvvD86HgEfzVINrfWRcLEzLZDqANL9c4McgiGRUn7rZer9X/f8uwHd8feC6sGAhZemnwNtY8us95lPkvQXPS67Uz7H0dl1jpLNtHsv9ap6KVQT30bdsGqS0cFVmoK/1R6jIto0mQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OhGtDk0e; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OhGtDk0e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263523; x=1799799523; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mCDXrYMSyGGejxXWe4/gKpSgUYhATo0cxRE8f7Kzqb8=; b=OhGtDk0e5oTi5SlIHdPZaPxMiPRxRzLiHaJV+mWDQf/atNiFBY9D8iSe CZ8R481aAQF6bgXg3eiGaxqQ31Aun50UZ/GfYZkF+jfOjBItuJ1o5oH3n QWiMxFnz3N+HzSfQvqqDJ3MML5/FkY5H+nN4fnlbhNT0OY5p+6Wnvo32f fn0QbnzkbpQTxQwzLe5sXuGO4Inx4wgNAiBtUqEbKf6ga7HaxNYLrp9Yc iI8rwYURoayaVcw8ZqGV7oqJBBNx2MHkeOEsZvX9lO5ij5cXTz5ZYfTFY S+eaeijbEYnb1BVJsS8PRBlcv+05DgqLJQPf0OfZOm1vUjObo0zRa9hY0 g==; X-CSE-ConnectionGUID: oNdwrRIiR8WyNQ+p9lt/7Q== X-CSE-MsgGUID: xw4eZUa+Q1i/hNg+hmEuyg== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264273" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264273" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:43 -0800 X-CSE-ConnectionGUID: cCF4ZobiRl+rIL9UhFZuUw== X-CSE-MsgGUID: 1S8/fYGNSJSNExksB6OlQQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042300" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:44 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 13/16] KVM: x86: Guard valid XCR0.APX settings Date: Mon, 12 Jan 2026 23:54:05 +0000 Message-ID: <20260112235408.168200-14-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prevent invalid XCR0.APX configurations in two cases: conflict with MPX and lack of SVM support. In the non-compacted XSAVE format, APX and MPX conflict on the same offset. Although MPX is being deprecated in practice, KVM should explicitly reject such configurations that set both bits. At this point, only VMX supports EGPRs. SVM will require corresponding extensions to handle EGPR indices. The addition to the supported XCR0 mask should accompany guest CPUID exposure, which will be done separately. Link: https://lore.kernel.org/ab3f4937-38f5-4354-8850-bf773c159bbe@redhat.c= om Suggested-by: Paolo Bonzini Signed-off-by: Chang S. Bae --- arch/x86/kvm/svm/svm.c | 7 ++++++- arch/x86/kvm/x86.c | 4 ++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 209faa742e98..a06e5a24b808 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5301,8 +5301,13 @@ static __init int svm_hardware_setup(void) } kvm_enable_efer_bits(EFER_NX); =20 + /* + * APX introduces EGPRs, which require additional VMCB support. + * Disable APX until the necessary extensions are handled. + */ kvm_caps.supported_xcr0 &=3D ~(XFEATURE_MASK_BNDREGS | - XFEATURE_MASK_BNDCSR); + XFEATURE_MASK_BNDCSR | + XFEATURE_MASK_APX); =20 if (boot_cpu_has(X86_FEATURE_FXSR_OPT)) kvm_enable_efer_bits(EFER_FFXSR); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e7f858488f2c..189a03483d03 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1391,6 +1391,10 @@ int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, = u64 xcr) (!(xcr0 & XFEATURE_MASK_BNDCSR))) return 1; =20 + /* MPX and APX conflict in the non-compacted XSAVE format */ + if (xcr0 & XFEATURE_MASK_BNDREGS && xcr0 & XFEATURE_MASK_APX) + return 1; + if (xcr0 & XFEATURE_MASK_AVX512) { if (!(xcr0 & XFEATURE_MASK_YMM)) return 1; --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 267C2275AFB; Tue, 13 Jan 2026 00:18:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263528; cv=none; b=FXc2b6qrOwY82896ffLQj3tObJS6jOnImvOp0Ib7ipmq/14mv20zmPN6CfgRp4n83AhIx+Ha77vSFvimWBzm5nwtG0+wKKl91ZtjHOi8x17+uJpkcOdTpRnzujC0vlw21Wb2kVxmIAWvZclJGMZPIV0Mq511ZntboKnYWVPjW4I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768263528; c=relaxed/simple; bh=JpLi1y3bTBto11eIj/IZX9rGESLc5O0rTqB+8uIQlRo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hzuA3xbDj/21UiHBtfOB+c0AyzuIHff4RnRe+zslFBbFDCI+l7akCeEzQ8BigsPNrKtXyjR8Jv7/149iQb6Q6vgU2Kl/0bsuV2YPpfyOEKfi0+CTVnBeXTUQLVT356Owb5ii1sVKWDGYF9WCFEQeLJxNn60eGHOp18pN0P7uxQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DX7+eDUh; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DX7+eDUh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768263526; x=1799799526; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JpLi1y3bTBto11eIj/IZX9rGESLc5O0rTqB+8uIQlRo=; b=DX7+eDUhxNQe9TnQkKgo80RPD9TNQVjwEAV7/SZ3Dx2E8ychFo3eM10G EvDI/g0bYbhGC8/mfJqyBqq+barWez/0xiPmMM1CLAxPjZLWVJUeRYmfZ CE1TpOiL1m51tjh1d2YtL754C41kgxmsf3BDrBg9ddQy5fn9JhpqizFda 1l5qLmNaYgB6phOBI5sFfdxPXZzaTYbITtm00CVismbd7quJaP1FDFiOa ZpxOU72AdvcIvFA9fRmByPW5FkpRUUxkHp4zwTBlnFlsUXQ0XFvxqkHrU RekGRS/3u1NdNfwFYsZWHD2buq2LNSEiVDIeNuTKx2oJa/jb3kn6i8n3S g==; X-CSE-ConnectionGUID: 8ztpyKM2Syas+BaTA5buZg== X-CSE-MsgGUID: kbQg/YxaS1CWqfMSsNAOeg== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264285" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264285" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:45 -0800 X-CSE-ConnectionGUID: GKYDSFwIR2SrnU51R4SxjQ== X-CSE-MsgGUID: 3LJtUmXeQLiiz8/43KGgEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042307" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:46 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com, Peter Fang Subject: [PATCH v2 14/16] KVM: x86: Expose APX foundational feature bit to guests Date: Mon, 12 Jan 2026 23:54:06 +0000 Message-ID: <20260112235408.168200-15-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Peter Fang Add the APX xfeature bit to the list of supported XCR0 components and expose the APX feature to guests. Update the maximum supported CPUID leaf to 0x29 to include the APX leaf. On SVM systems, ensure that the feature is not advertised as EGPR support is not yet supported. No APX sub-features are enumerated yet. Those will be exposed in a separate patch. Signed-off-by: Peter Fang Signed-off-by: Chang S. Bae --- V1 -> V2: Exclude the APX CPUID definition as patch8 includes it now --- arch/x86/kvm/cpuid.c | 8 +++++++- arch/x86/kvm/svm/svm.c | 8 ++++++++ arch/x86/kvm/x86.c | 3 ++- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 88a5426674a1..5431e31a4851 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1038,6 +1038,7 @@ void kvm_set_cpu_caps(void) F(AVX_VNNI_INT16), F(PREFETCHITI), F(AVX10), + SCATTERED_F(APX), ); =20 kvm_cpu_cap_init(CPUID_7_2_EDX, @@ -1401,7 +1402,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_ar= ray *array, u32 function) switch (function) { case 0: /* Limited to the highest leaf implemented in KVM. */ - entry->eax =3D min(entry->eax, 0x24U); + entry->eax =3D min(entry->eax, 0x29U); break; case 1: cpuid_entry_override(entry, CPUID_1_EDX); @@ -1646,6 +1647,11 @@ static inline int __do_cpuid_func(struct kvm_cpuid_a= rray *array, u32 function) entry->edx =3D 0; break; } + case 0x29: { + /* No APX sub-features are supported yet */ + entry->eax =3D entry->ebx =3D entry->ecx =3D entry->edx =3D 0; + break; + } case KVM_CPUID_SIGNATURE: { const u32 *sigptr =3D (const u32 *)KVM_SIGNATURE; entry->eax =3D KVM_CPUID_FEATURES; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index a06e5a24b808..9c76ea7a4231 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -5284,6 +5284,14 @@ static __init void svm_set_cpu_caps(void) */ kvm_cpu_cap_clear(X86_FEATURE_BUS_LOCK_DETECT); kvm_cpu_cap_clear(X86_FEATURE_MSR_IMM); + + /* + * If the APX xfeature bit is not supported, meaning that VMCB + * support for EGPRs is unavailable, then the APX feature should + * not be exposed to the guest. + */ + if (!(kvm_caps.supported_xcr0 & XFEATURE_MASK_APX)) + kvm_cpu_cap_clear(X86_FEATURE_APX); } =20 static __init int svm_hardware_setup(void) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 189a03483d03..67b3312ab737 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -214,7 +214,8 @@ static DEFINE_PER_CPU(struct kvm_user_return_msrs, user= _return_msrs); #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \ | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \ | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \ - | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE) + | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE \ + | XFEATURE_MASK_APX) =20 #define XFEATURE_MASK_CET_ALL (XFEATURE_MASK_CET_USER | XFEATURE_MASK_CET_= KERNEL) /* --=20 2.51.0 From nobody Sun Feb 8 00:12:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E6E4231829; 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a="80264291" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264291" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:48 -0800 X-CSE-ConnectionGUID: q7mfnKIWS2+qZkO2vBm4ow== X-CSE-MsgGUID: yPN8q+/kT+6eUprl2fmHyw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042313" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:48 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 15/16] KVM: x86: Expose APX sub-features to guests Date: Mon, 12 Jan 2026 23:54:07 +0000 Message-ID: <20260112235408.168200-16-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID leaf 0x29 sub-leaf 0 to enumerate APX sub-features to guests. This leaf currently defines the following sub-features: * New Conditional Instructions (NCI) * New Data Destination (NDD) * Flags Suppression (NF) The CPUID leaf is only exposed if the APX feature is enabled. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/cpuid.c | 10 ++++++++-- arch/x86/kvm/reverse_cpuid.h | 4 ++++ 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 9dedb8d77222..d75a76152340 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -794,6 +794,7 @@ enum kvm_only_cpuid_leafs { CPUID_24_0_EBX, CPUID_8000_0021_ECX, CPUID_7_1_ECX, + CPUID_29_0_EBX, NR_KVM_CPU_CAPS, =20 NKVMCAPINTS =3D NR_KVM_CPU_CAPS - NCAPINTS, diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 5431e31a4851..347b8f2402c7 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1070,6 +1070,10 @@ void kvm_set_cpu_caps(void) F(AVX10_512), ); =20 + kvm_cpu_cap_init(CPUID_29_0_EBX, + F(APX_NCI_NDD_NF), + ); + kvm_cpu_cap_init(CPUID_8000_0001_ECX, F(LAHF_LM), F(CMP_LEGACY), @@ -1648,8 +1652,10 @@ static inline int __do_cpuid_func(struct kvm_cpuid_a= rray *array, u32 function) break; } case 0x29: { - /* No APX sub-features are supported yet */ - entry->eax =3D entry->ebx =3D entry->ecx =3D entry->edx =3D 0; + if (!(kvm_caps.supported_xcr0 & XFEATURE_MASK_APX)) { + entry->eax =3D entry->ebx =3D entry->ecx =3D entry->edx =3D 0; + break; + } break; } case KVM_CPUID_SIGNATURE: { diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index e538b5444919..f8587586d031 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -50,6 +50,9 @@ #define X86_FEATURE_AVX10_256 KVM_X86_FEATURE(CPUID_24_0_EBX, 17) #define X86_FEATURE_AVX10_512 KVM_X86_FEATURE(CPUID_24_0_EBX, 18) =20 +/* Intel-defined sub-features, CPUID level 0x00000029:0 (EBX) */ +#define X86_FEATURE_APX_NCI_NDD_NF KVM_X86_FEATURE(CPUID_29_0_EBX, 0) + /* CPUID level 0x80000007 (EDX). */ #define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, = 8) =20 @@ -91,6 +94,7 @@ static const struct cpuid_reg reverse_cpuid[] =3D { [CPUID_24_0_EBX] =3D { 0x24, 0, CPUID_EBX}, [CPUID_8000_0021_ECX] =3D {0x80000021, 0, CPUID_ECX}, [CPUID_7_1_ECX] =3D { 7, 1, CPUID_ECX}, + [CPUID_29_0_EBX] =3D { 0x29, 0, CPUID_EBX}, }; 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X-CSE-ConnectionGUID: D6c8BrGySpu0Vy35/BtlUg== X-CSE-MsgGUID: DYCXNNscTnGcbnsosFSa/A== X-IronPort-AV: E=McAfee;i="6800,10657,11669"; a="80264297" X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="80264297" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2026 16:18:51 -0800 X-CSE-ConnectionGUID: OA0hqec9RZChdO+rZkuABA== X-CSE-MsgGUID: f6MsPvVEQXiICZUzNUNHhw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,222,1763452800"; d="scan'208";a="204042322" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by orviesa009.jf.intel.com with ESMTP; 12 Jan 2026 16:18:51 -0800 From: "Chang S. Bae" To: pbonzini@redhat.com, seanjc@google.com Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, chao.gao@intel.com, chang.seok.bae@intel.com Subject: [PATCH v2 16/16] KVM: x86: selftests: Add APX state handling and XCR0 sanity checks Date: Mon, 12 Jan 2026 23:54:08 +0000 Message-ID: <20260112235408.168200-17-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260112235408.168200-1-chang.seok.bae@intel.com> References: <20260112235408.168200-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that KVM exposes the APX feature to guests on APX-capable systems, extend the selftests to validate XCR0 configuration and state management. Since APX repurposes the XSAVE area previously used by MPX in the non-compacted format, add a check to ensure that MPX states are not set when APX is enabled. Also, load non-init APX state data in the guest so that XSTATE_BV[APX] is set, allowing validation of APX state testing. Signed-off-by: Chang S. Bae --- .../selftests/kvm/include/x86/processor.h | 1 + tools/testing/selftests/kvm/x86/state_test.c | 6 ++++++ .../selftests/kvm/x86/xcr0_cpuid_test.c | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 57d62a425109..6a1da26780ea 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -88,6 +88,7 @@ struct xstate { #define XFEATURE_MASK_LBR BIT_ULL(15) #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17) #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18) +#define XFEATURE_MASK_APX BIT_ULL(19) =20 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \ XFEATURE_MASK_ZMM_Hi256 | \ diff --git a/tools/testing/selftests/kvm/x86/state_test.c b/tools/testing/s= elftests/kvm/x86/state_test.c index f2c7a1c297e3..2b7aa4cca011 100644 --- a/tools/testing/selftests/kvm/x86/state_test.c +++ b/tools/testing/selftests/kvm/x86/state_test.c @@ -167,6 +167,12 @@ static void __attribute__((__flatten__)) guest_code(vo= id *arg) asm volatile ("vmovupd %0, %%zmm16" :: "m" (buffer)); } =20 + if (supported_xcr0 & XFEATURE_MASK_APX) { + /* mov $0xcccccccc, %r16 */ + asm volatile (".byte 0xd5, 0x18, 0xb8, 0xcc, 0xcc," + "0xcc, 0xcc, 0x00, 0x00, 0x00, 0x00"); + } + if (this_cpu_has(X86_FEATURE_MPX)) { uint64_t bounds[2] =3D { 10, 0xffffffffull }; uint64_t output[2] =3D { }; diff --git a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c b/tools/test= ing/selftests/kvm/x86/xcr0_cpuid_test.c index d038c1571729..e3d3af5ab6f2 100644 --- a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c @@ -46,6 +46,20 @@ do { \ __supported, (xfeatures)); \ } while (0) =20 +/* + * Verify that mutually exclusive architectural features do not overlap. + * For example, APX and MPX must never be reported as supported together. + */ +#define ASSERT_XFEATURE_CONFLICT(supported_xcr0, xfeatures, conflicts) \ +do { \ + uint64_t __supported =3D (supported_xcr0) & ((xfeatures) | (conflicts)); = \ + \ + __GUEST_ASSERT((__supported & (xfeatures)) !=3D (xfeatures) || \ + !(__supported & (conflicts)), \ + "supported =3D 0x%lx, xfeatures =3D 0x%llx, conflicts =3D 0x%llx"= , \ + __supported, (xfeatures), (conflicts)); \ +} while (0) + static void guest_code(void) { uint64_t initial_xcr0; @@ -79,6 +93,11 @@ static void guest_code(void) ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, XFEATURE_MASK_XTILE); =20 + /* Check APX by ensuring MPX is not exposed concurrently */ + ASSERT_XFEATURE_CONFLICT(supported_xcr0, + XFEATURE_MASK_APX, + XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR); + vector =3D xsetbv_safe(0, XFEATURE_MASK_FP); __GUEST_ASSERT(!vector, "Expected success on XSETBV(FP), got %s", --=20 2.51.0