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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add phy_link property Date: Mon, 12 Jan 2026 17:35:54 +0000 Message-ID: <20260112173555.1166714-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260112173555.1166714-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260112173555.1166714-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the renesas,miic-phy-link-active-low property to allow configuring the active level of phy_link status signals provided by the MIIC block. EtherPHY link-up and link-down status is required as a hardware IP feature independent of whether GMAC or ETHSW is used. With GMAC, link state is retrieved via MDC/MDIO and handled in software. In contrast, ETHSW exposes dedicated PHY_LINK pins that provide this information directly in hardware. These PHY_LINK signals are required not only for host-controlled traffic but also for switch-only forwarding paths where frames are exchanged between external nodes without CPU involvement. This is particularly important for redundancy protocols such as DLR (Device Level Ring), which depend on fast detection of link-down events caused by cable or port failures. Handling such events purely in software introduces latency, which is why ETHSW provides dedicated hardware PHY_LINK pins. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) --- v2->v3: - Updated commit message - Renamed DT property from renesas,miic-phylink-active-low to renesas,miic-phy-link-active-low. v1->v2: - Updated commit message to elaborate the necessity of PHY link signals. --- .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.ya= ml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 3adbcf56d2be..f9d39114e667 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -86,6 +86,13 @@ patternProperties: and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/= N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 =20 + renesas,miic-phy-link-active-low: + type: boolean + description: Indicates that the PHY-link signal provided by the Et= hernet switch, + EtherCAT, or SERCOS3 interface is active low. When present, this= property + sets the corresponding signal polarity to active low. When omitt= ed, the signal + defaults to active high. + required: - reg - renesas,miic-input --=20 2.52.0 From nobody Mon Feb 9 17:10:38 2026 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1EF037E307 for ; Mon, 12 Jan 2026 17:36:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768239370; cv=none; b=oyuxbedISsPV66ErPbRCK5yUS7I/x+EcruNkMF0pwAcyjppjxFXypi6k0cw9agBkTOxA9EpQtciiwPN/BLxLqJi8B1bd97yPJFia+Qbwev2xALGFuW0MWqYQuVBxRbvSLdkowOoM/5IGupUosuYMDe9G/XcFuph8gScrEPgyWuo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768239370; c=relaxed/simple; bh=GCdO5a+HMfjS0Onb4iX2dcKWJm/SM5/aDLNSivt+rZg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=H3WucaAa45n16qHbI/fSHogsrIt4sgbs7YgtsKvA5MNWbaJjgJye5/wieDEbECEJVm7JC3LHZI95yt/sSsXZDxbcrjEy/YemAUE11FALM5qFOv0/UGPqh2l46XWRYdYKGkGYa7h90OBG1GxYolbYmoXZp0OZJRph9XUZjHSmZbg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=H2/CRee0; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="H2/CRee0" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-42fbc3056afso3838443f8f.2 for ; Mon, 12 Jan 2026 09:36:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1768239366; x=1768844166; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tuk52pHE2ucr51aG3tpUoDcttX6aTJw3OWzP3ZmFW2E=; b=H2/CRee0//rGPYg0l1zmRr7B+722QUuuMKv92yP2gmELT0GHa8y0AorCZVvDDfMMl5 VVod1fNSHqTcetc4SehLAHpe7Yg8Ykj4tIgaZ/01MPtd41ptcqFS9A7cTtMbfjAp5+Wz GBLWx6tHYBvuGc84oL3pqgXWLqiiBcxUqhJYyL51qnjuKfDFjZdPKvzlf+RmmNhTNYRe H+kyiohngHx8+UwJ3ICkHQuX/cwsQ9dUETgTP8LkGnIZPjV52/M5Vyv1S0bGJoOxntCk il1IyCt5gbYw3OsizN0ize6bEE80kfcUruHiMAI/UfNuVKTUM/rTBsS33BIu5ndA9zu/ O4uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1768239366; x=1768844166; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=tuk52pHE2ucr51aG3tpUoDcttX6aTJw3OWzP3ZmFW2E=; b=fSon/iqk6gdjQfeI4/Kmdkeo3DTgoWG13IDWjPtUFFNgMT57Xru7bDb0fZoV1FbKuC xPGukWbVKW8X+1DHn/1ZOEuDxPu5B31pdoabkaDz6AvVr3GS4iaTHb0f4Oj94IqBdB2H awNPMmMW4cyXiXLKZPnbS0enK4sARHOPJb6RqcfTJ/J6qJ7LagT65jp/MWT5HkDFeuSw nciyNDyvsnwrDsVxlSuuDtB9ltM5U6wPQMU1iW+LW3GPLj8aNQ0JveHxyojb3p6dShtc HOU6j5DzuYf9rsbtlqVQ2koJ0xH3/JKD5B2TRPWe5kvng/nZPWjyrUcqFfaWDvsixYFC eftQ== X-Forwarded-Encrypted: i=1; AJvYcCXH6XgM/t88jg550CvriZEjWQ2fal1SevBtpJbJfdlECioPZ8cASzkI5xAKgYKzWizA2Xg05mzz2vtBFKA=@vger.kernel.org X-Gm-Message-State: AOJu0Yw5+lLu3hrmF6N0Q5NQfHCJY2sohc8OWkNlw3OdcuTTrkIr/DnL yuEibcT5+gLeB7AKqB1EIFVLi0cZ46+PmvGqiseLa2Im574Doy+gljbv X-Gm-Gg: AY/fxX7ZyIAsczaGR3+3FRdXcodtP4OsFx7EINPiZ8VzY6ZkyN9q8twHsYlLCckvat2 oViJZVsXPjQtL2Zny5jlkWpFRqqpN0VLy3qFsGwsV2PCmv7jP7KpddZMxS7hloMXI+0zKvr6yuy 9AmZ/4Bl8Ssu33R4oqZUb1y+OHXA3CV682KJJ1rqS8DcN1IaGhbpBxRthse30Uv5AciabdaSsrc ugOF5rfeTjwlk2/BiVNNEoAgDOOZ9gqPRWin40FbsYZu0/BcNyqaJQ4U+RLSf7VMYBTgWJJCUIL 7W0tQ2R3e9Th21D4HthYZoSIbIbhLJa6lTMtA+hm35omiL91meLVf1K5fnJPCb2bwPzANcvDVb6 N5SP0C4MPGmLtjQZdxhMYKzspWd+5cOd5oeA6xU/L92piidgakKSwkQeYi8uiA8TMwt5Pyu62kK DvUDcQLZYBKlwWgEwgR2X8SWOIT7h8pA3UqWWpnhToLkz/wV7RlfRLqD5WCbReNRzRrlr47pAHl H85OmSNEELLtkCVQ/UXtHAIj95d4iSsJcg= X-Google-Smtp-Source: AGHT+IHvetCOikt5zHJa+kt1XGT/CFTzAu/3wOZte9eNFcIcwZdd0nfXB3SqwzR7iSvrVRxboWe4ZQ== X-Received: by 2002:a05:6000:2087:b0:430:f8b3:e834 with SMTP id ffacd0b85a97d-432c3629b4amr24163355f8f.11.1768239366073; Mon, 12 Jan 2026 09:36:06 -0800 (PST) Received: from iku.Home ([2a06:5906:61b:2d00:9336:b2a5:a8c1:722e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd5ff0b2sm39625403f8f.42.2026.01.12.09.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jan 2026 09:36:05 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH net-next v3 2/2] net: pcs: rzn1-miic: Add PHY_LINK active-level configuration support Date: Mon, 12 Jan 2026 17:35:55 +0000 Message-ID: <20260112173555.1166714-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260112173555.1166714-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260112173555.1166714-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support to configure the active level of MIIC PHY_LINK status signals on a per-converter basis using a DT property. MIIC provides dedicated PHY_LINK signals that indicate EtherPHY link-up and link-down status in hardware. These signals are required regardless of whether GMAC or ETHSW is used. With GMAC, link state is retrieved via MDC/MDIO and handled in software, while ETHSW relies on PHY_LINK pins for both CPU-assisted operation and switch-only data paths that do not involve the host. Hardware PHY_LINK signals are also critical for fast reaction to link-down events, for example when running redundancy protocols such as Device Level Ring (DLR), where rapid detection of cable faults is required to switch to an alternate path without software latency. Parse the requested polarity from DT, accumulate the configuration during probing, and apply it to the MIIC_PHY_LINK register once hardware initialization is complete, when the registers can be safely modified. Handle SoC-specific bit layout differences between RZ/N1 and RZ/T2H/N2H within the driver. Signed-off-by: Lad Prabhakar --- v2->v3: - Updated commit message - Renamed DT property from renesas,miic-phylink-active-low to renesas,miic-phy-link-active-low. - Simplified the PHY_LINK configuration parsing logic in the driver as suggested. v1->v2: - No changes. --- drivers/net/pcs/pcs-rzn1-miic.c | 105 +++++++++++++++++++++++++++++++- 1 file changed, 102 insertions(+), 3 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-mii= c.c index 885f17c32643..8d7f82c1df2f 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -28,6 +28,8 @@ =20 #define MIIC_MODCTRL 0x8 =20 +#define MIIC_PHY_LINK 0x14 + #define MIIC_CONVCTRL(port) (0x100 + (port) * 4) =20 #define MIIC_CONVCTRL_CONV_SPEED GENMASK(1, 0) @@ -177,6 +179,16 @@ static const char * const rzt2h_reset_ids[] =3D { "crst", }; =20 +/** + * struct miic_phy_link_cfg - MIIC PHY_LINK configuration + * @mask: Mask of phy_link bits + * @val: Value of phy_link bits + */ +struct miic_phy_link_cfg { + u32 mask; + u32 val; +}; + /** * struct miic - MII converter structure * @base: base address of the MII converter @@ -184,6 +196,7 @@ static const char * const rzt2h_reset_ids[] =3D { * @lock: Lock used for read-modify-write access * @rsts: Reset controls for the MII converter * @of_data: Pointer to OF data + * @link_cfg: MIIC PHY_LINK configuration */ struct miic { void __iomem *base; @@ -191,6 +204,12 @@ struct miic { spinlock_t lock; struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS]; const struct miic_of_data *of_data; + struct miic_phy_link_cfg link_cfg; +}; + +enum miic_type { + MIIC_TYPE_RZN1, + MIIC_TYPE_RZT2H, }; =20 /** @@ -210,6 +229,7 @@ struct miic { * @init_unlock_lock_regs: Flag to indicate if registers need to be unlock= ed * before access. * @miic_write: Function pointer to write a value to a MIIC register + * @type: Type of MIIC */ struct miic_of_data { struct modctrl_match *match_table; @@ -226,6 +246,7 @@ struct miic_of_data { u8 reset_count; bool init_unlock_lock_regs; void (*miic_write)(struct miic *miic, int offset, u32 value); + enum miic_type type; }; =20 /** @@ -581,10 +602,79 @@ static int miic_match_dt_conf(struct miic *miic, s8 *= dt_val, u32 *mode_cfg) return -EINVAL; } =20 +static void miic_configure_phy_link(struct miic *miic, u32 conf, + u32 port, bool active_low) +{ + bool polarity_active_high; + u32 mask, shift; + + /* determine shift and polarity for this conf */ + if (miic->of_data->type =3D=3D MIIC_TYPE_RZN1) { + switch (conf) { + /* switch ports =3D> bits [3:0] (shift 0), active when low */ + case MIIC_SWITCH_PORTA: + case MIIC_SWITCH_PORTB: + case MIIC_SWITCH_PORTC: + case MIIC_SWITCH_PORTD: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* EtherCAT ports =3D> bits [7:4] (shift 4), active when high */ + case MIIC_ETHERCAT_PORTA: + case MIIC_ETHERCAT_PORTB: + case MIIC_ETHERCAT_PORTC: + shift =3D 4; + polarity_active_high =3D true; + break; + + /* Sercos ports =3D> bits [11:8] (shift 8), active when high */ + case MIIC_SERCOS_PORTA: + case MIIC_SERCOS_PORTB: + shift =3D 8; + polarity_active_high =3D true; + break; + + default: + return; + } + } else { + switch (conf) { + /* ETHSW ports =3D> bits [3:0] (shift 0), active when low */ + case ETHSS_ETHSW_PORT0: + case ETHSS_ETHSW_PORT1: + case ETHSS_ETHSW_PORT2: + shift =3D 0; + polarity_active_high =3D false; + break; + + /* ESC ports =3D> bits [7:4] (shift 4), active when high */ + case ETHSS_ESC_PORT0: + case ETHSS_ESC_PORT1: + case ETHSS_ESC_PORT2: + shift =3D 4; + polarity_active_high =3D true; + break; + + default: + return; + } + } + + mask =3D BIT(port + shift); + + miic->link_cfg.mask |=3D mask; + if (polarity_active_high !=3D active_low) + miic->link_cfg.val |=3D mask; + else + miic->link_cfg.val &=3D ~mask; +} + static int miic_parse_dt(struct miic *miic, u32 *mode_cfg) { struct device_node *np =3D miic->dev->of_node; struct device_node *conv; + bool active_low; int port, ret; s8 *dt_val; u32 conf; @@ -603,10 +693,15 @@ static int miic_parse_dt(struct miic *miic, u32 *mode= _cfg) if (of_property_read_u32(conv, "reg", &port)) continue; =20 + if (of_property_read_u32(conv, "renesas,miic-input", &conf)) + continue; + /* Adjust for 0 based index */ - port +=3D !miic->of_data->miic_port_start; - if (of_property_read_u32(conv, "renesas,miic-input", &conf) =3D=3D 0) - dt_val[port] =3D conf; + dt_val[port + !miic->of_data->miic_port_start] =3D conf; + + active_low =3D of_property_read_bool(conv, "renesas,miic-phy-link-active= -low"); + + miic_configure_phy_link(miic, conf, port, active_low); } =20 ret =3D miic_match_dt_conf(miic, dt_val, mode_cfg); @@ -696,6 +791,8 @@ static int miic_probe(struct platform_device *pdev) if (ret) goto disable_runtime_pm; =20 + miic_reg_rmw(miic, MIIC_PHY_LINK, miic->link_cfg.mask, miic->link_cfg.val= ); + /* miic_create() relies on that fact that data are attached to the * platform device to determine if the driver is ready so this needs to * be the last thing to be done after everything is initialized @@ -729,6 +826,7 @@ static struct miic_of_data rzn1_miic_of_data =3D { .sw_mode_mask =3D GENMASK(4, 0), .init_unlock_lock_regs =3D true, .miic_write =3D miic_reg_writel_unlocked, + .type =3D MIIC_TYPE_RZN1, }; =20 static struct miic_of_data rzt2h_miic_of_data =3D { @@ -745,6 +843,7 @@ static struct miic_of_data rzt2h_miic_of_data =3D { .reset_ids =3D rzt2h_reset_ids, .reset_count =3D ARRAY_SIZE(rzt2h_reset_ids), .miic_write =3D miic_reg_writel_locked, + .type =3D MIIC_TYPE_RZT2H, }; =20 static const struct of_device_id miic_of_mtable[] =3D { --=20 2.52.0